Seregon/Hermes

Hermes/Dyforge is a program written in c++ allows you to inject a dll that can analyze all processes in a program, can be used for mod and reverse engeneering

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DyMain/include/capstone/xcore.h
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Hermes / DyMain / include / capstone / xcore.h
1#ifndef CAPSTONE_XCORE_H
2#define CAPSTONE_XCORE_H
3 
4/* Capstone Disassembly Engine */
5/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014-2015 */
6 
7#ifdef __cplusplus
8extern "C" {
9#endif
10 
11#include "platform.h"
12#include "cs_operand.h"
13 
14#ifdef _MSC_VER
15#pragma warning(disable:4201)
16#endif
17 
18/// Operand type for instruction's operands
19typedef enum xcore_op_type {
20 XCORE_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized).
21 XCORE_OP_REG = CS_OP_REG, ///< = CS_OP_REG (Register operand).
22 XCORE_OP_IMM = CS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
23 XCORE_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
24} xcore_op_type;
25 
26/// XCore registers
27typedef enum xcore_reg {
28 XCORE_REG_INVALID = 0,
29 
30 XCORE_REG_CP,
31 XCORE_REG_DP,
32 XCORE_REG_LR,
33 XCORE_REG_SP,
34 XCORE_REG_R0,
35 XCORE_REG_R1,
36 XCORE_REG_R2,
37 XCORE_REG_R3,
38 XCORE_REG_R4,
39 XCORE_REG_R5,
40 XCORE_REG_R6,
41 XCORE_REG_R7,
42 XCORE_REG_R8,
43 XCORE_REG_R9,
44 XCORE_REG_R10,
45 XCORE_REG_R11,
46 
47 // pseudo registers
48 XCORE_REG_PC, ///< pc
49 
50 // internal thread registers
51 // see The-XMOS-XS1-Architecture(X7879A).pdf
52 XCORE_REG_SCP, ///< save pc
53 XCORE_REG_SSR, //< save status
54 XCORE_REG_ET, //< exception type
55 XCORE_REG_ED, //< exception data
56 XCORE_REG_SED, //< save exception data
57 XCORE_REG_KEP, //< kernel entry pointer
58 XCORE_REG_KSP, //< kernel stack pointer
59 XCORE_REG_ID, //< thread ID
60 
61 XCORE_REG_ENDING, // <-- mark the end of the list of registers
62} xcore_reg;
63 
64/// Instruction's operand referring to memory
65/// This is associated with XCORE_OP_MEM operand type above
66typedef struct xcore_op_mem {
67 uint8_t base; ///< base register, can be safely interpreted as
68 ///< a value of type `xcore_reg`, but it is only
69 ///< one byte wide
70 uint8_t index; ///< index register, same conditions apply here
71 int32_t disp; ///< displacement/offset value
72 int direct; ///< +1: forward, -1: backward
73} xcore_op_mem;
74 
75/// Instruction operand
76typedef struct cs_xcore_op {
77 xcore_op_type type; ///< operand type
78 union {
79 xcore_reg reg; ///< register value for REG operand
80 int32_t imm; ///< immediate value for IMM operand
81 xcore_op_mem mem; ///< base/disp value for MEM operand
82 };
83} cs_xcore_op;
84 
85/// Instruction structure
86typedef struct cs_xcore {
87 /// Number of operands of this instruction,
88 /// or 0 when instruction has no operand.
89 uint8_t op_count;
90 cs_xcore_op operands[8]; ///< operands for this instruction.
91} cs_xcore;
92 
93/// XCore instruction
94typedef enum xcore_insn {
95 XCORE_INS_INVALID = 0,
96 
97 XCORE_INS_ADD,
98 XCORE_INS_ANDNOT,
99 XCORE_INS_AND,
100 XCORE_INS_ASHR,
101 XCORE_INS_BAU,
102 XCORE_INS_BITREV,
103 XCORE_INS_BLA,
104 XCORE_INS_BLAT,
105 XCORE_INS_BL,
106 XCORE_INS_BF,
107 XCORE_INS_BT,
108 XCORE_INS_BU,
109 XCORE_INS_BRU,
110 XCORE_INS_BYTEREV,
111 XCORE_INS_CHKCT,
112 XCORE_INS_CLRE,
113 XCORE_INS_CLRPT,
114 XCORE_INS_CLRSR,
115 XCORE_INS_CLZ,
116 XCORE_INS_CRC8,
117 XCORE_INS_CRC32,
118 XCORE_INS_DCALL,
119 XCORE_INS_DENTSP,
120 XCORE_INS_DGETREG,
121 XCORE_INS_DIVS,
122 XCORE_INS_DIVU,
123 XCORE_INS_DRESTSP,
124 XCORE_INS_DRET,
125 XCORE_INS_ECALLF,
126 XCORE_INS_ECALLT,
127 XCORE_INS_EDU,
128 XCORE_INS_EEF,
129 XCORE_INS_EET,
130 XCORE_INS_EEU,
131 XCORE_INS_ENDIN,
132 XCORE_INS_ENTSP,
133 XCORE_INS_EQ,
134 XCORE_INS_EXTDP,
135 XCORE_INS_EXTSP,
136 XCORE_INS_FREER,
137 XCORE_INS_FREET,
138 XCORE_INS_GETD,
139 XCORE_INS_GET,
140 XCORE_INS_GETN,
141 XCORE_INS_GETR,
142 XCORE_INS_GETSR,
143 XCORE_INS_GETST,
144 XCORE_INS_GETTS,
145 XCORE_INS_INCT,
146 XCORE_INS_INIT,
147 XCORE_INS_INPW,
148 XCORE_INS_INSHR,
149 XCORE_INS_INT,
150 XCORE_INS_IN,
151 XCORE_INS_KCALL,
152 XCORE_INS_KENTSP,
153 XCORE_INS_KRESTSP,
154 XCORE_INS_KRET,
155 XCORE_INS_LADD,
156 XCORE_INS_LD16S,
157 XCORE_INS_LD8U,
158 XCORE_INS_LDA16,
159 XCORE_INS_LDAP,
160 XCORE_INS_LDAW,
161 XCORE_INS_LDC,
162 XCORE_INS_LDW,
163 XCORE_INS_LDIVU,
164 XCORE_INS_LMUL,
165 XCORE_INS_LSS,
166 XCORE_INS_LSUB,
167 XCORE_INS_LSU,
168 XCORE_INS_MACCS,
169 XCORE_INS_MACCU,
170 XCORE_INS_MJOIN,
171 XCORE_INS_MKMSK,
172 XCORE_INS_MSYNC,
173 XCORE_INS_MUL,
174 XCORE_INS_NEG,
175 XCORE_INS_NOT,
176 XCORE_INS_OR,
177 XCORE_INS_OUTCT,
178 XCORE_INS_OUTPW,
179 XCORE_INS_OUTSHR,
180 XCORE_INS_OUTT,
181 XCORE_INS_OUT,
182 XCORE_INS_PEEK,
183 XCORE_INS_REMS,
184 XCORE_INS_REMU,
185 XCORE_INS_RETSP,
186 XCORE_INS_SETCLK,
187 XCORE_INS_SET,
188 XCORE_INS_SETC,
189 XCORE_INS_SETD,
190 XCORE_INS_SETEV,
191 XCORE_INS_SETN,
192 XCORE_INS_SETPSC,
193 XCORE_INS_SETPT,
194 XCORE_INS_SETRDY,
195 XCORE_INS_SETSR,
196 XCORE_INS_SETTW,
197 XCORE_INS_SETV,
198 XCORE_INS_SEXT,
199 XCORE_INS_SHL,
200 XCORE_INS_SHR,
201 XCORE_INS_SSYNC,
202 XCORE_INS_ST16,
203 XCORE_INS_ST8,
204 XCORE_INS_STW,
205 XCORE_INS_SUB,
206 XCORE_INS_SYNCR,
207 XCORE_INS_TESTCT,
208 XCORE_INS_TESTLCL,
209 XCORE_INS_TESTWCT,
210 XCORE_INS_TSETMR,
211 XCORE_INS_START,
212 XCORE_INS_WAITEF,
213 XCORE_INS_WAITET,
214 XCORE_INS_WAITEU,
215 XCORE_INS_XOR,
216 XCORE_INS_ZEXT,
217 
218 XCORE_INS_ENDING, // <-- mark the end of the list of instructions
219} xcore_insn;
220 
221/// Group of XCore instructions
222typedef enum xcore_insn_group {
223 XCORE_GRP_INVALID = 0, ///< = CS_GRP_INVALID
224 
225 // Generic groups
226 // all jump instructions (conditional+direct+indirect jumps)
227 XCORE_GRP_JUMP, ///< = CS_GRP_JUMP
228 
229 XCORE_GRP_ENDING, // <-- mark the end of the list of groups
230} xcore_insn_group;
231 
232#ifdef __cplusplus
233}
234#endif
235 
236#endif
237