Seregon/Hermes

Hermes/Dyforge is a program written in c++ allows you to inject a dll that can analyze all processes in a program, can be used for mod and reverse engeneering

C/3.8 KB/No license
DyMain/include/capstone/tms320c64x.h
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Hermes / DyMain / include / capstone / tms320c64x.h
1/* Capstone Disassembly Engine */
2/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
3 
4#ifndef CAPSTONE_TMS320C64X_H
5#define CAPSTONE_TMS320C64X_H
6 
7#ifdef __cplusplus
8extern "C" {
9#endif
10 
11#include <stdint.h>
12#include "platform.h"
13#include "cs_operand.h"
14 
15#ifdef _MSC_VER
16#pragma warning(disable:4201)
17#endif
18 
19typedef enum tms320c64x_op_type {
20 TMS320C64X_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized).
21 TMS320C64X_OP_REG = CS_OP_REG, ///< = CS_OP_REG (Register operand).
22 TMS320C64X_OP_IMM = CS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
23 TMS320C64X_OP_REGPAIR = CS_OP_SPECIAL + 0, ///< Register pair for double word ops
24 TMS320C64X_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
25} tms320c64x_op_type;
26 
27typedef enum tms320c64x_mem_disp {
28 TMS320C64X_MEM_DISP_INVALID = 0,
29 TMS320C64X_MEM_DISP_CONSTANT,
30 TMS320C64X_MEM_DISP_REGISTER,
31} tms320c64x_mem_disp;
32 
33typedef enum tms320c64x_mem_dir {
34 TMS320C64X_MEM_DIR_INVALID = 0,
35 TMS320C64X_MEM_DIR_FW,
36 TMS320C64X_MEM_DIR_BW,
37} tms320c64x_mem_dir;
38 
39typedef enum tms320c64x_mem_mod {
40 TMS320C64X_MEM_MOD_INVALID = 0,
41 TMS320C64X_MEM_MOD_NO,
42 TMS320C64X_MEM_MOD_PRE,
43 TMS320C64X_MEM_MOD_POST,
44} tms320c64x_mem_mod;
45 
46typedef struct tms320c64x_op_mem {
47 unsigned int base; ///< base register
48 unsigned int disp; ///< displacement/offset value
49 unsigned int unit; ///< unit of base and offset register
50 unsigned int scaled; ///< offset scaled
51 unsigned int disptype; ///< displacement type
52 unsigned int direction; ///< direction
53 unsigned int modify; ///< modification
54} tms320c64x_op_mem;
55 
56typedef struct cs_tms320c64x_op {
57 tms320c64x_op_type type; ///< operand type
58 union {
59 unsigned int reg; ///< register value for REG operand or first register for REGPAIR operand
60 int32_t imm; ///< immediate value for IMM operand
61 tms320c64x_op_mem mem; ///< base/disp value for MEM operand
62 };
63} cs_tms320c64x_op;
64 
65typedef struct cs_tms320c64x {
66 uint8_t op_count;
67 cs_tms320c64x_op operands[8]; ///< operands for this instruction.
68 struct {
69 unsigned int reg;
70 unsigned int zero;
71 } condition;
72 struct {
73 unsigned int unit;
74 unsigned int side;
75 unsigned int crosspath;
76 } funit;
77 unsigned int parallel;
78} cs_tms320c64x;
79 
80typedef enum tms320c64x_reg {
81 TMS320C64X_REG_INVALID = 0,
82 
83 TMS320C64X_REG_AMR,
84 TMS320C64X_REG_CSR,
85 TMS320C64X_REG_DIER,
86 TMS320C64X_REG_DNUM,
87 TMS320C64X_REG_ECR,
88 TMS320C64X_REG_GFPGFR,
89 TMS320C64X_REG_GPLYA,
90 TMS320C64X_REG_GPLYB,
91 TMS320C64X_REG_ICR,
92 TMS320C64X_REG_IER,
93 TMS320C64X_REG_IERR,
94 TMS320C64X_REG_ILC,
95 TMS320C64X_REG_IRP,
96 TMS320C64X_REG_ISR,
97 TMS320C64X_REG_ISTP,
98 TMS320C64X_REG_ITSR,
99 TMS320C64X_REG_NRP,
100 TMS320C64X_REG_NTSR,
101 TMS320C64X_REG_REP,
102 TMS320C64X_REG_RILC,
103 TMS320C64X_REG_SSR,
104 TMS320C64X_REG_TSCH,
105 TMS320C64X_REG_TSCL,
106 TMS320C64X_REG_TSR,
107 TMS320C64X_REG_A0,
108 TMS320C64X_REG_A1,
109 TMS320C64X_REG_A2,
110 TMS320C64X_REG_A3,
111 TMS320C64X_REG_A4,
112 TMS320C64X_REG_A5,
113 TMS320C64X_REG_A6,
114 TMS320C64X_REG_A7,
115 TMS320C64X_REG_A8,
116 TMS320C64X_REG_A9,
117 TMS320C64X_REG_A10,
118 TMS320C64X_REG_A11,
119 TMS320C64X_REG_A12,
120 TMS320C64X_REG_A13,
121 TMS320C64X_REG_A14,
122 TMS320C64X_REG_A15,
123 TMS320C64X_REG_A16,
124 TMS320C64X_REG_A17,
125 TMS320C64X_REG_A18,
126 TMS320C64X_REG_A19,
127 TMS320C64X_REG_A20,
128 TMS320C64X_REG_A21,
129 TMS320C64X_REG_A22,
130 TMS320C64X_REG_A23,
131 TMS320C64X_REG_A24,
132 TMS320C64X_REG_A25,
133 TMS320C64X_REG_A26,
134 TMS320C64X_REG_A27,
135 TMS320C64X_REG_A28,
136 TMS320C64X_REG_A29,
137 TMS320C64X_REG_A30,
138 TMS320C64X_REG_A31,
139 TMS320C64X_REG_B0,
140 TMS320C64X_REG_B1,
141 TMS320C64X_REG_B2,
142 TMS320C64X_REG_B3,
143 TMS320C64X_REG_B4,
144 TMS320C64X_REG_B5,
145 TMS320C64X_REG_B6,
146 TMS320C64X_REG_B7,
147 TMS320C64X_REG_B8,
148 TMS320C64X_REG_B9,
149 TMS320C64X_REG_B10,
150 TMS320C64X_REG_B11,
151 TMS320C64X_REG_B12,
152 TMS320C64X_REG_B13,
153 TMS320C64X_REG_B14,
154 TMS320C64X_REG_B15,
155 TMS320C64X_REG_B16,
156 TMS320C64X_REG_B17,
157 TMS320C64X_REG_B18,
158 TMS320C64X_REG_B19,
159 TMS320C64X_REG_B20,
160 TMS320C64X_REG_B21,
161 TMS320C64X_REG_B22,
162 TMS320C64X_REG_B23,
163 TMS320C64X_REG_B24,
164 TMS320C64X_REG_B25,
165 TMS320C64X_REG_B26,
166 TMS320C64X_REG_B27,
167 TMS320C64X_REG_B28,
168 TMS320C64X_REG_B29,
169 TMS320C64X_REG_B30,
170 TMS320C64X_REG_B31,
171 TMS320C64X_REG_PCE1,
172 
173 TMS320C64X_REG_ENDING, // <-- mark the end of the list of registers
174 
175 // Alias registers
176 TMS320C64X_REG_EFR = TMS320C64X_REG_ECR,
177 TMS320C64X_REG_IFR = TMS320C64X_REG_ISR,
178} tms320c64x_reg;
179 
180typedef enum tms320c64x_insn {
181 TMS320C64X_INS_INVALID = 0,
182 
183 TMS320C64X_INS_ABS,
184 TMS320C64X_INS_ABS2,
185 TMS320C64X_INS_ADD,
186 TMS320C64X_INS_ADD2,
187 TMS320C64X_INS_ADD4,
188 TMS320C64X_INS_ADDAB,
189 TMS320C64X_INS_ADDAD,
190 TMS320C64X_INS_ADDAH,
191 TMS320C64X_INS_ADDAW,
192 TMS320C64X_INS_ADDK,
193 TMS320C64X_INS_ADDKPC,
194 TMS320C64X_INS_ADDU,
195 TMS320C64X_INS_AND,
196 TMS320C64X_INS_ANDN,
197 TMS320C64X_INS_AVG2,
198 TMS320C64X_INS_AVGU4,
199 TMS320C64X_INS_B,
200 TMS320C64X_INS_BDEC,
201 TMS320C64X_INS_BITC4,
202 TMS320C64X_INS_BNOP,
203 TMS320C64X_INS_BPOS,
204 TMS320C64X_INS_CLR,
205 TMS320C64X_INS_CMPEQ,
206 TMS320C64X_INS_CMPEQ2,
207 TMS320C64X_INS_CMPEQ4,
208 TMS320C64X_INS_CMPGT,
209 TMS320C64X_INS_CMPGT2,
210 TMS320C64X_INS_CMPGTU4,
211 TMS320C64X_INS_CMPLT,
212 TMS320C64X_INS_CMPLTU,
213 TMS320C64X_INS_DEAL,
214 TMS320C64X_INS_DOTP2,
215 TMS320C64X_INS_DOTPN2,
216 TMS320C64X_INS_DOTPNRSU2,
217 TMS320C64X_INS_DOTPRSU2,
218 TMS320C64X_INS_DOTPSU4,
219 TMS320C64X_INS_DOTPU4,
220 TMS320C64X_INS_EXT,
221 TMS320C64X_INS_EXTU,
222 TMS320C64X_INS_GMPGTU,
223 TMS320C64X_INS_GMPY4,
224 TMS320C64X_INS_LDB,
225 TMS320C64X_INS_LDBU,
226 TMS320C64X_INS_LDDW,
227 TMS320C64X_INS_LDH,
228 TMS320C64X_INS_LDHU,
229 TMS320C64X_INS_LDNDW,
230 TMS320C64X_INS_LDNW,
231 TMS320C64X_INS_LDW,
232 TMS320C64X_INS_LMBD,
233 TMS320C64X_INS_MAX2,
234 TMS320C64X_INS_MAXU4,
235 TMS320C64X_INS_MIN2,
236 TMS320C64X_INS_MINU4,
237 TMS320C64X_INS_MPY,
238 TMS320C64X_INS_MPY2,
239 TMS320C64X_INS_MPYH,
240 TMS320C64X_INS_MPYHI,
241 TMS320C64X_INS_MPYHIR,
242 TMS320C64X_INS_MPYHL,
243 TMS320C64X_INS_MPYHLU,
244 TMS320C64X_INS_MPYHSLU,
245 TMS320C64X_INS_MPYHSU,
246 TMS320C64X_INS_MPYHU,
247 TMS320C64X_INS_MPYHULS,
248 TMS320C64X_INS_MPYHUS,
249 TMS320C64X_INS_MPYLH,
250 TMS320C64X_INS_MPYLHU,
251 TMS320C64X_INS_MPYLI,
252 TMS320C64X_INS_MPYLIR,
253 TMS320C64X_INS_MPYLSHU,
254 TMS320C64X_INS_MPYLUHS,
255 TMS320C64X_INS_MPYSU,
256 TMS320C64X_INS_MPYSU4,
257 TMS320C64X_INS_MPYU,
258 TMS320C64X_INS_MPYU4,
259 TMS320C64X_INS_MPYUS,
260 TMS320C64X_INS_MVC,
261 TMS320C64X_INS_MVD,
262 TMS320C64X_INS_MVK,
263 TMS320C64X_INS_MVKL,
264 TMS320C64X_INS_MVKLH,
265 TMS320C64X_INS_NOP,
266 TMS320C64X_INS_NORM,
267 TMS320C64X_INS_OR,
268 TMS320C64X_INS_PACK2,
269 TMS320C64X_INS_PACKH2,
270 TMS320C64X_INS_PACKH4,
271 TMS320C64X_INS_PACKHL2,
272 TMS320C64X_INS_PACKL4,
273 TMS320C64X_INS_PACKLH2,
274 TMS320C64X_INS_ROTL,
275 TMS320C64X_INS_SADD,
276 TMS320C64X_INS_SADD2,
277 TMS320C64X_INS_SADDU4,
278 TMS320C64X_INS_SADDUS2,
279 TMS320C64X_INS_SAT,
280 TMS320C64X_INS_SET,
281 TMS320C64X_INS_SHFL,
282 TMS320C64X_INS_SHL,
283 TMS320C64X_INS_SHLMB,
284 TMS320C64X_INS_SHR,
285 TMS320C64X_INS_SHR2,
286 TMS320C64X_INS_SHRMB,
287 TMS320C64X_INS_SHRU,
288 TMS320C64X_INS_SHRU2,
289 TMS320C64X_INS_SMPY,
290 TMS320C64X_INS_SMPY2,
291 TMS320C64X_INS_SMPYH,
292 TMS320C64X_INS_SMPYHL,
293 TMS320C64X_INS_SMPYLH,
294 TMS320C64X_INS_SPACK2,
295 TMS320C64X_INS_SPACKU4,
296 TMS320C64X_INS_SSHL,
297 TMS320C64X_INS_SSHVL,
298 TMS320C64X_INS_SSHVR,
299 TMS320C64X_INS_SSUB,
300 TMS320C64X_INS_STB,
301 TMS320C64X_INS_STDW,
302 TMS320C64X_INS_STH,
303 TMS320C64X_INS_STNDW,
304 TMS320C64X_INS_STNW,
305 TMS320C64X_INS_STW,
306 TMS320C64X_INS_SUB,
307 TMS320C64X_INS_SUB2,
308 TMS320C64X_INS_SUB4,
309 TMS320C64X_INS_SUBAB,
310 TMS320C64X_INS_SUBABS4,
311 TMS320C64X_INS_SUBAH,
312 TMS320C64X_INS_SUBAW,
313 TMS320C64X_INS_SUBC,
314 TMS320C64X_INS_SUBU,
315 TMS320C64X_INS_SWAP4,
316 TMS320C64X_INS_UNPKHU4,
317 TMS320C64X_INS_UNPKLU4,
318 TMS320C64X_INS_XOR,
319 TMS320C64X_INS_XPND2,
320 TMS320C64X_INS_XPND4,
321 // Aliases
322 TMS320C64X_INS_IDLE,
323 TMS320C64X_INS_MV,
324 TMS320C64X_INS_NEG,
325 TMS320C64X_INS_NOT,
326 TMS320C64X_INS_SWAP2,
327 TMS320C64X_INS_ZERO,
328 
329 TMS320C64X_INS_ENDING, // <-- mark the end of the list of instructions
330} tms320c64x_insn;
331 
332typedef enum tms320c64x_insn_group {
333 TMS320C64X_GRP_INVALID = 0, ///< = CS_GRP_INVALID
334 
335 TMS320C64X_GRP_JUMP, ///< = CS_GRP_JUMP
336 
337 TMS320C64X_GRP_FUNIT_D = 128,
338 TMS320C64X_GRP_FUNIT_L,
339 TMS320C64X_GRP_FUNIT_M,
340 TMS320C64X_GRP_FUNIT_S,
341 TMS320C64X_GRP_FUNIT_NO,
342 
343 TMS320C64X_GRP_ENDING, // <-- mark the end of the list of groups
344} tms320c64x_insn_group;
345 
346typedef enum tms320c64x_funit {
347 TMS320C64X_FUNIT_INVALID = 0,
348 TMS320C64X_FUNIT_D,
349 TMS320C64X_FUNIT_L,
350 TMS320C64X_FUNIT_M,
351 TMS320C64X_FUNIT_S,
352 TMS320C64X_FUNIT_NO
353} tms320c64x_funit;
354 
355#ifdef __cplusplus
356}
357#endif
358 
359#endif
360 
361