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| 1 | #ifndef CAPSTONE_SPARC_H |
| 2 | #define CAPSTONE_SPARC_H |
| 3 | |
| 4 | /* Capstone Disassembly Engine */ |
| 5 | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014-2015 */ |
| 6 | |
| 7 | #ifdef __cplusplus |
| 8 | extern "C" { |
| 9 | #endif |
| 10 | |
| 11 | #include "platform.h" |
| 12 | #include "cs_operand.h" |
| 13 | |
| 14 | // GCC SPARC toolchain has a default macro called "sparc" which breaks |
| 15 | // compilation |
| 16 | #undef sparc |
| 17 | |
| 18 | #ifdef _MSC_VER |
| 19 | #pragma warning(disable:4201) |
| 20 | #endif |
| 21 | |
| 22 | /// Enums corresponding to Sparc condition codes, both icc's and fcc's. |
| 23 | typedef enum sparc_cc { |
| 24 | SPARC_CC_INVALID = 0, ///< invalid CC (default) |
| 25 | // Integer condition codes |
| 26 | SPARC_CC_ICC_A = 8+256, ///< Always |
| 27 | SPARC_CC_ICC_N = 0+256, ///< Never |
| 28 | SPARC_CC_ICC_NE = 9+256, ///< Not Equal |
| 29 | SPARC_CC_ICC_E = 1+256, ///< Equal |
| 30 | SPARC_CC_ICC_G = 10+256, ///< Greater |
| 31 | SPARC_CC_ICC_LE = 2+256, ///< Less or Equal |
| 32 | SPARC_CC_ICC_GE = 11+256, ///< Greater or Equal |
| 33 | SPARC_CC_ICC_L = 3+256, ///< Less |
| 34 | SPARC_CC_ICC_GU = 12+256, ///< Greater Unsigned |
| 35 | SPARC_CC_ICC_LEU = 4+256, ///< Less or Equal Unsigned |
| 36 | SPARC_CC_ICC_CC = 13+256, ///< Carry Clear/Great or Equal Unsigned |
| 37 | SPARC_CC_ICC_CS = 5+256, ///< Carry Set/Less Unsigned |
| 38 | SPARC_CC_ICC_POS = 14+256, ///< Positive |
| 39 | SPARC_CC_ICC_NEG = 6+256, ///< Negative |
| 40 | SPARC_CC_ICC_VC = 15+256, ///< Overflow Clear |
| 41 | SPARC_CC_ICC_VS = 7+256, ///< Overflow Set |
| 42 | |
| 43 | // Floating condition codes |
| 44 | SPARC_CC_FCC_A = 8+16+256, ///< Always |
| 45 | SPARC_CC_FCC_N = 0+16+256, ///< Never |
| 46 | SPARC_CC_FCC_U = 7+16+256, ///< Unordered |
| 47 | SPARC_CC_FCC_G = 6+16+256, ///< Greater |
| 48 | SPARC_CC_FCC_UG = 5+16+256, ///< Unordered or Greater |
| 49 | SPARC_CC_FCC_L = 4+16+256, ///< Less |
| 50 | SPARC_CC_FCC_UL = 3+16+256, ///< Unordered or Less |
| 51 | SPARC_CC_FCC_LG = 2+16+256, ///< Less or Greater |
| 52 | SPARC_CC_FCC_NE = 1+16+256, ///< Not Equal |
| 53 | SPARC_CC_FCC_E = 9+16+256, ///< Equal |
| 54 | SPARC_CC_FCC_UE = 10+16+256, ///< Unordered or Equal |
| 55 | SPARC_CC_FCC_GE = 11+16+256, ///< Greater or Equal |
| 56 | SPARC_CC_FCC_UGE = 12+16+256, ///< Unordered or Greater or Equal |
| 57 | SPARC_CC_FCC_LE = 13+16+256, ///< Less or Equal |
| 58 | SPARC_CC_FCC_ULE = 14+16+256, ///< Unordered or Less or Equal |
| 59 | SPARC_CC_FCC_O = 15+16+256, ///< Ordered |
| 60 | } sparc_cc; |
| 61 | |
| 62 | /// Branch hint |
| 63 | typedef enum sparc_hint { |
| 64 | SPARC_HINT_INVALID = 0, ///< no hint |
| 65 | SPARC_HINT_A = 1 << 0, ///< annul delay slot instruction |
| 66 | SPARC_HINT_PT = 1 << 1, ///< branch taken |
| 67 | SPARC_HINT_PN = 1 << 2, ///< branch NOT taken |
| 68 | SPARC_HINT_A_PN = SPARC_HINT_A | SPARC_HINT_PN, |
| 69 | SPARC_HINT_A_PT = SPARC_HINT_A | SPARC_HINT_PT, |
| 70 | } sparc_hint; |
| 71 | |
| 72 | /// Operand type for instruction's operands |
| 73 | typedef enum sparc_op_type { |
| 74 | SPARC_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized). |
| 75 | SPARC_OP_REG = CS_OP_REG, ///< = CS_OP_REG (Register operand). |
| 76 | SPARC_OP_IMM = CS_OP_IMM, ///< = CS_OP_IMM (Immediate operand). |
| 77 | SPARC_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand). |
| 78 | } sparc_op_type; |
| 79 | |
| 80 | /// SPARC registers |
| 81 | typedef enum sparc_reg { |
| 82 | SPARC_REG_INVALID = 0, |
| 83 | |
| 84 | SPARC_REG_F0, |
| 85 | SPARC_REG_F1, |
| 86 | SPARC_REG_F2, |
| 87 | SPARC_REG_F3, |
| 88 | SPARC_REG_F4, |
| 89 | SPARC_REG_F5, |
| 90 | SPARC_REG_F6, |
| 91 | SPARC_REG_F7, |
| 92 | SPARC_REG_F8, |
| 93 | SPARC_REG_F9, |
| 94 | SPARC_REG_F10, |
| 95 | SPARC_REG_F11, |
| 96 | SPARC_REG_F12, |
| 97 | SPARC_REG_F13, |
| 98 | SPARC_REG_F14, |
| 99 | SPARC_REG_F15, |
| 100 | SPARC_REG_F16, |
| 101 | SPARC_REG_F17, |
| 102 | SPARC_REG_F18, |
| 103 | SPARC_REG_F19, |
| 104 | SPARC_REG_F20, |
| 105 | SPARC_REG_F21, |
| 106 | SPARC_REG_F22, |
| 107 | SPARC_REG_F23, |
| 108 | SPARC_REG_F24, |
| 109 | SPARC_REG_F25, |
| 110 | SPARC_REG_F26, |
| 111 | SPARC_REG_F27, |
| 112 | SPARC_REG_F28, |
| 113 | SPARC_REG_F29, |
| 114 | SPARC_REG_F30, |
| 115 | SPARC_REG_F31, |
| 116 | SPARC_REG_F32, |
| 117 | SPARC_REG_F34, |
| 118 | SPARC_REG_F36, |
| 119 | SPARC_REG_F38, |
| 120 | SPARC_REG_F40, |
| 121 | SPARC_REG_F42, |
| 122 | SPARC_REG_F44, |
| 123 | SPARC_REG_F46, |
| 124 | SPARC_REG_F48, |
| 125 | SPARC_REG_F50, |
| 126 | SPARC_REG_F52, |
| 127 | SPARC_REG_F54, |
| 128 | SPARC_REG_F56, |
| 129 | SPARC_REG_F58, |
| 130 | SPARC_REG_F60, |
| 131 | SPARC_REG_F62, |
| 132 | SPARC_REG_FCC0, // Floating condition codes |
| 133 | SPARC_REG_FCC1, |
| 134 | SPARC_REG_FCC2, |
| 135 | SPARC_REG_FCC3, |
| 136 | SPARC_REG_FP, |
| 137 | SPARC_REG_G0, |
| 138 | SPARC_REG_G1, |
| 139 | SPARC_REG_G2, |
| 140 | SPARC_REG_G3, |
| 141 | SPARC_REG_G4, |
| 142 | SPARC_REG_G5, |
| 143 | SPARC_REG_G6, |
| 144 | SPARC_REG_G7, |
| 145 | SPARC_REG_I0, |
| 146 | SPARC_REG_I1, |
| 147 | SPARC_REG_I2, |
| 148 | SPARC_REG_I3, |
| 149 | SPARC_REG_I4, |
| 150 | SPARC_REG_I5, |
| 151 | SPARC_REG_I7, |
| 152 | SPARC_REG_ICC, // Integer condition codes |
| 153 | SPARC_REG_L0, |
| 154 | SPARC_REG_L1, |
| 155 | SPARC_REG_L2, |
| 156 | SPARC_REG_L3, |
| 157 | SPARC_REG_L4, |
| 158 | SPARC_REG_L5, |
| 159 | SPARC_REG_L6, |
| 160 | SPARC_REG_L7, |
| 161 | SPARC_REG_O0, |
| 162 | SPARC_REG_O1, |
| 163 | SPARC_REG_O2, |
| 164 | SPARC_REG_O3, |
| 165 | SPARC_REG_O4, |
| 166 | SPARC_REG_O5, |
| 167 | SPARC_REG_O7, |
| 168 | SPARC_REG_SP, |
| 169 | SPARC_REG_Y, |
| 170 | |
| 171 | // special register |
| 172 | SPARC_REG_XCC, |
| 173 | |
| 174 | SPARC_REG_ENDING, // <-- mark the end of the list of registers |
| 175 | |
| 176 | // extras |
| 177 | SPARC_REG_O6 = SPARC_REG_SP, |
| 178 | SPARC_REG_I6 = SPARC_REG_FP, |
| 179 | } sparc_reg; |
| 180 | |
| 181 | /// Instruction's operand referring to memory |
| 182 | /// This is associated with SPARC_OP_MEM operand type above |
| 183 | typedef struct sparc_op_mem { |
| 184 | uint8_t base; ///< base register, can be safely interpreted as |
| 185 | ///< a value of type `sparc_reg`, but it is only |
| 186 | ///< one byte wide |
| 187 | uint8_t index; ///< index register, same conditions apply here |
| 188 | int32_t disp; ///< displacement/offset value |
| 189 | } sparc_op_mem; |
| 190 | |
| 191 | /// Instruction operand |
| 192 | typedef struct cs_sparc_op { |
| 193 | sparc_op_type type; ///< operand type |
| 194 | union { |
| 195 | sparc_reg reg; ///< register value for REG operand |
| 196 | int64_t imm; ///< immediate value for IMM operand |
| 197 | sparc_op_mem mem; ///< base/disp value for MEM operand |
| 198 | }; |
| 199 | } cs_sparc_op; |
| 200 | |
| 201 | /// Instruction structure |
| 202 | typedef struct cs_sparc { |
| 203 | sparc_cc cc; ///< code condition for this insn |
| 204 | sparc_hint hint; ///< branch hint: encoding as bitwise OR of sparc_hint. |
| 205 | /// Number of operands of this instruction, |
| 206 | /// or 0 when instruction has no operand. |
| 207 | uint8_t op_count; |
| 208 | cs_sparc_op operands[4]; ///< operands for this instruction. |
| 209 | } cs_sparc; |
| 210 | |
| 211 | /// SPARC instruction |
| 212 | typedef enum sparc_insn { |
| 213 | SPARC_INS_INVALID = 0, |
| 214 | |
| 215 | SPARC_INS_ADDCC, |
| 216 | SPARC_INS_ADDX, |
| 217 | SPARC_INS_ADDXCC, |
| 218 | SPARC_INS_ADDXC, |
| 219 | SPARC_INS_ADDXCCC, |
| 220 | SPARC_INS_ADD, |
| 221 | SPARC_INS_ALIGNADDR, |
| 222 | SPARC_INS_ALIGNADDRL, |
| 223 | SPARC_INS_ANDCC, |
| 224 | SPARC_INS_ANDNCC, |
| 225 | SPARC_INS_ANDN, |
| 226 | SPARC_INS_AND, |
| 227 | SPARC_INS_ARRAY16, |
| 228 | SPARC_INS_ARRAY32, |
| 229 | SPARC_INS_ARRAY8, |
| 230 | SPARC_INS_B, |
| 231 | SPARC_INS_JMP, |
| 232 | SPARC_INS_BMASK, |
| 233 | SPARC_INS_FB, |
| 234 | SPARC_INS_BRGEZ, |
| 235 | SPARC_INS_BRGZ, |
| 236 | SPARC_INS_BRLEZ, |
| 237 | SPARC_INS_BRLZ, |
| 238 | SPARC_INS_BRNZ, |
| 239 | SPARC_INS_BRZ, |
| 240 | SPARC_INS_BSHUFFLE, |
| 241 | SPARC_INS_CALL, |
| 242 | SPARC_INS_CASX, |
| 243 | SPARC_INS_CAS, |
| 244 | SPARC_INS_CMASK16, |
| 245 | SPARC_INS_CMASK32, |
| 246 | SPARC_INS_CMASK8, |
| 247 | SPARC_INS_CMP, |
| 248 | SPARC_INS_EDGE16, |
| 249 | SPARC_INS_EDGE16L, |
| 250 | SPARC_INS_EDGE16LN, |
| 251 | SPARC_INS_EDGE16N, |
| 252 | SPARC_INS_EDGE32, |
| 253 | SPARC_INS_EDGE32L, |
| 254 | SPARC_INS_EDGE32LN, |
| 255 | SPARC_INS_EDGE32N, |
| 256 | SPARC_INS_EDGE8, |
| 257 | SPARC_INS_EDGE8L, |
| 258 | SPARC_INS_EDGE8LN, |
| 259 | SPARC_INS_EDGE8N, |
| 260 | SPARC_INS_FABSD, |
| 261 | SPARC_INS_FABSQ, |
| 262 | SPARC_INS_FABSS, |
| 263 | SPARC_INS_FADDD, |
| 264 | SPARC_INS_FADDQ, |
| 265 | SPARC_INS_FADDS, |
| 266 | SPARC_INS_FALIGNDATA, |
| 267 | SPARC_INS_FAND, |
| 268 | SPARC_INS_FANDNOT1, |
| 269 | SPARC_INS_FANDNOT1S, |
| 270 | SPARC_INS_FANDNOT2, |
| 271 | SPARC_INS_FANDNOT2S, |
| 272 | SPARC_INS_FANDS, |
| 273 | SPARC_INS_FCHKSM16, |
| 274 | SPARC_INS_FCMPD, |
| 275 | SPARC_INS_FCMPEQ16, |
| 276 | SPARC_INS_FCMPEQ32, |
| 277 | SPARC_INS_FCMPGT16, |
| 278 | SPARC_INS_FCMPGT32, |
| 279 | SPARC_INS_FCMPLE16, |
| 280 | SPARC_INS_FCMPLE32, |
| 281 | SPARC_INS_FCMPNE16, |
| 282 | SPARC_INS_FCMPNE32, |
| 283 | SPARC_INS_FCMPQ, |
| 284 | SPARC_INS_FCMPS, |
| 285 | SPARC_INS_FDIVD, |
| 286 | SPARC_INS_FDIVQ, |
| 287 | SPARC_INS_FDIVS, |
| 288 | SPARC_INS_FDMULQ, |
| 289 | SPARC_INS_FDTOI, |
| 290 | SPARC_INS_FDTOQ, |
| 291 | SPARC_INS_FDTOS, |
| 292 | SPARC_INS_FDTOX, |
| 293 | SPARC_INS_FEXPAND, |
| 294 | SPARC_INS_FHADDD, |
| 295 | SPARC_INS_FHADDS, |
| 296 | SPARC_INS_FHSUBD, |
| 297 | SPARC_INS_FHSUBS, |
| 298 | SPARC_INS_FITOD, |
| 299 | SPARC_INS_FITOQ, |
| 300 | SPARC_INS_FITOS, |
| 301 | SPARC_INS_FLCMPD, |
| 302 | SPARC_INS_FLCMPS, |
| 303 | SPARC_INS_FLUSHW, |
| 304 | SPARC_INS_FMEAN16, |
| 305 | SPARC_INS_FMOVD, |
| 306 | SPARC_INS_FMOVQ, |
| 307 | SPARC_INS_FMOVRDGEZ, |
| 308 | SPARC_INS_FMOVRQGEZ, |
| 309 | SPARC_INS_FMOVRSGEZ, |
| 310 | SPARC_INS_FMOVRDGZ, |
| 311 | SPARC_INS_FMOVRQGZ, |
| 312 | SPARC_INS_FMOVRSGZ, |
| 313 | SPARC_INS_FMOVRDLEZ, |
| 314 | SPARC_INS_FMOVRQLEZ, |
| 315 | SPARC_INS_FMOVRSLEZ, |
| 316 | SPARC_INS_FMOVRDLZ, |
| 317 | SPARC_INS_FMOVRQLZ, |
| 318 | SPARC_INS_FMOVRSLZ, |
| 319 | SPARC_INS_FMOVRDNZ, |
| 320 | SPARC_INS_FMOVRQNZ, |
| 321 | SPARC_INS_FMOVRSNZ, |
| 322 | SPARC_INS_FMOVRDZ, |
| 323 | SPARC_INS_FMOVRQZ, |
| 324 | SPARC_INS_FMOVRSZ, |
| 325 | SPARC_INS_FMOVS, |
| 326 | SPARC_INS_FMUL8SUX16, |
| 327 | SPARC_INS_FMUL8ULX16, |
| 328 | SPARC_INS_FMUL8X16, |
| 329 | SPARC_INS_FMUL8X16AL, |
| 330 | SPARC_INS_FMUL8X16AU, |
| 331 | SPARC_INS_FMULD, |
| 332 | SPARC_INS_FMULD8SUX16, |
| 333 | SPARC_INS_FMULD8ULX16, |
| 334 | SPARC_INS_FMULQ, |
| 335 | SPARC_INS_FMULS, |
| 336 | SPARC_INS_FNADDD, |
| 337 | SPARC_INS_FNADDS, |
| 338 | SPARC_INS_FNAND, |
| 339 | SPARC_INS_FNANDS, |
| 340 | SPARC_INS_FNEGD, |
| 341 | SPARC_INS_FNEGQ, |
| 342 | SPARC_INS_FNEGS, |
| 343 | SPARC_INS_FNHADDD, |
| 344 | SPARC_INS_FNHADDS, |
| 345 | SPARC_INS_FNOR, |
| 346 | SPARC_INS_FNORS, |
| 347 | SPARC_INS_FNOT1, |
| 348 | SPARC_INS_FNOT1S, |
| 349 | SPARC_INS_FNOT2, |
| 350 | SPARC_INS_FNOT2S, |
| 351 | SPARC_INS_FONE, |
| 352 | SPARC_INS_FONES, |
| 353 | SPARC_INS_FOR, |
| 354 | SPARC_INS_FORNOT1, |
| 355 | SPARC_INS_FORNOT1S, |
| 356 | SPARC_INS_FORNOT2, |
| 357 | SPARC_INS_FORNOT2S, |
| 358 | SPARC_INS_FORS, |
| 359 | SPARC_INS_FPACK16, |
| 360 | SPARC_INS_FPACK32, |
| 361 | SPARC_INS_FPACKFIX, |
| 362 | SPARC_INS_FPADD16, |
| 363 | SPARC_INS_FPADD16S, |
| 364 | SPARC_INS_FPADD32, |
| 365 | SPARC_INS_FPADD32S, |
| 366 | SPARC_INS_FPADD64, |
| 367 | SPARC_INS_FPMERGE, |
| 368 | SPARC_INS_FPSUB16, |
| 369 | SPARC_INS_FPSUB16S, |
| 370 | SPARC_INS_FPSUB32, |
| 371 | SPARC_INS_FPSUB32S, |
| 372 | SPARC_INS_FQTOD, |
| 373 | SPARC_INS_FQTOI, |
| 374 | SPARC_INS_FQTOS, |
| 375 | SPARC_INS_FQTOX, |
| 376 | SPARC_INS_FSLAS16, |
| 377 | SPARC_INS_FSLAS32, |
| 378 | SPARC_INS_FSLL16, |
| 379 | SPARC_INS_FSLL32, |
| 380 | SPARC_INS_FSMULD, |
| 381 | SPARC_INS_FSQRTD, |
| 382 | SPARC_INS_FSQRTQ, |
| 383 | SPARC_INS_FSQRTS, |
| 384 | SPARC_INS_FSRA16, |
| 385 | SPARC_INS_FSRA32, |
| 386 | SPARC_INS_FSRC1, |
| 387 | SPARC_INS_FSRC1S, |
| 388 | SPARC_INS_FSRC2, |
| 389 | SPARC_INS_FSRC2S, |
| 390 | SPARC_INS_FSRL16, |
| 391 | SPARC_INS_FSRL32, |
| 392 | SPARC_INS_FSTOD, |
| 393 | SPARC_INS_FSTOI, |
| 394 | SPARC_INS_FSTOQ, |
| 395 | SPARC_INS_FSTOX, |
| 396 | SPARC_INS_FSUBD, |
| 397 | SPARC_INS_FSUBQ, |
| 398 | SPARC_INS_FSUBS, |
| 399 | SPARC_INS_FXNOR, |
| 400 | SPARC_INS_FXNORS, |
| 401 | SPARC_INS_FXOR, |
| 402 | SPARC_INS_FXORS, |
| 403 | SPARC_INS_FXTOD, |
| 404 | SPARC_INS_FXTOQ, |
| 405 | SPARC_INS_FXTOS, |
| 406 | SPARC_INS_FZERO, |
| 407 | SPARC_INS_FZEROS, |
| 408 | SPARC_INS_JMPL, |
| 409 | SPARC_INS_LDD, |
| 410 | SPARC_INS_LD, |
| 411 | SPARC_INS_LDQ, |
| 412 | SPARC_INS_LDSB, |
| 413 | SPARC_INS_LDSH, |
| 414 | SPARC_INS_LDSW, |
| 415 | SPARC_INS_LDUB, |
| 416 | SPARC_INS_LDUH, |
| 417 | SPARC_INS_LDX, |
| 418 | SPARC_INS_LZCNT, |
| 419 | SPARC_INS_MEMBAR, |
| 420 | SPARC_INS_MOVDTOX, |
| 421 | SPARC_INS_MOV, |
| 422 | SPARC_INS_MOVRGEZ, |
| 423 | SPARC_INS_MOVRGZ, |
| 424 | SPARC_INS_MOVRLEZ, |
| 425 | SPARC_INS_MOVRLZ, |
| 426 | SPARC_INS_MOVRNZ, |
| 427 | SPARC_INS_MOVRZ, |
| 428 | SPARC_INS_MOVSTOSW, |
| 429 | SPARC_INS_MOVSTOUW, |
| 430 | SPARC_INS_MULX, |
| 431 | SPARC_INS_NOP, |
| 432 | SPARC_INS_ORCC, |
| 433 | SPARC_INS_ORNCC, |
| 434 | SPARC_INS_ORN, |
| 435 | SPARC_INS_OR, |
| 436 | SPARC_INS_PDIST, |
| 437 | SPARC_INS_PDISTN, |
| 438 | SPARC_INS_POPC, |
| 439 | SPARC_INS_RD, |
| 440 | SPARC_INS_RESTORE, |
| 441 | SPARC_INS_RETT, |
| 442 | SPARC_INS_SAVE, |
| 443 | SPARC_INS_SDIVCC, |
| 444 | SPARC_INS_SDIVX, |
| 445 | SPARC_INS_SDIV, |
| 446 | SPARC_INS_SETHI, |
| 447 | SPARC_INS_SHUTDOWN, |
| 448 | SPARC_INS_SIAM, |
| 449 | SPARC_INS_SLLX, |
| 450 | SPARC_INS_SLL, |
| 451 | SPARC_INS_SMULCC, |
| 452 | SPARC_INS_SMUL, |
| 453 | SPARC_INS_SRAX, |
| 454 | SPARC_INS_SRA, |
| 455 | SPARC_INS_SRLX, |
| 456 | SPARC_INS_SRL, |
| 457 | SPARC_INS_STBAR, |
| 458 | SPARC_INS_STB, |
| 459 | SPARC_INS_STD, |
| 460 | SPARC_INS_ST, |
| 461 | SPARC_INS_STH, |
| 462 | SPARC_INS_STQ, |
| 463 | SPARC_INS_STX, |
| 464 | SPARC_INS_SUBCC, |
| 465 | SPARC_INS_SUBX, |
| 466 | SPARC_INS_SUBXCC, |
| 467 | SPARC_INS_SUB, |
| 468 | SPARC_INS_SWAP, |
| 469 | SPARC_INS_TADDCCTV, |
| 470 | SPARC_INS_TADDCC, |
| 471 | SPARC_INS_T, |
| 472 | SPARC_INS_TSUBCCTV, |
| 473 | SPARC_INS_TSUBCC, |
| 474 | SPARC_INS_UDIVCC, |
| 475 | SPARC_INS_UDIVX, |
| 476 | SPARC_INS_UDIV, |
| 477 | SPARC_INS_UMULCC, |
| 478 | SPARC_INS_UMULXHI, |
| 479 | SPARC_INS_UMUL, |
| 480 | SPARC_INS_UNIMP, |
| 481 | SPARC_INS_FCMPED, |
| 482 | SPARC_INS_FCMPEQ, |
| 483 | SPARC_INS_FCMPES, |
| 484 | SPARC_INS_WR, |
| 485 | SPARC_INS_XMULX, |
| 486 | SPARC_INS_XMULXHI, |
| 487 | SPARC_INS_XNORCC, |
| 488 | SPARC_INS_XNOR, |
| 489 | SPARC_INS_XORCC, |
| 490 | SPARC_INS_XOR, |
| 491 | |
| 492 | // alias instructions |
| 493 | SPARC_INS_RET, |
| 494 | SPARC_INS_RETL, |
| 495 | |
| 496 | SPARC_INS_ENDING, // <-- mark the end of the list of instructions |
| 497 | } sparc_insn; |
| 498 | |
| 499 | /// Group of SPARC instructions |
| 500 | typedef enum sparc_insn_group { |
| 501 | SPARC_GRP_INVALID = 0, ///< = CS_GRP_INVALID |
| 502 | |
| 503 | // Generic groups |
| 504 | // all jump instructions (conditional+direct+indirect jumps) |
| 505 | SPARC_GRP_JUMP, ///< = CS_GRP_JUMP |
| 506 | |
| 507 | // Architecture-specific groups |
| 508 | SPARC_GRP_HARDQUAD = 128, |
| 509 | SPARC_GRP_V9, |
| 510 | SPARC_GRP_VIS, |
| 511 | SPARC_GRP_VIS2, |
| 512 | SPARC_GRP_VIS3, |
| 513 | SPARC_GRP_32BIT, |
| 514 | SPARC_GRP_64BIT, |
| 515 | |
| 516 | SPARC_GRP_ENDING, // <-- mark the end of the list of groups |
| 517 | } sparc_insn_group; |
| 518 | |
| 519 | #ifdef __cplusplus |
| 520 | } |
| 521 | #endif |
| 522 | |
| 523 | #endif |
| 524 |