Seregon/Hermes

Hermes/Dyforge is a program written in c++ allows you to inject a dll that can analyze all processes in a program, can be used for mod and reverse engeneering

C/3.8 KB/No license
DyMain/include/capstone/sh.h
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Hermes / DyMain / include / capstone / sh.h
1#ifndef CAPSTONE_SH_H
2#define CAPSTONE_SH_H
3 
4/* Capstone Disassembly Engine */
5/* By Yoshinori Sato, 2022 */
6 
7#ifdef __cplusplus
8extern "C" {
9#endif
10 
11#include "platform.h"
12#include "cs_operand.h"
13 
14#ifdef _MSC_VER
15#pragma warning(disable:4201)
16#endif
17 
18/// SH registers and special registers
19typedef enum {
20 SH_REG_INVALID = 0,
21 
22 SH_REG_R0,
23 SH_REG_R1,
24 SH_REG_R2,
25 SH_REG_R3,
26 SH_REG_R4,
27 SH_REG_R5,
28 SH_REG_R6,
29 SH_REG_R7,
30 
31 SH_REG_R8,
32 SH_REG_R9,
33 SH_REG_R10,
34 SH_REG_R11,
35 SH_REG_R12,
36 SH_REG_R13,
37 SH_REG_R14,
38 SH_REG_R15,
39 
40 SH_REG_R0_BANK,
41 SH_REG_R1_BANK,
42 SH_REG_R2_BANK,
43 SH_REG_R3_BANK,
44 SH_REG_R4_BANK,
45 SH_REG_R5_BANK,
46 SH_REG_R6_BANK,
47 SH_REG_R7_BANK,
48 
49 SH_REG_FR0,
50 SH_REG_FR1,
51 SH_REG_FR2,
52 SH_REG_FR3,
53 SH_REG_FR4,
54 SH_REG_FR5,
55 SH_REG_FR6,
56 SH_REG_FR7,
57 SH_REG_FR8,
58 SH_REG_FR9,
59 SH_REG_FR10,
60 SH_REG_FR11,
61 SH_REG_FR12,
62 SH_REG_FR13,
63 SH_REG_FR14,
64 SH_REG_FR15,
65 
66 SH_REG_DR0,
67 SH_REG_DR2,
68 SH_REG_DR4,
69 SH_REG_DR6,
70 SH_REG_DR8,
71 SH_REG_DR10,
72 SH_REG_DR12,
73 SH_REG_DR14,
74 
75 SH_REG_XD0,
76 SH_REG_XD2,
77 SH_REG_XD4,
78 SH_REG_XD6,
79 SH_REG_XD8,
80 SH_REG_XD10,
81 SH_REG_XD12,
82 SH_REG_XD14,
83 
84 SH_REG_XF0,
85 SH_REG_XF1,
86 SH_REG_XF2,
87 SH_REG_XF3,
88 SH_REG_XF4,
89 SH_REG_XF5,
90 SH_REG_XF6,
91 SH_REG_XF7,
92 SH_REG_XF8,
93 SH_REG_XF9,
94 SH_REG_XF10,
95 SH_REG_XF11,
96 SH_REG_XF12,
97 SH_REG_XF13,
98 SH_REG_XF14,
99 SH_REG_XF15,
100 
101 SH_REG_FV0,
102 SH_REG_FV4,
103 SH_REG_FV8,
104 SH_REG_FV12,
105 
106 SH_REG_XMATRX,
107 
108 SH_REG_PC,
109 SH_REG_PR,
110 SH_REG_MACH,
111 SH_REG_MACL,
112 
113 SH_REG_SR,
114 SH_REG_GBR,
115 SH_REG_SSR,
116 SH_REG_SPC,
117 SH_REG_SGR,
118 SH_REG_DBR,
119 SH_REG_VBR,
120 SH_REG_TBR,
121 SH_REG_RS,
122 SH_REG_RE,
123 SH_REG_MOD,
124 
125 SH_REG_FPUL,
126 SH_REG_FPSCR,
127 
128 SH_REG_DSP_X0,
129 SH_REG_DSP_X1,
130 SH_REG_DSP_Y0,
131 SH_REG_DSP_Y1,
132 SH_REG_DSP_A0,
133 SH_REG_DSP_A1,
134 SH_REG_DSP_A0G,
135 SH_REG_DSP_A1G,
136 SH_REG_DSP_M0,
137 SH_REG_DSP_M1,
138 SH_REG_DSP_DSR,
139 
140 SH_REG_DSP_RSV0,
141 SH_REG_DSP_RSV1,
142 SH_REG_DSP_RSV2,
143 SH_REG_DSP_RSV3,
144 SH_REG_DSP_RSV4,
145 SH_REG_DSP_RSV5,
146 SH_REG_DSP_RSV6,
147 SH_REG_DSP_RSV7,
148 SH_REG_DSP_RSV8,
149 SH_REG_DSP_RSV9,
150 SH_REG_DSP_RSVA,
151 SH_REG_DSP_RSVB,
152 SH_REG_DSP_RSVC,
153 SH_REG_DSP_RSVD,
154 SH_REG_DSP_RSVE,
155 SH_REG_DSP_RSVF,
156 
157 SH_REG_ENDING, // <-- mark the end of the list of registers
158} sh_reg;
159 
160typedef enum {
161 SH_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized).
162 SH_OP_REG = CS_OP_REG, ///< = CS_OP_REG (Register operand).
163 SH_OP_IMM = CS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
164 SH_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
165} sh_op_type;
166 
167typedef enum {
168 SH_OP_MEM_INVALID = 0, /// <= Invalid
169 SH_OP_MEM_REG_IND, /// <= Register indirect
170 SH_OP_MEM_REG_POST, /// <= Register post increment
171 SH_OP_MEM_REG_PRE, /// <= Register pre decrement
172 SH_OP_MEM_REG_DISP, /// <= displacement
173 SH_OP_MEM_REG_R0, /// <= R0 indexed
174 SH_OP_MEM_GBR_DISP, /// <= GBR based displacement
175 SH_OP_MEM_GBR_R0, /// <= GBR based R0 indexed
176 SH_OP_MEM_PCR, /// <= PC relative
177 SH_OP_MEM_TBR_DISP, /// <= TBR based displaysment
178} sh_op_mem_type;
179 
180typedef struct sh_op_mem {
181 sh_op_mem_type address; /// <= memory address
182 sh_reg reg; /// <= base register
183 uint32_t disp; /// <= displacement
184} sh_op_mem;
185 
186typedef enum sh_dsp_insn {
187 SH_INS_DSP_INVALID = 0,
188 SH_INS_DSP_NOP = 1,
189 SH_INS_DSP_MOV,
190 SH_INS_DSP_PSHL,
191 SH_INS_DSP_PSHA,
192 SH_INS_DSP_PMULS,
193 SH_INS_DSP_PCLR_PMULS,
194 SH_INS_DSP_PSUB_PMULS,
195 SH_INS_DSP_PADD_PMULS,
196 SH_INS_DSP_PSUBC,
197 SH_INS_DSP_PADDC,
198 SH_INS_DSP_PCMP,
199 SH_INS_DSP_PABS,
200 SH_INS_DSP_PRND,
201 SH_INS_DSP_PSUB,
202 SH_INS_DSP_PSUBr,
203 SH_INS_DSP_PADD,
204 SH_INS_DSP_PAND,
205 SH_INS_DSP_PXOR,
206 SH_INS_DSP_POR,
207 SH_INS_DSP_PDEC,
208 SH_INS_DSP_PINC,
209 SH_INS_DSP_PCLR,
210 SH_INS_DSP_PDMSB,
211 SH_INS_DSP_PNEG,
212 SH_INS_DSP_PCOPY,
213 SH_INS_DSP_PSTS,
214 SH_INS_DSP_PLDS,
215 SH_INS_DSP_PSWAP,
216 SH_INS_DSP_PWAD,
217 SH_INS_DSP_PWSB,
218} sh_dsp_insn;
219 
220typedef enum sh_dsp_operand {
221 SH_OP_DSP_INVALID,
222 SH_OP_DSP_REG_PRE,
223 SH_OP_DSP_REG_IND,
224 SH_OP_DSP_REG_POST,
225 SH_OP_DSP_REG_INDEX,
226 SH_OP_DSP_REG,
227 SH_OP_DSP_IMM,
228
229} sh_dsp_operand;
230 
231typedef enum sh_dsp_cc {
232 SH_DSP_CC_INVALID,
233 SH_DSP_CC_NONE,
234 SH_DSP_CC_DCT,
235 SH_DSP_CC_DCF,
236} sh_dsp_cc;
237 
238typedef struct sh_op_dsp {
239 sh_dsp_insn insn;
240 sh_dsp_operand operand[2];
241 sh_reg r[6];
242 sh_dsp_cc cc;
243 uint8_t imm;
244 int size;
245} sh_op_dsp;
246
247/// Instruction operand
248typedef struct cs_sh_op {
249 sh_op_type type;
250 union {
251 uint64_t imm; ///< immediate value for IMM operand
252 sh_reg reg; ///< register value for REG operand
253 sh_op_mem mem; ///< data when operand is targeting memory
254 sh_op_dsp dsp; ///< dsp instruction
255 };
256} cs_sh_op;
257 
258/// SH instruction
259typedef enum sh_insn {
260 SH_INS_INVALID,
261 SH_INS_ADD_r,
262 SH_INS_ADD,
263 SH_INS_ADDC,
264 SH_INS_ADDV,
265 SH_INS_AND,
266 SH_INS_BAND,
267 SH_INS_BANDNOT,
268 SH_INS_BCLR,
269 SH_INS_BF,
270 SH_INS_BF_S,
271 SH_INS_BLD,
272 SH_INS_BLDNOT,
273 SH_INS_BOR,
274 SH_INS_BORNOT,
275 SH_INS_BRA,
276 SH_INS_BRAF,
277 SH_INS_BSET,
278 SH_INS_BSR,
279 SH_INS_BSRF,
280 SH_INS_BST,
281 SH_INS_BT,
282 SH_INS_BT_S,
283 SH_INS_BXOR,
284 SH_INS_CLIPS,
285 SH_INS_CLIPU,
286 SH_INS_CLRDMXY,
287 SH_INS_CLRMAC,
288 SH_INS_CLRS,
289 SH_INS_CLRT,
290 SH_INS_CMP_EQ,
291 SH_INS_CMP_GE,
292 SH_INS_CMP_GT,
293 SH_INS_CMP_HI,
294 SH_INS_CMP_HS,
295 SH_INS_CMP_PL,
296 SH_INS_CMP_PZ,
297 SH_INS_CMP_STR,
298 SH_INS_DIV0S,
299 SH_INS_DIV0U,
300 SH_INS_DIV1,
301 SH_INS_DIVS,
302 SH_INS_DIVU,
303 SH_INS_DMULS_L,
304 SH_INS_DMULU_L,
305 SH_INS_DT,
306 SH_INS_EXTS_B,
307 SH_INS_EXTS_W,
308 SH_INS_EXTU_B,
309 SH_INS_EXTU_W,
310 SH_INS_FABS,
311 SH_INS_FADD,
312 SH_INS_FCMP_EQ,
313 SH_INS_FCMP_GT,
314 SH_INS_FCNVDS,
315 SH_INS_FCNVSD,
316 SH_INS_FDIV,
317 SH_INS_FIPR,
318 SH_INS_FLDI0,
319 SH_INS_FLDI1,
320 SH_INS_FLDS,
321 SH_INS_FLOAT,
322 SH_INS_FMAC,
323 SH_INS_FMOV,
324 SH_INS_FMUL,
325 SH_INS_FNEG,
326 SH_INS_FPCHG,
327 SH_INS_FRCHG,
328 SH_INS_FSCA,
329 SH_INS_FSCHG,
330 SH_INS_FSQRT,
331 SH_INS_FSRRA,
332 SH_INS_FSTS,
333 SH_INS_FSUB,
334 SH_INS_FTRC,
335 SH_INS_FTRV,
336 SH_INS_ICBI,
337 SH_INS_JMP,
338 SH_INS_JSR,
339 SH_INS_JSR_N,
340 SH_INS_LDBANK,
341 SH_INS_LDC,
342 SH_INS_LDRC,
343 SH_INS_LDRE,
344 SH_INS_LDRS,
345 SH_INS_LDS,
346 SH_INS_LDTLB,
347 SH_INS_MAC_L,
348 SH_INS_MAC_W,
349 SH_INS_MOV,
350 SH_INS_MOVA,
351 SH_INS_MOVCA,
352 SH_INS_MOVCO,
353 SH_INS_MOVI20,
354 SH_INS_MOVI20S,
355 SH_INS_MOVLI,
356 SH_INS_MOVML,
357 SH_INS_MOVMU,
358 SH_INS_MOVRT,
359 SH_INS_MOVT,
360 SH_INS_MOVU,
361 SH_INS_MOVUA,
362 SH_INS_MUL_L,
363 SH_INS_MULR,
364 SH_INS_MULS_W,
365 SH_INS_MULU_W,
366 SH_INS_NEG,
367 SH_INS_NEGC,
368 SH_INS_NOP,
369 SH_INS_NOT,
370 SH_INS_NOTT,
371 SH_INS_OCBI,
372 SH_INS_OCBP,
373 SH_INS_OCBWB,
374 SH_INS_OR,
375 SH_INS_PREF,
376 SH_INS_PREFI,
377 SH_INS_RESBANK,
378 SH_INS_ROTCL,
379 SH_INS_ROTCR,
380 SH_INS_ROTL,
381 SH_INS_ROTR,
382 SH_INS_RTE,
383 SH_INS_RTS,
384 SH_INS_RTS_N,
385 SH_INS_RTV_N,
386 SH_INS_SETDMX,
387 SH_INS_SETDMY,
388 SH_INS_SETRC,
389 SH_INS_SETS,
390 SH_INS_SETT,
391 SH_INS_SHAD,
392 SH_INS_SHAL,
393 SH_INS_SHAR,
394 SH_INS_SHLD,
395 SH_INS_SHLL,
396 SH_INS_SHLL16,
397 SH_INS_SHLL2,
398 SH_INS_SHLL8,
399 SH_INS_SHLR,
400 SH_INS_SHLR16,
401 SH_INS_SHLR2,
402 SH_INS_SHLR8,
403 SH_INS_SLEEP,
404 SH_INS_STBANK,
405 SH_INS_STC,
406 SH_INS_STS,
407 SH_INS_SUB,
408 SH_INS_SUBC,
409 SH_INS_SUBV,
410 SH_INS_SWAP_B,
411 SH_INS_SWAP_W,
412 SH_INS_SYNCO,
413 SH_INS_TAS,
414 SH_INS_TRAPA,
415 SH_INS_TST,
416 SH_INS_XOR,
417 SH_INS_XTRCT,
418 SH_INS_DSP,
419 SH_INS_ENDING, // <-- mark the end of the list of instructions
420} sh_insn;
421 
422/// Instruction structure
423typedef struct cs_sh {
424 sh_insn insn;
425 uint8_t size;
426 uint8_t op_count;
427 cs_sh_op operands[3];
428} cs_sh;
429 
430/// Group of SH instructions
431typedef enum sh_insn_group {
432 SH_GRP_INVALID = 0, ///< CS_GRUP_INVALID
433 SH_GRP_JUMP, ///< = CS_GRP_JUMP
434 SH_GRP_CALL, ///< = CS_GRP_CALL
435 SH_GRP_INT, ///< = CS_GRP_INT
436 SH_GRP_RET, ///< = CS_GRP_RET
437 SH_GRP_IRET, ///< = CS_GRP_IRET
438 SH_GRP_PRIVILEGE, ///< = CS_GRP_PRIVILEGE
439 SH_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE
440 
441 SH_GRP_SH1,
442 SH_GRP_SH2,
443 SH_GRP_SH2E,
444 SH_GRP_SH2DSP,
445 SH_GRP_SH2A,
446 SH_GRP_SH2AFPU,
447 SH_GRP_SH3,
448 SH_GRP_SH3DSP,
449 SH_GRP_SH4,
450 SH_GRP_SH4A,
451
452 SH_GRP_ENDING,// <-- mark the end of the list of groups
453} sh_insn_group;
454 
455#ifdef __cplusplus
456}
457#endif
458 
459#endif
460