Seregon/Hermes

Hermes/Dyforge is a program written in c++ allows you to inject a dll that can analyze all processes in a program, can be used for mod and reverse engeneering

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DyMain/include/capstone/mos65xx.h
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Hermes / DyMain / include / capstone / mos65xx.h
1#ifndef CAPSTONE_MOS65XX_H
2#define CAPSTONE_MOS65XX_H
3 
4/* Capstone Disassembly Engine */
5/* By Sebastian Macke <sebastian@macke.de, 2018 */
6 
7#ifdef __cplusplus
8extern "C" {
9#endif
10 
11#include "platform.h"
12#include "cs_operand.h"
13 
14/// MOS65XX registers and special registers
15typedef enum mos65xx_reg {
16 MOS65XX_REG_INVALID = 0,
17 MOS65XX_REG_ACC, ///< accumulator
18 MOS65XX_REG_X, ///< X index register
19 MOS65XX_REG_Y, ///< Y index register
20 MOS65XX_REG_P, ///< status register
21 MOS65XX_REG_SP, ///< stack pointer register
22 MOS65XX_REG_DP, ///< direct page register
23 MOS65XX_REG_B, ///< data bank register
24 MOS65XX_REG_K, ///< program bank register
25 MOS65XX_REG_ENDING, // <-- mark the end of the list of registers
26} mos65xx_reg;
27 
28/// MOS65XX Addressing Modes
29typedef enum mos65xx_address_mode {
30 MOS65XX_AM_NONE = 0, ///< No address mode.
31 MOS65XX_AM_IMP, ///< implied addressing (no addressing mode)
32 MOS65XX_AM_ACC, ///< accumulator addressing
33 MOS65XX_AM_IMM, ///< 8/16 Bit immediate value
34 MOS65XX_AM_REL, ///< relative addressing used by branches
35 MOS65XX_AM_INT, ///< interrupt addressing
36 MOS65XX_AM_BLOCK, ///< memory block addressing
37 MOS65XX_AM_ZP, ///< zeropage addressing
38 MOS65XX_AM_ZP_X, ///< indexed zeropage addressing by the X index register
39 MOS65XX_AM_ZP_Y, ///< indexed zeropage addressing by the Y index register
40 MOS65XX_AM_ZP_REL, ///< zero page address, branch relative address
41 MOS65XX_AM_ZP_IND, ///< indirect zeropage addressing
42 MOS65XX_AM_ZP_X_IND, ///< indexed zeropage indirect addressing by the X index register
43 MOS65XX_AM_ZP_IND_Y, ///< indirect zeropage indexed addressing by the Y index register
44 MOS65XX_AM_ZP_IND_LONG, ///< zeropage indirect long addressing
45 MOS65XX_AM_ZP_IND_LONG_Y, ///< zeropage indirect long addressing indexed by Y register
46 MOS65XX_AM_ABS, ///< absolute addressing
47 MOS65XX_AM_ABS_X, ///< indexed absolute addressing by the X index register
48 MOS65XX_AM_ABS_Y, ///< indexed absolute addressing by the Y index register
49 MOS65XX_AM_ABS_IND, ///< absolute indirect addressing
50 MOS65XX_AM_ABS_X_IND, ///< indexed absolute indirect addressing by the X index register
51 MOS65XX_AM_ABS_IND_LONG, ///< absolute indirect long addressing
52 MOS65XX_AM_ABS_LONG, ///< absolute long address mode
53 MOS65XX_AM_ABS_LONG_X, ///< absolute long address mode, indexed by X register
54 MOS65XX_AM_SR, ///< stack relative addressing
55 MOS65XX_AM_SR_IND_Y, ///< indirect stack relative addressing indexed by the Y index register
56} mos65xx_address_mode;
57 
58/// MOS65XX instruction
59typedef enum mos65xx_insn {
60 MOS65XX_INS_INVALID = 0,
61 MOS65XX_INS_ADC,
62 MOS65XX_INS_AND,
63 MOS65XX_INS_ASL,
64 MOS65XX_INS_BBR,
65 MOS65XX_INS_BBS,
66 MOS65XX_INS_BCC,
67 MOS65XX_INS_BCS,
68 MOS65XX_INS_BEQ,
69 MOS65XX_INS_BIT,
70 MOS65XX_INS_BMI,
71 MOS65XX_INS_BNE,
72 MOS65XX_INS_BPL,
73 MOS65XX_INS_BRA,
74 MOS65XX_INS_BRK,
75 MOS65XX_INS_BRL,
76 MOS65XX_INS_BVC,
77 MOS65XX_INS_BVS,
78 MOS65XX_INS_CLC,
79 MOS65XX_INS_CLD,
80 MOS65XX_INS_CLI,
81 MOS65XX_INS_CLV,
82 MOS65XX_INS_CMP,
83 MOS65XX_INS_COP,
84 MOS65XX_INS_CPX,
85 MOS65XX_INS_CPY,
86 MOS65XX_INS_DEC,
87 MOS65XX_INS_DEX,
88 MOS65XX_INS_DEY,
89 MOS65XX_INS_EOR,
90 MOS65XX_INS_INC,
91 MOS65XX_INS_INX,
92 MOS65XX_INS_INY,
93 MOS65XX_INS_JML,
94 MOS65XX_INS_JMP,
95 MOS65XX_INS_JSL,
96 MOS65XX_INS_JSR,
97 MOS65XX_INS_LDA,
98 MOS65XX_INS_LDX,
99 MOS65XX_INS_LDY,
100 MOS65XX_INS_LSR,
101 MOS65XX_INS_MVN,
102 MOS65XX_INS_MVP,
103 MOS65XX_INS_NOP,
104 MOS65XX_INS_ORA,
105 MOS65XX_INS_PEA,
106 MOS65XX_INS_PEI,
107 MOS65XX_INS_PER,
108 MOS65XX_INS_PHA,
109 MOS65XX_INS_PHB,
110 MOS65XX_INS_PHD,
111 MOS65XX_INS_PHK,
112 MOS65XX_INS_PHP,
113 MOS65XX_INS_PHX,
114 MOS65XX_INS_PHY,
115 MOS65XX_INS_PLA,
116 MOS65XX_INS_PLB,
117 MOS65XX_INS_PLD,
118 MOS65XX_INS_PLP,
119 MOS65XX_INS_PLX,
120 MOS65XX_INS_PLY,
121 MOS65XX_INS_REP,
122 MOS65XX_INS_RMB,
123 MOS65XX_INS_ROL,
124 MOS65XX_INS_ROR,
125 MOS65XX_INS_RTI,
126 MOS65XX_INS_RTL,
127 MOS65XX_INS_RTS,
128 MOS65XX_INS_SBC,
129 MOS65XX_INS_SEC,
130 MOS65XX_INS_SED,
131 MOS65XX_INS_SEI,
132 MOS65XX_INS_SEP,
133 MOS65XX_INS_SMB,
134 MOS65XX_INS_STA,
135 MOS65XX_INS_STP,
136 MOS65XX_INS_STX,
137 MOS65XX_INS_STY,
138 MOS65XX_INS_STZ,
139 MOS65XX_INS_TAX,
140 MOS65XX_INS_TAY,
141 MOS65XX_INS_TCD,
142 MOS65XX_INS_TCS,
143 MOS65XX_INS_TDC,
144 MOS65XX_INS_TRB,
145 MOS65XX_INS_TSB,
146 MOS65XX_INS_TSC,
147 MOS65XX_INS_TSX,
148 MOS65XX_INS_TXA,
149 MOS65XX_INS_TXS,
150 MOS65XX_INS_TXY,
151 MOS65XX_INS_TYA,
152 MOS65XX_INS_TYX,
153 MOS65XX_INS_WAI,
154 MOS65XX_INS_WDM,
155 MOS65XX_INS_XBA,
156 MOS65XX_INS_XCE,
157 MOS65XX_INS_ENDING, // <-- mark the end of the list of instructions
158} mos65xx_insn;
159 
160/// Group of MOS65XX instructions
161typedef enum mos65xx_group_type {
162 MOS65XX_GRP_INVALID = 0, ///< CS_GRP_INVALID
163 MOS65XX_GRP_JUMP, ///< = CS_GRP_JUMP
164 MOS65XX_GRP_CALL, ///< = CS_GRP_RET
165 MOS65XX_GRP_RET, ///< = CS_GRP_RET
166 MOS65XX_GRP_INT, ///< = CS_GRP_INT
167 MOS65XX_GRP_IRET = 5, ///< = CS_GRP_IRET
168 MOS65XX_GRP_BRANCH_RELATIVE = 6, ///< = CS_GRP_BRANCH_RELATIVE
169 MOS65XX_GRP_ENDING,// <-- mark the end of the list of groups
170} mos65xx_group_type;
171 
172/// Operand type for instruction's operands
173typedef enum mos65xx_op_type {
174 MOS65XX_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized).
175 MOS65XX_OP_REG = CS_OP_REG, ///< = CS_OP_REG (Register operand).
176 MOS65XX_OP_IMM = CS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
177 MOS65XX_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
178} mos65xx_op_type;
179 
180/// Instruction operand
181typedef struct cs_mos65xx_op {
182 mos65xx_op_type type; ///< operand type
183 union {
184 mos65xx_reg reg; ///< register value for REG operand
185 uint16_t imm; ///< immediate value for IMM operand
186 uint32_t mem; ///< address for MEM operand
187 };
188} cs_mos65xx_op;
189 
190/// The MOS65XX address mode and its operands
191typedef struct cs_mos65xx {
192 mos65xx_address_mode am;
193 bool modifies_flags;
194 
195 /// Number of operands of this instruction,
196 /// or 0 when instruction has no operand.
197 uint8_t op_count;
198 cs_mos65xx_op operands[3]; ///< operands for this instruction.
199} cs_mos65xx;
200 
201#ifdef __cplusplus
202}
203#endif
204 
205#endif //CAPSTONE_MOS65XX_H
206