Seregon/Hermes

Hermes/Dyforge is a program written in c++ allows you to inject a dll that can analyze all processes in a program, can be used for mod and reverse engeneering

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DyMain/include/capstone/capstone.h
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Hermes / DyMain / include / capstone / capstone.h
1#ifndef CAPSTONE_ENGINE_H
2#define CAPSTONE_ENGINE_H
3 
4/* Capstone Disassembly Engine */
5/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2016 */
6 
7#ifdef __cplusplus
8extern "C" {
9#endif
10 
11#include <stdarg.h>
12 
13#if defined(CAPSTONE_HAS_OSXKERNEL)
14#include <libkern/libkern.h>
15#else
16#include <stdlib.h>
17#include <stdio.h>
18#endif
19 
20#include "cs_operand.h"
21#include "platform.h"
22 
23#ifdef _MSC_VER
24#pragma warning(disable:4201)
25#pragma warning(disable:4100)
26#define CAPSTONE_API __cdecl
27#ifdef CAPSTONE_SHARED
28#define CAPSTONE_EXPORT __declspec(dllexport)
29#else // defined(CAPSTONE_STATIC)
30#define CAPSTONE_EXPORT
31#endif
32#else
33#define CAPSTONE_API
34#if (defined(__GNUC__) || defined(__IBMC__)) && !defined(CAPSTONE_STATIC)
35#define CAPSTONE_EXPORT __attribute__((visibility("default")))
36#else // defined(CAPSTONE_STATIC)
37#define CAPSTONE_EXPORT
38#endif
39#endif
40 
41#if (defined(__GNUC__) || defined(__IBMC__))
42#define CAPSTONE_DEPRECATED __attribute__((deprecated))
43#elif defined(_MSC_VER)
44#define CAPSTONE_DEPRECATED __declspec(deprecated)
45#else
46#pragma message("WARNING: You need to implement CAPSTONE_DEPRECATED for this compiler")
47#define CAPSTONE_DEPRECATED
48#endif
49 
50// Capstone API version
51#define CS_API_MAJOR 6
52#define CS_API_MINOR 0
53 
54// Version for bleeding edge code of the Github's "next" branch.
55// Use this if you want the absolutely latest development code.
56// This version number will be bumped up whenever we have a new major change.
57#define CS_NEXT_VERSION 7
58 
59// Capstone package version
60#define CS_VERSION_MAJOR CS_API_MAJOR
61#define CS_VERSION_MINOR CS_API_MINOR
62#define CS_VERSION_EXTRA 0
63 
64/// Macro to create combined version which can be compared to
65/// result of cs_version() API.
66#define CS_MAKE_VERSION(major, minor) ((major << 8) + minor)
67 
68/// Maximum size of an instruction mnemonic string.
69#define CS_MNEMONIC_SIZE 32
70 
71// Handle using with all API
72typedef size_t csh;
73 
74/// Architecture type
75typedef enum cs_arch {
76 CS_ARCH_ARM = 0, ///< ARM architecture (including Thumb, Thumb-2)
77#ifdef CAPSTONE_AARCH64_COMPAT_HEADER
78 CS_ARCH_ARM64 = 1, ///< ARM64
79#else
80 CS_ARCH_AARCH64 = 1, ///< AArch64
81#endif
82#ifdef CAPSTONE_SYSTEMZ_COMPAT_HEADER
83 CS_ARCH_SYSZ = 2, ///< SystemZ architecture
84#else
85 CS_ARCH_SYSTEMZ = 2, ///< SystemZ architecture
86#endif
87 CS_ARCH_MIPS, ///< Mips architecture
88 CS_ARCH_X86, ///< X86 architecture (including x86 & x86-64)
89 CS_ARCH_PPC, ///< PowerPC architecture
90 CS_ARCH_SPARC, ///< Sparc architecture
91 CS_ARCH_XCORE, ///< XCore architecture
92 CS_ARCH_M68K, ///< 68K architecture
93 CS_ARCH_TMS320C64X, ///< TMS320C64x architecture
94 CS_ARCH_M680X, ///< 680X architecture
95 CS_ARCH_EVM, ///< Ethereum architecture
96 CS_ARCH_MOS65XX, ///< MOS65XX architecture (including MOS6502)
97 CS_ARCH_WASM, ///< WebAssembly architecture
98 CS_ARCH_BPF, ///< Berkeley Packet Filter architecture (including eBPF)
99 CS_ARCH_RISCV, ///< RISCV architecture
100 CS_ARCH_SH, ///< SH architecture
101 CS_ARCH_TRICORE, ///< TriCore architecture
102 CS_ARCH_ALPHA, ///< Alpha architecture
103 CS_ARCH_HPPA, ///< HPPA architecture
104 CS_ARCH_LOONGARCH, ///< LoongArch architecture
105 CS_ARCH_XTENSA, ///< Xtensa architecture
106 CS_ARCH_ARC, ///< ARC architecture
107 CS_ARCH_MAX,
108 CS_ARCH_ALL = 0xFFFF, // All architectures - for cs_support()
109} cs_arch;
110 
111// Support value to verify diet mode of the engine.
112// If cs_support(CS_SUPPORT_DIET) return True, the engine was compiled
113// in diet mode.
114#define CS_SUPPORT_DIET (CS_ARCH_ALL + 1)
115 
116// Support value to verify X86 reduce mode of the engine.
117// If cs_support(CS_SUPPORT_X86_REDUCE) return True, the engine was compiled
118// in X86 reduce mode.
119#define CS_SUPPORT_X86_REDUCE (CS_ARCH_ALL + 2)
120 
121/// Mode type
122typedef enum cs_mode {
123 CS_MODE_LITTLE_ENDIAN = 0, ///< little-endian mode (default mode)
124 CS_MODE_ARM = 0, ///< 32-bit ARM
125 CS_MODE_16 = 1 << 1, ///< 16-bit mode (X86)
126 CS_MODE_32 = 1 << 2, ///< 32-bit mode (X86)
127 CS_MODE_64 = 1 << 3, ///< 64-bit mode (X86, PPC)
128 CS_MODE_THUMB = 1 << 4, ///< ARM's Thumb mode, including Thumb-2
129 CS_MODE_MCLASS = 1 << 5, ///< ARM's Cortex-M series
130 CS_MODE_V8 = 1 << 6, ///< ARMv8 A32 encodings for ARM
131 CS_MODE_V9 = 1 << 4, ///< SparcV9 mode (Sparc)
132 CS_MODE_QPX = 1 << 4, ///< Quad Processing eXtensions mode (PPC)
133 CS_MODE_SPE = 1 << 5, ///< Signal Processing Engine mode (PPC)
134 CS_MODE_BOOKE = 1 << 6, ///< Book-E mode (PPC)
135 CS_MODE_PS = 1 << 7, ///< Paired-singles mode (PPC)
136 CS_MODE_AIX_OS = 1 << 8, ///< PowerPC AIX-OS
137 CS_MODE_PWR7 = 1 << 9, ///< Power 7
138 CS_MODE_PWR8 = 1 << 10, ///< Power 8
139 CS_MODE_PWR9 = 1 << 11, ///< Power 9
140 CS_MODE_PWR10 = 1 << 12, ///< Power 10
141 CS_MODE_PPC_ISA_FUTURE = 1 << 13, ///< Power ISA Future
142 CS_MODE_MODERN_AIX_AS = 1 << 14, ///< PowerPC AIX-OS with modern assembly
143 CS_MODE_MSYNC = 1 << 15, ///< PowerPC Has only the msync instruction instead of sync. Implies BOOKE
144 CS_MODE_M68K_000 = 1 << 1, ///< M68K 68000 mode
145 CS_MODE_M68K_010 = 1 << 2, ///< M68K 68010 mode
146 CS_MODE_M68K_020 = 1 << 3, ///< M68K 68020 mode
147 CS_MODE_M68K_030 = 1 << 4, ///< M68K 68030 mode
148 CS_MODE_M68K_040 = 1 << 5, ///< M68K 68040 mode
149 CS_MODE_M68K_060 = 1 << 6, ///< M68K 68060 mode
150 CS_MODE_BIG_ENDIAN = 1U << 31, ///< big-endian mode
151 CS_MODE_MIPS16 = CS_MODE_16, ///< Generic mips16
152 CS_MODE_MIPS32 = CS_MODE_32, ///< Generic mips32
153 CS_MODE_MIPS64 = CS_MODE_64, ///< Generic mips64
154 CS_MODE_MICRO = 1 << 4, ///< microMips
155 CS_MODE_MIPS1 = 1 << 5, ///< Mips I ISA Support
156 CS_MODE_MIPS2 = 1 << 6, ///< Mips II ISA Support
157 CS_MODE_MIPS32R2 = 1 << 7, ///< Mips32r2 ISA Support
158 CS_MODE_MIPS32R3 = 1 << 8, ///< Mips32r3 ISA Support
159 CS_MODE_MIPS32R5 = 1 << 9, ///< Mips32r5 ISA Support
160 CS_MODE_MIPS32R6 = 1 << 10, ///< Mips32r6 ISA Support
161 CS_MODE_MIPS3 = 1 << 11, ///< MIPS III ISA Support
162 CS_MODE_MIPS4 = 1 << 12, ///< MIPS IV ISA Support
163 CS_MODE_MIPS5 = 1 << 13, ///< MIPS V ISA Support
164 CS_MODE_MIPS64R2 = 1 << 14, ///< Mips64r2 ISA Support
165 CS_MODE_MIPS64R3 = 1 << 15, ///< Mips64r3 ISA Support
166 CS_MODE_MIPS64R5 = 1 << 16, ///< Mips64r5 ISA Support
167 CS_MODE_MIPS64R6 = 1 << 17, ///< Mips64r6 ISA Support
168 CS_MODE_OCTEON = 1 << 18, ///< Octeon cnMIPS Support
169 CS_MODE_OCTEONP = 1 << 19, ///< Octeon+ cnMIPS Support
170 CS_MODE_NANOMIPS = 1 << 20, ///< Generic nanomips
171 CS_MODE_NMS1 = ((1 << 21) | CS_MODE_NANOMIPS), ///< nanoMips NMS1
172 CS_MODE_I7200 = ((1 << 22) | CS_MODE_NANOMIPS), ///< nanoMips I7200
173 CS_MODE_MIPS_NOFLOAT = 1 << 23, ///< Disable floating points ops
174 CS_MODE_MIPS_PTR64 = 1 << 24, ///< Mips pointers are 64-bit
175 CS_MODE_MICRO32R3 = (CS_MODE_MICRO | CS_MODE_MIPS32R3), ///< microMips32r3
176 CS_MODE_MICRO32R6 = (CS_MODE_MICRO | CS_MODE_MIPS32R6), ///< microMips32r6
177 CS_MODE_M680X_6301 = 1 << 1, ///< M680X Hitachi 6301,6303 mode
178 CS_MODE_M680X_6309 = 1 << 2, ///< M680X Hitachi 6309 mode
179 CS_MODE_M680X_6800 = 1 << 3, ///< M680X Motorola 6800,6802 mode
180 CS_MODE_M680X_6801 = 1 << 4, ///< M680X Motorola 6801,6803 mode
181 CS_MODE_M680X_6805 = 1 << 5, ///< M680X Motorola/Freescale 6805 mode
182 CS_MODE_M680X_6808 = 1 << 6, ///< M680X Motorola/Freescale/NXP 68HC08 mode
183 CS_MODE_M680X_6809 = 1 << 7, ///< M680X Motorola 6809 mode
184 CS_MODE_M680X_6811 = 1 << 8, ///< M680X Motorola/Freescale/NXP 68HC11 mode
185 CS_MODE_M680X_CPU12 = 1 << 9, ///< M680X Motorola/Freescale/NXP CPU12
186 ///< used on M68HC12/HCS12
187 CS_MODE_M680X_HCS08 = 1 << 10, ///< M680X Freescale/NXP HCS08 mode
188 CS_MODE_BPF_CLASSIC = 0, ///< Classic BPF mode (default)
189 CS_MODE_BPF_EXTENDED = 1 << 0, ///< Extended BPF mode
190 CS_MODE_RISCV32 = 1 << 0, ///< RISCV RV32G
191 CS_MODE_RISCV64 = 1 << 1, ///< RISCV RV64G
192 CS_MODE_RISCVC = 1 << 2, ///< RISCV compressed instructure mode
193 CS_MODE_MOS65XX_6502 = 1 << 1, ///< MOS65XXX MOS 6502
194 CS_MODE_MOS65XX_65C02 = 1 << 2, ///< MOS65XXX WDC 65c02
195 CS_MODE_MOS65XX_W65C02 = 1 << 3, ///< MOS65XXX WDC W65c02
196 CS_MODE_MOS65XX_65816 = 1 << 4, ///< MOS65XXX WDC 65816, 8-bit m/x
197 CS_MODE_MOS65XX_65816_LONG_M = (1 << 5), ///< MOS65XXX WDC 65816, 16-bit m, 8-bit x
198 CS_MODE_MOS65XX_65816_LONG_X = (1 << 6), ///< MOS65XXX WDC 65816, 8-bit m, 16-bit x
199 CS_MODE_MOS65XX_65816_LONG_MX = CS_MODE_MOS65XX_65816_LONG_M | CS_MODE_MOS65XX_65816_LONG_X,
200 CS_MODE_SH2 = 1 << 1, ///< SH2
201 CS_MODE_SH2A = 1 << 2, ///< SH2A
202 CS_MODE_SH3 = 1 << 3, ///< SH3
203 CS_MODE_SH4 = 1 << 4, ///< SH4
204 CS_MODE_SH4A = 1 << 5, ///< SH4A
205 CS_MODE_SHFPU = 1 << 6, ///< w/ FPU
206 CS_MODE_SHDSP = 1 << 7, ///< w/ DSP
207 CS_MODE_TRICORE_110 = 1 << 1, ///< Tricore 1.1
208 CS_MODE_TRICORE_120 = 1 << 2, ///< Tricore 1.2
209 CS_MODE_TRICORE_130 = 1 << 3, ///< Tricore 1.3
210 CS_MODE_TRICORE_131 = 1 << 4, ///< Tricore 1.3.1
211 CS_MODE_TRICORE_160 = 1 << 5, ///< Tricore 1.6
212 CS_MODE_TRICORE_161 = 1 << 6, ///< Tricore 1.6.1
213 CS_MODE_TRICORE_162 = 1 << 7, ///< Tricore 1.6.2
214 CS_MODE_TRICORE_180 = 1 << 8, ///< Tricore 1.8.0
215 CS_MODE_HPPA_11 = 1 << 1, ///< HPPA 1.1
216 CS_MODE_HPPA_20 = 1 << 2, ///< HPPA 2.0
217 CS_MODE_HPPA_20W = CS_MODE_HPPA_20 | (1 << 3), ///< HPPA 2.0 wide
218 CS_MODE_LOONGARCH32 = 1 << 0, ///< LoongArch32
219 CS_MODE_LOONGARCH64 = 1 << 1, ///< LoongArch64
220 CS_MODE_SYSTEMZ_ARCH8 = 1 << 1, ///< Enables features of the ARCH8 processor
221 CS_MODE_SYSTEMZ_ARCH9 = 1 << 2, ///< Enables features of the ARCH9 processor
222 CS_MODE_SYSTEMZ_ARCH10 = 1 << 3, ///< Enables features of the ARCH10 processor
223 CS_MODE_SYSTEMZ_ARCH11 = 1 << 4, ///< Enables features of the ARCH11 processor
224 CS_MODE_SYSTEMZ_ARCH12 = 1 << 5, ///< Enables features of the ARCH12 processor
225 CS_MODE_SYSTEMZ_ARCH13 = 1 << 6, ///< Enables features of the ARCH13 processor
226 CS_MODE_SYSTEMZ_ARCH14 = 1 << 7, ///< Enables features of the ARCH14 processor
227 CS_MODE_SYSTEMZ_Z10 = 1 << 8, ///< Enables features of the Z10 processor
228 CS_MODE_SYSTEMZ_Z196 = 1 << 9, ///< Enables features of the Z196 processor
229 CS_MODE_SYSTEMZ_ZEC12 = 1 << 10, ///< Enables features of the ZEC12 processor
230 CS_MODE_SYSTEMZ_Z13 = 1 << 11, ///< Enables features of the Z13 processor
231 CS_MODE_SYSTEMZ_Z14 = 1 << 12, ///< Enables features of the Z14 processor
232 CS_MODE_SYSTEMZ_Z15 = 1 << 13, ///< Enables features of the Z15 processor
233 CS_MODE_SYSTEMZ_Z16 = 1 << 14, ///< Enables features of the Z16 processor
234 CS_MODE_SYSTEMZ_GENERIC = 1 << 15, ///< Enables features of the generic processor
235 CS_MODE_XTENSA_ESP32 = 1 << 1, ///< Xtensa ESP32
236 CS_MODE_XTENSA_ESP32S2 = 1 << 2, ///< Xtensa ESP32S2
237 CS_MODE_XTENSA_ESP8266 = 1 << 3, ///< Xtensa ESP328266
238} cs_mode;
239 
240typedef void* (CAPSTONE_API *cs_malloc_t)(size_t size);
241typedef void* (CAPSTONE_API *cs_calloc_t)(size_t nmemb, size_t size);
242typedef void* (CAPSTONE_API *cs_realloc_t)(void *ptr, size_t size);
243typedef void (CAPSTONE_API *cs_free_t)(void *ptr);
244typedef int (CAPSTONE_API *cs_vsnprintf_t)(char *str, size_t size, const char *format, va_list ap);
245 
246 
247/// User-defined dynamic memory related functions: malloc/calloc/realloc/free/vsnprintf()
248/// By default, Capstone uses system's malloc(), calloc(), realloc(), free() & vsnprintf().
249typedef struct cs_opt_mem {
250 cs_malloc_t malloc;
251 cs_calloc_t calloc;
252 cs_realloc_t realloc;
253 cs_free_t free;
254 cs_vsnprintf_t vsnprintf;
255} cs_opt_mem;
256 
257/// Customize mnemonic for instructions with alternative name.
258/// To reset existing customized instruction to its default mnemonic,
259/// call cs_option(CS_OPT_MNEMONIC) again with the same @id and NULL value
260/// for @mnemonic.
261typedef struct cs_opt_mnem {
262 /// ID of instruction to be customized.
263 unsigned int id;
264 /// Customized instruction mnemonic.
265 const char *mnemonic;
266} cs_opt_mnem;
267 
268/// Runtime option for the disassembled engine
269typedef enum cs_opt_type {
270 CS_OPT_INVALID = 0, ///< No option specified
271 CS_OPT_SYNTAX, ///< Assembly output syntax
272 CS_OPT_DETAIL, ///< Break down instruction structure into details
273 CS_OPT_MODE, ///< Change engine's mode at run-time
274 CS_OPT_MEM, ///< User-defined dynamic memory related functions
275 CS_OPT_SKIPDATA, ///< Skip data when disassembling. Then engine is in SKIPDATA mode.
276 CS_OPT_SKIPDATA_SETUP, ///< Setup user-defined function for SKIPDATA option
277 CS_OPT_MNEMONIC, ///< Customize instruction mnemonic
278 CS_OPT_UNSIGNED, ///< print immediate operands in unsigned form
279 CS_OPT_ONLY_OFFSET_BRANCH, ///< ARM, PPC, AArch64: Don't add the branch immediate value to the PC.
280 CS_OPT_LITBASE, ///< Xtensa, set the LITBASE value. LITBASE is set to 0 by default.
281} cs_opt_type;
282 
283/// Runtime option value (associated with option type above)
284typedef enum cs_opt_value {
285 CS_OPT_OFF = 0, ///< Turn OFF an option - default for CS_OPT_DETAIL, CS_OPT_SKIPDATA, CS_OPT_UNSIGNED.
286 CS_OPT_ON = 1 << 0, ///< Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA).
287 CS_OPT_SYNTAX_DEFAULT = 1 << 1, ///< Default asm syntax (CS_OPT_SYNTAX).
288 CS_OPT_SYNTAX_INTEL = 1 << 2, ///< X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX).
289 CS_OPT_SYNTAX_ATT = 1 << 3, ///< X86 ATT asm syntax (CS_OPT_SYNTAX).
290 CS_OPT_SYNTAX_NOREGNAME = 1 << 4, ///< Prints register name with only number (CS_OPT_SYNTAX)
291 CS_OPT_SYNTAX_MASM = 1 << 5, ///< X86 Intel Masm syntax (CS_OPT_SYNTAX).
292 CS_OPT_SYNTAX_MOTOROLA = 1 << 6, ///< MOS65XX use $ as hex prefix
293 CS_OPT_SYNTAX_CS_REG_ALIAS = 1 << 7, ///< Prints common register alias which are not defined in LLVM (ARM: r9 = sb etc.)
294 CS_OPT_SYNTAX_PERCENT = 1 << 8, ///< Prints the % in front of PPC registers.
295 CS_OPT_SYNTAX_NO_DOLLAR = 1 << 9, ///< Does not print the $ in front of Mips, LoongArch registers.
296 CS_OPT_DETAIL_REAL = 1 << 1, ///< If enabled, always sets the real instruction detail. Even if the instruction is an alias.
297} cs_opt_value;
298 
299/// An option
300typedef struct {
301 cs_opt_type type; ///< The option type
302 cs_opt_value val; ///< The option value to set.
303} cs_opt;
304 
305/// Common instruction groups - to be consistent across all architectures.
306typedef enum cs_group_type {
307 CS_GRP_INVALID = 0, ///< uninitialized/invalid group.
308 CS_GRP_JUMP, ///< all jump instructions (conditional+direct+indirect jumps)
309 CS_GRP_CALL, ///< all call instructions
310 CS_GRP_RET, ///< all return instructions
311 CS_GRP_INT, ///< all interrupt instructions (int+syscall)
312 CS_GRP_IRET, ///< all interrupt return instructions
313 CS_GRP_PRIVILEGE, ///< all privileged instructions
314 CS_GRP_BRANCH_RELATIVE, ///< all relative branching instructions
315} cs_group_type;
316 
317/**
318 User-defined callback function for SKIPDATA option.
319 See tests/test_skipdata.c for sample code demonstrating this API.
320 
321 @code: the input buffer containing code to be disassembled.
322 This is the same buffer passed to cs_disasm().
323 @code_size: size (in bytes) of the above @code buffer.
324 @offset: the position of the currently-examining byte in the input
325 buffer @code mentioned above.
326 @user_data: user-data passed to cs_option() via @user_data field in
327 cs_opt_skipdata struct below.
328 
329 @return: return number of bytes to skip, or 0 to immediately stop disassembling.
330*/
331typedef size_t (CAPSTONE_API *cs_skipdata_cb_t)(const uint8_t *code, size_t code_size, size_t offset, void *user_data);
332 
333/// User-customized setup for SKIPDATA option
334typedef struct cs_opt_skipdata {
335 /// Capstone considers data to skip as special "instructions".
336 /// User can specify the string for this instruction's "mnemonic" here.
337 /// By default (if @mnemonic is NULL), Capstone use ".byte".
338 const char *mnemonic;
339 
340 /// User-defined callback function to be called when Capstone hits data.
341 /// If the returned value from this callback is positive (>0), Capstone
342 /// will skip exactly that number of bytes & continue. Otherwise, if
343 /// the callback returns 0, Capstone stops disassembling and returns
344 /// immediately from cs_disasm()
345 /// NOTE: if this callback pointer is NULL, Capstone would skip a number
346 /// of bytes depending on architectures, as following:
347 /// Arm: 2 bytes (Thumb mode) or 4 bytes.
348 /// AArch64: 4 bytes.
349 /// Mips: 4 bytes.
350 /// M680x: 1 byte.
351 /// PowerPC: 4 bytes.
352 /// Sparc: 4 bytes.
353 /// SystemZ: 2 bytes.
354 /// X86: 1 bytes.
355 /// XCore: 2 bytes.
356 /// EVM: 1 bytes.
357 /// RISCV: 4 bytes.
358 /// WASM: 1 bytes.
359 /// MOS65XX: 1 bytes.
360 /// BPF: 8 bytes.
361 /// TriCore: 2 bytes.
362 /// LoongArch: 4 bytes.
363 /// ARC: 2 bytes.
364 cs_skipdata_cb_t callback; // default value is NULL
365 
366 /// User-defined data to be passed to @callback function pointer.
367 void *user_data;
368} cs_opt_skipdata;
369 
370 
371#include "arm.h"
372#ifdef CAPSTONE_AARCH64_COMPAT_HEADER
373#include "arm64.h"
374#else
375#include "aarch64.h"
376#endif
377#include "m68k.h"
378#include "mips.h"
379#include "ppc.h"
380#include "sparc.h"
381#include "systemz.h"
382#include "x86.h"
383#include "xcore.h"
384#include "tms320c64x.h"
385#include "m680x.h"
386#include "evm.h"
387#include "riscv.h"
388#include "wasm.h"
389#include "mos65xx.h"
390#include "bpf.h"
391#include "sh.h"
392#include "tricore.h"
393#include "alpha.h"
394#include "hppa.h"
395#include "loongarch.h"
396#include "xtensa.h"
397#include "arc.h"
398 
399#define MAX_IMPL_W_REGS 47
400#define MAX_IMPL_R_REGS 20
401#define MAX_NUM_GROUPS 16
402 
403/// NOTE: All information in cs_detail is only available when CS_OPT_DETAIL = CS_OPT_ON
404/// Initialized as memset(., 0, offsetof(cs_detail, ARCH)+sizeof(cs_ARCH))
405/// by ARCH_getInstruction in arch/ARCH/ARCHDisassembler.c
406/// if cs_detail changes, in particular if a field is added after the union,
407/// then update arch/ARCH/ARCHDisassembler.c accordingly
408typedef struct cs_detail {
409 uint16_t regs_read
410 [MAX_IMPL_R_REGS]; ///< list of implicit registers read by this insn
411 uint8_t regs_read_count; ///< number of implicit registers read by this insn
412 
413 uint16_t regs_write
414 [MAX_IMPL_W_REGS]; ///< list of implicit registers modified by this insn
415 uint8_t regs_write_count; ///< number of implicit registers modified by this insn
416 
417 uint8_t groups[MAX_NUM_GROUPS]; ///< list of group this instruction belong to
418 uint8_t groups_count; ///< number of groups this insn belongs to
419 
420 bool writeback; ///< Instruction has writeback operands.
421 
422 /// Architecture-specific instruction info
423 union {
424 cs_x86 x86; ///< X86 architecture, including 16-bit, 32-bit & 64-bit mode
425#ifdef CAPSTONE_AARCH64_COMPAT_HEADER
426 cs_arm64 arm64;
427#else
428 cs_aarch64 aarch64; ///< AArch6464 architecture (aka ARM64)
429#endif
430 
431#ifdef CAPSTONE_SYSTEMZ_COMPAT_HEADER
432 cs_sysz sysz; ///< SystemZ architecture
433#else
434 cs_systemz systemz; ///< SystemZ architecture (aka SysZ)
435#endif
436 cs_arm arm; ///< ARM architecture (including Thumb/Thumb2)
437 cs_m68k m68k; ///< M68K architecture
438 cs_mips mips; ///< MIPS architecture
439 cs_ppc ppc; ///< PowerPC architecture
440 cs_sparc sparc; ///< Sparc architecture
441 cs_xcore xcore; ///< XCore architecture
442 cs_tms320c64x tms320c64x; ///< TMS320C64x architecture
443 cs_m680x m680x; ///< M680X architecture
444 cs_evm evm; ///< Ethereum architecture
445 cs_mos65xx mos65xx; ///< MOS65XX architecture (including MOS6502)
446 cs_wasm wasm; ///< Web Assembly architecture
447 cs_bpf bpf; ///< Berkeley Packet Filter architecture (including eBPF)
448 cs_riscv riscv; ///< RISCV architecture
449 cs_sh sh; ///< SH architecture
450 cs_tricore tricore; ///< TriCore architecture
451 cs_alpha alpha; ///< Alpha architecture
452 cs_hppa hppa; ///< HPPA architecture
453 cs_loongarch loongarch; ///< LoongArch architecture
454 cs_xtensa xtensa; ///< Xtensa architecture
455 cs_arc arc; ///< ARC architecture
456 };
457} cs_detail;
458 
459/// Detail information of disassembled instruction
460typedef struct cs_insn {
461 /// Instruction ID (basically a numeric ID for the instruction mnemonic)
462 /// Find the instruction id in the '[ARCH]_insn' enum in the header file
463 /// of corresponding architecture, such as 'arm_insn' in arm.h for ARM,
464 /// 'x86_insn' in x86.h for X86, etc...
465 /// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
466 /// NOTE: in Skipdata mode, "data" instruction has 0 for this id field.
467 unsigned int id;
468 
469 /// If this instruction is an alias instruction, this member is set with
470 /// the alias ID.
471 /// Otherwise to <ARCH>_INS_INVALID.
472 /// -- Only supported by auto-sync archs --
473 uint64_t alias_id;
474 
475 /// Address (EIP) of this instruction
476 /// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
477 uint64_t address;
478 
479 /// Size of this instruction
480 /// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
481 uint16_t size;
482 
483 /// Machine bytes of this instruction, with number of bytes indicated by @size above
484 /// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
485 uint8_t bytes[24];
486 
487 /// Ascii text of instruction mnemonic
488 /// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
489 char mnemonic[CS_MNEMONIC_SIZE];
490 
491 /// Ascii text of instruction operands
492 /// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
493 char op_str[160];
494 
495 /// True: This instruction is an alias.
496 /// False: Otherwise.
497 /// -- Only supported by auto-sync archs --
498 bool is_alias;
499 
500 /// True: The operands are the ones of the alias instructions.
501 /// False: The detail operands are from the real instruction.
502 bool usesAliasDetails;
503 
504 /// Pointer to cs_detail.
505 /// NOTE: detail pointer is only valid when both requirements below are met:
506 /// (1) CS_OP_DETAIL = CS_OPT_ON
507 /// (2) Engine is not in Skipdata mode (CS_OP_SKIPDATA option set to CS_OPT_ON)
508 ///
509 /// NOTE 2: when in Skipdata mode, or when detail mode is OFF, even if this pointer
510 /// is not NULL, its content is still irrelevant.
511 cs_detail *detail;
512} cs_insn;
513 
514 
515/// Calculate the offset of a disassembled instruction in its buffer, given its position
516/// in its array of disassembled insn
517/// NOTE: this macro works with position (>=1), not index
518#define CS_INSN_OFFSET(insns, post) (insns[post - 1].address - insns[0].address)
519 
520 
521/// All type of errors encountered by Capstone API.
522/// These are values returned by cs_errno()
523typedef enum cs_err {
524 CS_ERR_OK = 0, ///< No error: everything was fine
525 CS_ERR_MEM, ///< Out-Of-Memory error: cs_open(), cs_disasm(), cs_disasm_iter()
526 CS_ERR_ARCH, ///< Unsupported architecture: cs_open()
527 CS_ERR_HANDLE, ///< Invalid handle: cs_op_count(), cs_op_index()
528 CS_ERR_CSH, ///< Invalid csh argument: cs_close(), cs_errno(), cs_option()
529 CS_ERR_MODE, ///< Invalid/unsupported mode: cs_open()
530 CS_ERR_OPTION, ///< Invalid/unsupported option: cs_option()
531 CS_ERR_DETAIL, ///< Information is unavailable because detail option is OFF
532 CS_ERR_MEMSETUP, ///< Dynamic memory management uninitialized (see CS_OPT_MEM)
533 CS_ERR_VERSION, ///< Unsupported version (bindings)
534 CS_ERR_DIET, ///< Access irrelevant data in "diet" engine
535 CS_ERR_SKIPDATA, ///< Access irrelevant data for "data" instruction in SKIPDATA mode
536 CS_ERR_X86_ATT, ///< X86 AT&T syntax is unsupported (opt-out at compile time)
537 CS_ERR_X86_INTEL, ///< X86 Intel syntax is unsupported (opt-out at compile time)
538 CS_ERR_X86_MASM, ///< X86 Masm syntax is unsupported (opt-out at compile time)
539} cs_err;
540 
541/**
542 Return combined API version & major and minor version numbers.
543 
544 @major: major number of API version
545 @minor: minor number of API version
546 
547 @return hexical number as (major << 8 | minor), which encodes both
548 major & minor versions.
549 NOTE: This returned value can be compared with version number made
550 with macro CS_MAKE_VERSION
551 
552 For example, second API version would return 1 in @major, and 1 in @minor
553 The return value would be 0x0101
554 
555 NOTE: if you only care about returned value, but not major and minor values,
556 set both @major & @minor arguments to NULL.
557*/
558CAPSTONE_EXPORT
559unsigned int CAPSTONE_API cs_version(int *major, int *minor);
560 
561CAPSTONE_EXPORT
562void CAPSTONE_API cs_arch_register_arm(void);
563CAPSTONE_EXPORT
564void CAPSTONE_API cs_arch_register_aarch64(void);
565#ifdef CAPSTONE_AARCH64_COMPAT_HEADER
566#define cs_arch_register_aarch64 cs_arch_register_arm64
567#endif
568CAPSTONE_EXPORT
569void CAPSTONE_API cs_arch_register_mips(void);
570CAPSTONE_EXPORT
571void CAPSTONE_API cs_arch_register_x86(void);
572CAPSTONE_EXPORT
573void CAPSTONE_API cs_arch_register_powerpc(void);
574CAPSTONE_EXPORT
575void CAPSTONE_API cs_arch_register_sparc(void);
576CAPSTONE_EXPORT
577void CAPSTONE_API cs_arch_register_systemz(void);
578#ifdef CAPSTONE_SYSTEMZ_COMPAT_HEADER
579#define cs_arch_register_sysz cs_arch_register_systemz
580#endif
581CAPSTONE_EXPORT
582void CAPSTONE_API cs_arch_register_xcore(void);
583CAPSTONE_EXPORT
584void CAPSTONE_API cs_arch_register_m68k(void);
585CAPSTONE_EXPORT
586void CAPSTONE_API cs_arch_register_tms320c64x(void);
587CAPSTONE_EXPORT
588void CAPSTONE_API cs_arch_register_m680x(void);
589CAPSTONE_EXPORT
590void CAPSTONE_API cs_arch_register_evm(void);
591CAPSTONE_EXPORT
592void CAPSTONE_API cs_arch_register_mos65xx(void);
593CAPSTONE_EXPORT
594void CAPSTONE_API cs_arch_register_wasm(void);
595CAPSTONE_EXPORT
596void CAPSTONE_API cs_arch_register_bpf(void);
597CAPSTONE_EXPORT
598void CAPSTONE_API cs_arch_register_riscv(void);
599CAPSTONE_EXPORT
600void CAPSTONE_API cs_arch_register_sh(void);
601CAPSTONE_EXPORT
602void CAPSTONE_API cs_arch_register_tricore(void);
603CAPSTONE_EXPORT
604void CAPSTONE_API cs_arch_register_alpha(void);
605CAPSTONE_EXPORT
606void CAPSTONE_API cs_arch_register_loongarch(void);
607CAPSTONE_EXPORT
608void CAPSTONE_API cs_arch_register_arc(void);
609 
610/**
611 This API can be used to either ask for archs supported by this library,
612 or check to see if the library was compile with 'diet' option (or called
613 in 'diet' mode).
614 
615 To check if a particular arch is supported by this library, set @query to
616 arch mode (CS_ARCH_* value).
617 To verify if this library supports all the archs, use CS_ARCH_ALL.
618 
619 To check if this library is in 'diet' mode, set @query to CS_SUPPORT_DIET.
620 
621 @return True if this library supports the given arch, or in 'diet' mode.
622*/
623CAPSTONE_EXPORT
624bool CAPSTONE_API cs_support(int query);
625 
626/**
627 Initialize CS handle: this must be done before any usage of CS.
628 
629 @arch: architecture type (CS_ARCH_*)
630 @mode: hardware mode. This is combined of CS_MODE_*
631 @handle: pointer to handle, which will be updated at return time
632 
633 @return CS_ERR_OK on success, or other value on failure (refer to cs_err enum
634 for detailed error).
635*/
636CAPSTONE_EXPORT
637cs_err CAPSTONE_API cs_open(cs_arch arch, cs_mode mode, csh *handle);
638 
639/**
640 Close CS handle: MUST do to release the handle when it is not used anymore.
641 NOTE: this must be only called when there is no longer usage of Capstone,
642 not even access to cs_insn array. The reason is the this API releases some
643 cached memory, thus access to any Capstone API after cs_close() might crash
644 your application.
645 
646 In fact,this API invalidate @handle by ZERO out its value (i.e *handle = 0).
647 
648 @handle: pointer to a handle returned by cs_open()
649 
650 @return CS_ERR_OK on success, or other value on failure (refer to cs_err enum
651 for detailed error).
652*/
653CAPSTONE_EXPORT
654cs_err CAPSTONE_API cs_close(csh *handle);
655 
656/**
657 Set option for disassembling engine at runtime
658 
659 @handle: handle returned by cs_open()
660 @type: type of option to be set
661 @value: option value corresponding with @type
662 
663 @return: CS_ERR_OK on success, or other value on failure.
664 Refer to cs_err enum for detailed error.
665 
666 NOTE: in the case of CS_OPT_MEM, handle's value can be anything,
667 so that cs_option(handle, CS_OPT_MEM, value) can (i.e must) be called
668 even before cs_open()
669*/
670CAPSTONE_EXPORT
671cs_err CAPSTONE_API cs_option(csh handle, cs_opt_type type, size_t value);
672 
673/**
674 Report the last error number when some API function fail.
675 Like glibc's errno, cs_errno might not retain its old value once accessed.
676 
677 @handle: handle returned by cs_open()
678 
679 @return: error code of cs_err enum type (CS_ERR_*, see above)
680*/
681CAPSTONE_EXPORT
682cs_err CAPSTONE_API cs_errno(csh handle);
683 
684 
685/**
686 Return a string describing given error code.
687 
688 @code: error code (see CS_ERR_* above)
689 
690 @return: returns a pointer to a string that describes the error code
691 passed in the argument @code
692*/
693CAPSTONE_EXPORT
694const char * CAPSTONE_API cs_strerror(cs_err code);
695 
696/**
697 Disassemble binary code, given the code buffer, size, address and number
698 of instructions to be decoded.
699 This API dynamically allocate memory to contain disassembled instruction.
700 Resulting instructions will be put into @*insn
701 
702 NOTE 1: this API will automatically determine memory needed to contain
703 output disassembled instructions in @insn.
704 
705 NOTE 2: caller must free the allocated memory itself to avoid memory leaking.
706 
707 NOTE 3: for system with scarce memory to be dynamically allocated such as
708 OS kernel or firmware, the API cs_disasm_iter() might be a better choice than
709 cs_disasm(). The reason is that with cs_disasm(), based on limited available
710 memory, we have to calculate in advance how many instructions to be disassembled,
711 which complicates things. This is especially troublesome for the case @count=0,
712 when cs_disasm() runs uncontrollably (until either end of input buffer, or
713 when it encounters an invalid instruction).
714
715 @handle: handle returned by cs_open()
716 @code: buffer containing raw binary code to be disassembled.
717 @code_size: size of the above code buffer.
718 @address: address of the first instruction in given raw code buffer.
719 @insn: array of instructions filled in by this API.
720 NOTE: @insn will be allocated by this function, and should be freed
721 with cs_free() API.
722 @count: number of instructions to be disassembled, or 0 to get all of them
723 
724 @return: the number of successfully disassembled instructions,
725 or 0 if this function failed to disassemble the given code
726 
727 On failure, call cs_errno() for error code.
728*/
729CAPSTONE_EXPORT
730size_t CAPSTONE_API cs_disasm(csh handle,
731 const uint8_t *code, size_t code_size,
732 uint64_t address,
733 size_t count,
734 cs_insn **insn);
735 
736/**
737 Free memory allocated by cs_malloc() or cs_disasm() (argument @insn)
738 
739 @insn: pointer returned by @insn argument in cs_disasm() or cs_malloc()
740 @count: number of cs_insn structures returned by cs_disasm(), or 1
741 to free memory allocated by cs_malloc().
742*/
743CAPSTONE_EXPORT
744void CAPSTONE_API cs_free(cs_insn *insn, size_t count);
745 
746 
747/**
748 Allocate memory for 1 instruction to be used by cs_disasm_iter().
749 
750 @handle: handle returned by cs_open()
751 
752 NOTE: when no longer in use, you can reclaim the memory allocated for
753 this instruction with cs_free(insn, 1)
754*/
755CAPSTONE_EXPORT
756cs_insn * CAPSTONE_API cs_malloc(csh handle);
757 
758/**
759 Fast API to disassemble binary code, given the code buffer, size, address
760 and number of instructions to be decoded.
761 This API puts the resulting instruction into a given cache in @insn.
762 See tests/test_iter.c for sample code demonstrating this API.
763 
764 NOTE 1: this API will update @code, @size & @address to point to the next
765 instruction in the input buffer. Therefore, it is convenient to use
766 cs_disasm_iter() inside a loop to quickly iterate all the instructions.
767 While decoding one instruction at a time can also be achieved with
768 cs_disasm(count=1), some benchmarks shown that cs_disasm_iter() can be 30%
769 faster on random input.
770 
771 NOTE 2: the cache in @insn can be created with cs_malloc() API.
772 
773 NOTE 3: for system with scarce memory to be dynamically allocated such as
774 OS kernel or firmware, this API is recommended over cs_disasm(), which
775 allocates memory based on the number of instructions to be disassembled.
776 The reason is that with cs_disasm(), based on limited available memory,
777 we have to calculate in advance how many instructions to be disassembled,
778 which complicates things. This is especially troublesome for the case
779 @count=0, when cs_disasm() runs uncontrollably (until either end of input
780 buffer, or when it encounters an invalid instruction).
781
782 @handle: handle returned by cs_open()
783 @code: buffer containing raw binary code to be disassembled
784 @size: size of above code
785 @address: address of the first insn in given raw code buffer
786 @insn: pointer to instruction to be filled in by this API.
787 
788 @return: true if this API successfully decode 1 instruction,
789 or false otherwise.
790 
791 On failure, call cs_errno() for error code.
792*/
793CAPSTONE_EXPORT
794bool CAPSTONE_API cs_disasm_iter(csh handle,
795 const uint8_t **code, size_t *size,
796 uint64_t *address, cs_insn *insn);
797 
798/**
799 Return friendly name of register in a string.
800 Find the instruction id from header file of corresponding architecture (arm.h for ARM,
801 x86.h for X86, ...)
802 
803 WARN: when in 'diet' mode, this API is irrelevant because engine does not
804 store register name.
805 
806 @handle: handle returned by cs_open()
807 @reg_id: register id
808 
809 @return: string name of the register, or NULL if @reg_id is invalid.
810*/
811CAPSTONE_EXPORT
812const char * CAPSTONE_API cs_reg_name(csh handle, unsigned int reg_id);
813 
814/**
815 Return friendly name of an instruction in a string.
816 Find the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
817 
818 WARN: when in 'diet' mode, this API is irrelevant because the engine does not
819 store instruction name.
820 
821 @handle: handle returned by cs_open()
822 @insn_id: instruction id
823 
824 @return: string name of the instruction, or NULL if @insn_id is invalid.
825*/
826CAPSTONE_EXPORT
827const char * CAPSTONE_API cs_insn_name(csh handle, unsigned int insn_id);
828 
829/**
830 Return friendly name of a group id (that an instruction can belong to)
831 Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
832 
833 WARN: when in 'diet' mode, this API is irrelevant because the engine does not
834 store group name.
835 
836 @handle: handle returned by cs_open()
837 @group_id: group id
838 
839 @return: string name of the group, or NULL if @group_id is invalid.
840*/
841CAPSTONE_EXPORT
842const char * CAPSTONE_API cs_group_name(csh handle, unsigned int group_id);
843 
844/**
845 Check if a disassembled instruction belong to a particular group.
846 Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
847 Internally, this simply verifies if @group_id matches any member of insn->groups array.
848 
849 NOTE: this API is only valid when detail option is ON (which is OFF by default).
850 
851 WARN: when in 'diet' mode, this API is irrelevant because the engine does not
852 update @groups array.
853 
854 @handle: handle returned by cs_open()
855 @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
856 @group_id: group that you want to check if this instruction belong to.
857 
858 @return: true if this instruction indeed belongs to the given group, or false otherwise.
859*/
860CAPSTONE_EXPORT
861bool CAPSTONE_API cs_insn_group(csh handle, const cs_insn *insn, unsigned int group_id);
862 
863/**
864 Check if a disassembled instruction IMPLICITLY used a particular register.
865 Find the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
866 Internally, this simply verifies if @reg_id matches any member of insn->regs_read array.
867 
868 NOTE: this API is only valid when detail option is ON (which is OFF by default)
869 
870 WARN: when in 'diet' mode, this API is irrelevant because the engine does not
871 update @regs_read array.
872 
873 @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
874 @reg_id: register that you want to check if this instruction used it.
875 
876 @return: true if this instruction indeed implicitly used the given register, or false otherwise.
877*/
878CAPSTONE_EXPORT
879bool CAPSTONE_API cs_reg_read(csh handle, const cs_insn *insn, unsigned int reg_id);
880 
881/**
882 Check if a disassembled instruction IMPLICITLY modified a particular register.
883 Find the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
884 Internally, this simply verifies if @reg_id matches any member of insn->regs_write array.
885 
886 NOTE: this API is only valid when detail option is ON (which is OFF by default)
887 
888 WARN: when in 'diet' mode, this API is irrelevant because the engine does not
889 update @regs_write array.
890 
891 @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
892 @reg_id: register that you want to check if this instruction modified it.
893 
894 @return: true if this instruction indeed implicitly modified the given register, or false otherwise.
895*/
896CAPSTONE_EXPORT
897bool CAPSTONE_API cs_reg_write(csh handle, const cs_insn *insn, unsigned int reg_id);
898 
899/**
900 Count the number of operands of a given type.
901 Find the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
902 
903 NOTE: this API is only valid when detail option is ON (which is OFF by default)
904 
905 @handle: handle returned by cs_open()
906 @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
907 @op_type: Operand type to be found.
908 
909 @return: number of operands of given type @op_type in instruction @insn,
910 or -1 on failure.
911*/
912CAPSTONE_EXPORT
913int CAPSTONE_API cs_op_count(csh handle, const cs_insn *insn, unsigned int op_type);
914 
915/**
916 Retrieve the position of operand of given type in <arch>.operands[] array.
917 Later, the operand can be accessed using the returned position.
918 Find the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
919 
920 NOTE: this API is only valid when detail option is ON (which is OFF by default)
921 
922 @handle: handle returned by cs_open()
923 @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
924 @op_type: Operand type to be found.
925 @position: position of the operand to be found. This must be in the range
926 [1, cs_op_count(handle, insn, op_type)]
927 
928 @return: index of operand of given type @op_type in <arch>.operands[] array
929 in instruction @insn, or -1 on failure.
930*/
931CAPSTONE_EXPORT
932int CAPSTONE_API cs_op_index(csh handle, const cs_insn *insn, unsigned int op_type,
933 unsigned int position);
934 
935/// Type of array to keep the list of registers
936typedef uint16_t cs_regs[64];
937 
938/**
939 Retrieve all the registers accessed by an instruction, either explicitly or
940 implicitly.
941 
942 WARN: when in 'diet' mode, this API is irrelevant because engine does not
943 store registers.
944 
945 @handle: handle returned by cs_open()
946 @insn: disassembled instruction structure returned from cs_disasm() or cs_disasm_iter()
947 @regs_read: on return, this array contains all registers read by instruction.
948 @regs_read_count: number of registers kept inside @regs_read array.
949 @regs_write: on return, this array contains all registers written by instruction.
950 @regs_write_count: number of registers kept inside @regs_write array.
951 
952 @return CS_ERR_OK on success, or other value on failure (refer to cs_err enum
953 for detailed error).
954*/
955CAPSTONE_EXPORT
956cs_err CAPSTONE_API cs_regs_access(csh handle, const cs_insn *insn,
957 cs_regs regs_read, uint8_t *regs_read_count,
958 cs_regs regs_write, uint8_t *regs_write_count);
959 
960#ifdef __cplusplus
961}
962#endif
963 
964#endif
965