Hermes/Dyforge is a program written in c++ allows you to inject a dll that can analyze all processes in a program, can be used for mod and reverse engeneering
| 1 | #ifndef CAPSTONE_ARM64_H |
| 2 | #define CAPSTONE_ARM64_H |
| 3 | |
| 4 | /* Capstone Disassembly Engine */ |
| 5 | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ |
| 6 | |
| 7 | #ifdef __cplusplus |
| 8 | extern "C" { |
| 9 | #endif |
| 10 | |
| 11 | #include "aarch64.h" |
| 12 | #include "cs_operand.h" |
| 13 | #include "platform.h" |
| 14 | |
| 15 | #include <assert.h> |
| 16 | |
| 17 | #ifdef _MSC_VER |
| 18 | #pragma warning(disable : 4201) |
| 19 | #endif |
| 20 | |
| 21 | typedef enum { |
| 22 | ARM64_SFT_INVALID = AARCH64_SFT_INVALID, |
| 23 | ARM64_SFT_LSL = AARCH64_SFT_LSL, |
| 24 | ARM64_SFT_MSL = AARCH64_SFT_MSL, |
| 25 | ARM64_SFT_LSR = AARCH64_SFT_LSR, |
| 26 | ARM64_SFT_ASR = AARCH64_SFT_ASR, |
| 27 | ARM64_SFT_ROR = AARCH64_SFT_ROR, |
| 28 | ARM64_SFT_LSL_REG = AARCH64_SFT_LSL_REG, |
| 29 | ARM64_SFT_MSL_REG = AARCH64_SFT_MSL_REG, |
| 30 | ARM64_SFT_LSR_REG = AARCH64_SFT_LSR_REG, |
| 31 | ARM64_SFT_ASR_REG = AARCH64_SFT_ASR_REG, |
| 32 | ARM64_SFT_ROR_REG = AARCH64_SFT_ROR_REG, |
| 33 | } arm64_shifter; |
| 34 | |
| 35 | typedef enum { |
| 36 | ARM64_EXT_INVALID = AARCH64_EXT_INVALID, |
| 37 | ARM64_EXT_UXTB = AARCH64_EXT_UXTB, |
| 38 | ARM64_EXT_UXTH = AARCH64_EXT_UXTH, |
| 39 | ARM64_EXT_UXTW = AARCH64_EXT_UXTW, |
| 40 | ARM64_EXT_UXTX = AARCH64_EXT_UXTX, |
| 41 | ARM64_EXT_SXTB = AARCH64_EXT_SXTB, |
| 42 | ARM64_EXT_SXTH = AARCH64_EXT_SXTH, |
| 43 | ARM64_EXT_SXTW = AARCH64_EXT_SXTW, |
| 44 | ARM64_EXT_SXTX = AARCH64_EXT_SXTX, |
| 45 | } arm64_extender; |
| 46 | |
| 47 | typedef enum { |
| 48 | ARM64LAYOUT_INVALID = AARCH64LAYOUT_INVALID, |
| 49 | ARM64LAYOUT_VL_B = AARCH64LAYOUT_VL_B, |
| 50 | ARM64LAYOUT_VL_H = AARCH64LAYOUT_VL_H, |
| 51 | ARM64LAYOUT_VL_S = AARCH64LAYOUT_VL_S, |
| 52 | ARM64LAYOUT_VL_D = AARCH64LAYOUT_VL_D, |
| 53 | ARM64LAYOUT_VL_Q = AARCH64LAYOUT_VL_Q, |
| 54 | |
| 55 | ARM64LAYOUT_VL_4B = AARCH64LAYOUT_VL_4B, |
| 56 | ARM64LAYOUT_VL_2H = AARCH64LAYOUT_VL_2H, |
| 57 | ARM64LAYOUT_VL_1S = AARCH64LAYOUT_VL_1S, |
| 58 | |
| 59 | ARM64LAYOUT_VL_8B = AARCH64LAYOUT_VL_8B, |
| 60 | ARM64LAYOUT_VL_4H = AARCH64LAYOUT_VL_4H, |
| 61 | ARM64LAYOUT_VL_2S = AARCH64LAYOUT_VL_2S, |
| 62 | ARM64LAYOUT_VL_1D = AARCH64LAYOUT_VL_1D, |
| 63 | |
| 64 | ARM64LAYOUT_VL_16B = AARCH64LAYOUT_VL_16B, |
| 65 | ARM64LAYOUT_VL_8H = AARCH64LAYOUT_VL_8H, |
| 66 | ARM64LAYOUT_VL_4S = AARCH64LAYOUT_VL_4S, |
| 67 | ARM64LAYOUT_VL_2D = AARCH64LAYOUT_VL_2D, |
| 68 | ARM64LAYOUT_VL_1Q = AARCH64LAYOUT_VL_1Q, |
| 69 | |
| 70 | ARM64LAYOUT_VL_64B = AARCH64LAYOUT_VL_64B, |
| 71 | ARM64LAYOUT_VL_32H = AARCH64LAYOUT_VL_32H, |
| 72 | ARM64LAYOUT_VL_16S = AARCH64LAYOUT_VL_16S, |
| 73 | ARM64LAYOUT_VL_8D = AARCH64LAYOUT_VL_8D, |
| 74 | |
| 75 | ARM64LAYOUT_VL_COMPLETE = AARCH64LAYOUT_VL_COMPLETE, |
| 76 | } ARM64Layout_VectorLayout; |
| 77 | |
| 78 | |
| 79 | typedef enum { |
| 80 | ARM64CC_EQ = AArch64CC_EQ, |
| 81 | ARM64CC_NE = AArch64CC_NE, |
| 82 | ARM64CC_HS = AArch64CC_HS, |
| 83 | ARM64CC_LO = AArch64CC_LO, |
| 84 | ARM64CC_MI = AArch64CC_MI, |
| 85 | ARM64CC_PL = AArch64CC_PL, |
| 86 | ARM64CC_VS = AArch64CC_VS, |
| 87 | ARM64CC_VC = AArch64CC_VC, |
| 88 | ARM64CC_HI = AArch64CC_HI, |
| 89 | ARM64CC_LS = AArch64CC_LS, |
| 90 | ARM64CC_GE = AArch64CC_GE, |
| 91 | ARM64CC_LT = AArch64CC_LT, |
| 92 | ARM64CC_GT = AArch64CC_GT, |
| 93 | ARM64CC_LE = AArch64CC_LE, |
| 94 | ARM64CC_AL = AArch64CC_AL, |
| 95 | ARM64CC_NV = AArch64CC_NV, |
| 96 | ARM64CC_Invalid = AArch64CC_Invalid, |
| 97 | |
| 98 | ARM64CC_ANY_ACTIVE = AArch64CC_ANY_ACTIVE, |
| 99 | ARM64CC_FIRST_ACTIVE = AArch64CC_FIRST_ACTIVE, |
| 100 | ARM64CC_LAST_ACTIVE = AArch64CC_LAST_ACTIVE, |
| 101 | ARM64CC_NONE_ACTIVE = AArch64CC_NONE_ACTIVE, |
| 102 | } ARM64CC_CondCode; |
| 103 | |
| 104 | inline static const char *ARM64CC_getCondCodeName(ARM64CC_CondCode Code) |
| 105 | { |
| 106 | switch (Code) { |
| 107 | default: |
| 108 | assert(0 && "Unknown condition code"); |
| 109 | case ARM64CC_EQ: |
| 110 | return "eq"; |
| 111 | case ARM64CC_NE: |
| 112 | return "ne"; |
| 113 | case ARM64CC_HS: |
| 114 | return "hs"; |
| 115 | case ARM64CC_LO: |
| 116 | return "lo"; |
| 117 | case ARM64CC_MI: |
| 118 | return "mi"; |
| 119 | case ARM64CC_PL: |
| 120 | return "pl"; |
| 121 | case ARM64CC_VS: |
| 122 | return "vs"; |
| 123 | case ARM64CC_VC: |
| 124 | return "vc"; |
| 125 | case ARM64CC_HI: |
| 126 | return "hi"; |
| 127 | case ARM64CC_LS: |
| 128 | return "ls"; |
| 129 | case ARM64CC_GE: |
| 130 | return "ge"; |
| 131 | case ARM64CC_LT: |
| 132 | return "lt"; |
| 133 | case ARM64CC_GT: |
| 134 | return "gt"; |
| 135 | case ARM64CC_LE: |
| 136 | return "le"; |
| 137 | case ARM64CC_AL: |
| 138 | return "al"; |
| 139 | case ARM64CC_NV: |
| 140 | return "nv"; |
| 141 | } |
| 142 | } |
| 143 | |
| 144 | inline static ARM64CC_CondCode ARM64CC_getInvertedCondCode(ARM64CC_CondCode Code) |
| 145 | { |
| 146 | |
| 147 | return (ARM64CC_CondCode)((unsigned)(Code) ^ 0x1); |
| 148 | } |
| 149 | |
| 150 | inline static unsigned ARM64CC_getNZCVToSatisfyCondCode(ARM64CC_CondCode Code) |
| 151 | { |
| 152 | enum { N = 8, Z = 4, C = 2, V = 1 }; |
| 153 | switch (Code) { |
| 154 | default: |
| 155 | assert(0 && "Unknown condition code"); |
| 156 | case ARM64CC_EQ: |
| 157 | return Z; // Z == 1 |
| 158 | case ARM64CC_NE: |
| 159 | return 0; // Z == 0 |
| 160 | case ARM64CC_HS: |
| 161 | return C; // C == 1 |
| 162 | case ARM64CC_LO: |
| 163 | return 0; // C == 0 |
| 164 | case ARM64CC_MI: |
| 165 | return N; // N == 1 |
| 166 | case ARM64CC_PL: |
| 167 | return 0; // N == 0 |
| 168 | case ARM64CC_VS: |
| 169 | return V; // V == 1 |
| 170 | case ARM64CC_VC: |
| 171 | return 0; // V == 0 |
| 172 | case ARM64CC_HI: |
| 173 | return C; // C == 1 && Z == 0 |
| 174 | case ARM64CC_LS: |
| 175 | return 0; // C == 0 || Z == 1 |
| 176 | case ARM64CC_GE: |
| 177 | return 0; // N == V |
| 178 | case ARM64CC_LT: |
| 179 | return N; // N != V |
| 180 | case ARM64CC_GT: |
| 181 | return 0; // Z == 0 && N == V |
| 182 | case ARM64CC_LE: |
| 183 | return Z; // Z == 1 || N != V |
| 184 | } |
| 185 | } |
| 186 | |
| 187 | inline static bool ARM64CC_isReflexive(ARM64CC_CondCode Code) |
| 188 | { |
| 189 | switch (Code) { |
| 190 | case ARM64CC_EQ: |
| 191 | case ARM64CC_HS: |
| 192 | case ARM64CC_PL: |
| 193 | case ARM64CC_LS: |
| 194 | case ARM64CC_GE: |
| 195 | case ARM64CC_LE: |
| 196 | case ARM64CC_AL: |
| 197 | case ARM64CC_NV: |
| 198 | return true; |
| 199 | default: |
| 200 | return false; |
| 201 | } |
| 202 | } |
| 203 | |
| 204 | inline static bool ARM64CC_isIrreflexive(ARM64CC_CondCode Code) |
| 205 | { |
| 206 | switch (Code) { |
| 207 | case ARM64CC_NE: |
| 208 | case ARM64CC_LO: |
| 209 | case ARM64CC_MI: |
| 210 | case ARM64CC_HI: |
| 211 | case ARM64CC_LT: |
| 212 | case ARM64CC_GT: |
| 213 | return true; |
| 214 | default: |
| 215 | return false; |
| 216 | } |
| 217 | } |
| 218 | |
| 219 | |
| 220 | typedef enum { |
| 221 | |
| 222 | ARM64_TLBI_ALLE1 = AARCH64_TLBI_ALLE1, |
| 223 | ARM64_TLBI_ALLE1IS = AARCH64_TLBI_ALLE1IS, |
| 224 | ARM64_TLBI_ALLE1ISNXS = AARCH64_TLBI_ALLE1ISNXS, |
| 225 | ARM64_TLBI_ALLE1NXS = AARCH64_TLBI_ALLE1NXS, |
| 226 | ARM64_TLBI_ALLE1OS = AARCH64_TLBI_ALLE1OS, |
| 227 | ARM64_TLBI_ALLE1OSNXS = AARCH64_TLBI_ALLE1OSNXS, |
| 228 | ARM64_TLBI_ALLE2 = AARCH64_TLBI_ALLE2, |
| 229 | ARM64_TLBI_ALLE2IS = AARCH64_TLBI_ALLE2IS, |
| 230 | ARM64_TLBI_ALLE2ISNXS = AARCH64_TLBI_ALLE2ISNXS, |
| 231 | ARM64_TLBI_ALLE2NXS = AARCH64_TLBI_ALLE2NXS, |
| 232 | ARM64_TLBI_ALLE2OS = AARCH64_TLBI_ALLE2OS, |
| 233 | ARM64_TLBI_ALLE2OSNXS = AARCH64_TLBI_ALLE2OSNXS, |
| 234 | ARM64_TLBI_ALLE3 = AARCH64_TLBI_ALLE3, |
| 235 | ARM64_TLBI_ALLE3IS = AARCH64_TLBI_ALLE3IS, |
| 236 | ARM64_TLBI_ALLE3ISNXS = AARCH64_TLBI_ALLE3ISNXS, |
| 237 | ARM64_TLBI_ALLE3NXS = AARCH64_TLBI_ALLE3NXS, |
| 238 | ARM64_TLBI_ALLE3OS = AARCH64_TLBI_ALLE3OS, |
| 239 | ARM64_TLBI_ALLE3OSNXS = AARCH64_TLBI_ALLE3OSNXS, |
| 240 | ARM64_TLBI_ASIDE1 = AARCH64_TLBI_ASIDE1, |
| 241 | ARM64_TLBI_ASIDE1IS = AARCH64_TLBI_ASIDE1IS, |
| 242 | ARM64_TLBI_ASIDE1ISNXS = AARCH64_TLBI_ASIDE1ISNXS, |
| 243 | ARM64_TLBI_ASIDE1NXS = AARCH64_TLBI_ASIDE1NXS, |
| 244 | ARM64_TLBI_ASIDE1OS = AARCH64_TLBI_ASIDE1OS, |
| 245 | ARM64_TLBI_ASIDE1OSNXS = AARCH64_TLBI_ASIDE1OSNXS, |
| 246 | ARM64_TLBI_IPAS2E1 = AARCH64_TLBI_IPAS2E1, |
| 247 | ARM64_TLBI_IPAS2E1IS = AARCH64_TLBI_IPAS2E1IS, |
| 248 | ARM64_TLBI_IPAS2E1ISNXS = AARCH64_TLBI_IPAS2E1ISNXS, |
| 249 | ARM64_TLBI_IPAS2E1NXS = AARCH64_TLBI_IPAS2E1NXS, |
| 250 | ARM64_TLBI_IPAS2E1OS = AARCH64_TLBI_IPAS2E1OS, |
| 251 | ARM64_TLBI_IPAS2E1OSNXS = AARCH64_TLBI_IPAS2E1OSNXS, |
| 252 | ARM64_TLBI_IPAS2LE1 = AARCH64_TLBI_IPAS2LE1, |
| 253 | ARM64_TLBI_IPAS2LE1IS = AARCH64_TLBI_IPAS2LE1IS, |
| 254 | ARM64_TLBI_IPAS2LE1ISNXS = AARCH64_TLBI_IPAS2LE1ISNXS, |
| 255 | ARM64_TLBI_IPAS2LE1NXS = AARCH64_TLBI_IPAS2LE1NXS, |
| 256 | ARM64_TLBI_IPAS2LE1OS = AARCH64_TLBI_IPAS2LE1OS, |
| 257 | ARM64_TLBI_IPAS2LE1OSNXS = AARCH64_TLBI_IPAS2LE1OSNXS, |
| 258 | ARM64_TLBI_PAALL = AARCH64_TLBI_PAALL, |
| 259 | ARM64_TLBI_PAALLNXS = AARCH64_TLBI_PAALLNXS, |
| 260 | ARM64_TLBI_PAALLOS = AARCH64_TLBI_PAALLOS, |
| 261 | ARM64_TLBI_PAALLOSNXS = AARCH64_TLBI_PAALLOSNXS, |
| 262 | ARM64_TLBI_RIPAS2E1 = AARCH64_TLBI_RIPAS2E1, |
| 263 | ARM64_TLBI_RIPAS2E1IS = AARCH64_TLBI_RIPAS2E1IS, |
| 264 | ARM64_TLBI_RIPAS2E1ISNXS = AARCH64_TLBI_RIPAS2E1ISNXS, |
| 265 | ARM64_TLBI_RIPAS2E1NXS = AARCH64_TLBI_RIPAS2E1NXS, |
| 266 | ARM64_TLBI_RIPAS2E1OS = AARCH64_TLBI_RIPAS2E1OS, |
| 267 | ARM64_TLBI_RIPAS2E1OSNXS = AARCH64_TLBI_RIPAS2E1OSNXS, |
| 268 | ARM64_TLBI_RIPAS2LE1 = AARCH64_TLBI_RIPAS2LE1, |
| 269 | ARM64_TLBI_RIPAS2LE1IS = AARCH64_TLBI_RIPAS2LE1IS, |
| 270 | ARM64_TLBI_RIPAS2LE1ISNXS = AARCH64_TLBI_RIPAS2LE1ISNXS, |
| 271 | ARM64_TLBI_RIPAS2LE1NXS = AARCH64_TLBI_RIPAS2LE1NXS, |
| 272 | ARM64_TLBI_RIPAS2LE1OS = AARCH64_TLBI_RIPAS2LE1OS, |
| 273 | ARM64_TLBI_RIPAS2LE1OSNXS = AARCH64_TLBI_RIPAS2LE1OSNXS, |
| 274 | ARM64_TLBI_RPALOS = AARCH64_TLBI_RPALOS, |
| 275 | ARM64_TLBI_RPALOSNXS = AARCH64_TLBI_RPALOSNXS, |
| 276 | ARM64_TLBI_RPAOS = AARCH64_TLBI_RPAOS, |
| 277 | ARM64_TLBI_RPAOSNXS = AARCH64_TLBI_RPAOSNXS, |
| 278 | ARM64_TLBI_RVAAE1 = AARCH64_TLBI_RVAAE1, |
| 279 | ARM64_TLBI_RVAAE1IS = AARCH64_TLBI_RVAAE1IS, |
| 280 | ARM64_TLBI_RVAAE1ISNXS = AARCH64_TLBI_RVAAE1ISNXS, |
| 281 | ARM64_TLBI_RVAAE1NXS = AARCH64_TLBI_RVAAE1NXS, |
| 282 | ARM64_TLBI_RVAAE1OS = AARCH64_TLBI_RVAAE1OS, |
| 283 | ARM64_TLBI_RVAAE1OSNXS = AARCH64_TLBI_RVAAE1OSNXS, |
| 284 | ARM64_TLBI_RVAALE1 = AARCH64_TLBI_RVAALE1, |
| 285 | ARM64_TLBI_RVAALE1IS = AARCH64_TLBI_RVAALE1IS, |
| 286 | ARM64_TLBI_RVAALE1ISNXS = AARCH64_TLBI_RVAALE1ISNXS, |
| 287 | ARM64_TLBI_RVAALE1NXS = AARCH64_TLBI_RVAALE1NXS, |
| 288 | ARM64_TLBI_RVAALE1OS = AARCH64_TLBI_RVAALE1OS, |
| 289 | ARM64_TLBI_RVAALE1OSNXS = AARCH64_TLBI_RVAALE1OSNXS, |
| 290 | ARM64_TLBI_RVAE1 = AARCH64_TLBI_RVAE1, |
| 291 | ARM64_TLBI_RVAE1IS = AARCH64_TLBI_RVAE1IS, |
| 292 | ARM64_TLBI_RVAE1ISNXS = AARCH64_TLBI_RVAE1ISNXS, |
| 293 | ARM64_TLBI_RVAE1NXS = AARCH64_TLBI_RVAE1NXS, |
| 294 | ARM64_TLBI_RVAE1OS = AARCH64_TLBI_RVAE1OS, |
| 295 | ARM64_TLBI_RVAE1OSNXS = AARCH64_TLBI_RVAE1OSNXS, |
| 296 | ARM64_TLBI_RVAE2 = AARCH64_TLBI_RVAE2, |
| 297 | ARM64_TLBI_RVAE2IS = AARCH64_TLBI_RVAE2IS, |
| 298 | ARM64_TLBI_RVAE2ISNXS = AARCH64_TLBI_RVAE2ISNXS, |
| 299 | ARM64_TLBI_RVAE2NXS = AARCH64_TLBI_RVAE2NXS, |
| 300 | ARM64_TLBI_RVAE2OS = AARCH64_TLBI_RVAE2OS, |
| 301 | ARM64_TLBI_RVAE2OSNXS = AARCH64_TLBI_RVAE2OSNXS, |
| 302 | ARM64_TLBI_RVAE3 = AARCH64_TLBI_RVAE3, |
| 303 | ARM64_TLBI_RVAE3IS = AARCH64_TLBI_RVAE3IS, |
| 304 | ARM64_TLBI_RVAE3ISNXS = AARCH64_TLBI_RVAE3ISNXS, |
| 305 | ARM64_TLBI_RVAE3NXS = AARCH64_TLBI_RVAE3NXS, |
| 306 | ARM64_TLBI_RVAE3OS = AARCH64_TLBI_RVAE3OS, |
| 307 | ARM64_TLBI_RVAE3OSNXS = AARCH64_TLBI_RVAE3OSNXS, |
| 308 | ARM64_TLBI_RVALE1 = AARCH64_TLBI_RVALE1, |
| 309 | ARM64_TLBI_RVALE1IS = AARCH64_TLBI_RVALE1IS, |
| 310 | ARM64_TLBI_RVALE1ISNXS = AARCH64_TLBI_RVALE1ISNXS, |
| 311 | ARM64_TLBI_RVALE1NXS = AARCH64_TLBI_RVALE1NXS, |
| 312 | ARM64_TLBI_RVALE1OS = AARCH64_TLBI_RVALE1OS, |
| 313 | ARM64_TLBI_RVALE1OSNXS = AARCH64_TLBI_RVALE1OSNXS, |
| 314 | ARM64_TLBI_RVALE2 = AARCH64_TLBI_RVALE2, |
| 315 | ARM64_TLBI_RVALE2IS = AARCH64_TLBI_RVALE2IS, |
| 316 | ARM64_TLBI_RVALE2ISNXS = AARCH64_TLBI_RVALE2ISNXS, |
| 317 | ARM64_TLBI_RVALE2NXS = AARCH64_TLBI_RVALE2NXS, |
| 318 | ARM64_TLBI_RVALE2OS = AARCH64_TLBI_RVALE2OS, |
| 319 | ARM64_TLBI_RVALE2OSNXS = AARCH64_TLBI_RVALE2OSNXS, |
| 320 | ARM64_TLBI_RVALE3 = AARCH64_TLBI_RVALE3, |
| 321 | ARM64_TLBI_RVALE3IS = AARCH64_TLBI_RVALE3IS, |
| 322 | ARM64_TLBI_RVALE3ISNXS = AARCH64_TLBI_RVALE3ISNXS, |
| 323 | ARM64_TLBI_RVALE3NXS = AARCH64_TLBI_RVALE3NXS, |
| 324 | ARM64_TLBI_RVALE3OS = AARCH64_TLBI_RVALE3OS, |
| 325 | ARM64_TLBI_RVALE3OSNXS = AARCH64_TLBI_RVALE3OSNXS, |
| 326 | ARM64_TLBI_VAAE1 = AARCH64_TLBI_VAAE1, |
| 327 | ARM64_TLBI_VAAE1IS = AARCH64_TLBI_VAAE1IS, |
| 328 | ARM64_TLBI_VAAE1ISNXS = AARCH64_TLBI_VAAE1ISNXS, |
| 329 | ARM64_TLBI_VAAE1NXS = AARCH64_TLBI_VAAE1NXS, |
| 330 | ARM64_TLBI_VAAE1OS = AARCH64_TLBI_VAAE1OS, |
| 331 | ARM64_TLBI_VAAE1OSNXS = AARCH64_TLBI_VAAE1OSNXS, |
| 332 | ARM64_TLBI_VAALE1 = AARCH64_TLBI_VAALE1, |
| 333 | ARM64_TLBI_VAALE1IS = AARCH64_TLBI_VAALE1IS, |
| 334 | ARM64_TLBI_VAALE1ISNXS = AARCH64_TLBI_VAALE1ISNXS, |
| 335 | ARM64_TLBI_VAALE1NXS = AARCH64_TLBI_VAALE1NXS, |
| 336 | ARM64_TLBI_VAALE1OS = AARCH64_TLBI_VAALE1OS, |
| 337 | ARM64_TLBI_VAALE1OSNXS = AARCH64_TLBI_VAALE1OSNXS, |
| 338 | ARM64_TLBI_VAE1 = AARCH64_TLBI_VAE1, |
| 339 | ARM64_TLBI_VAE1IS = AARCH64_TLBI_VAE1IS, |
| 340 | ARM64_TLBI_VAE1ISNXS = AARCH64_TLBI_VAE1ISNXS, |
| 341 | ARM64_TLBI_VAE1NXS = AARCH64_TLBI_VAE1NXS, |
| 342 | ARM64_TLBI_VAE1OS = AARCH64_TLBI_VAE1OS, |
| 343 | ARM64_TLBI_VAE1OSNXS = AARCH64_TLBI_VAE1OSNXS, |
| 344 | ARM64_TLBI_VAE2 = AARCH64_TLBI_VAE2, |
| 345 | ARM64_TLBI_VAE2IS = AARCH64_TLBI_VAE2IS, |
| 346 | ARM64_TLBI_VAE2ISNXS = AARCH64_TLBI_VAE2ISNXS, |
| 347 | ARM64_TLBI_VAE2NXS = AARCH64_TLBI_VAE2NXS, |
| 348 | ARM64_TLBI_VAE2OS = AARCH64_TLBI_VAE2OS, |
| 349 | ARM64_TLBI_VAE2OSNXS = AARCH64_TLBI_VAE2OSNXS, |
| 350 | ARM64_TLBI_VAE3 = AARCH64_TLBI_VAE3, |
| 351 | ARM64_TLBI_VAE3IS = AARCH64_TLBI_VAE3IS, |
| 352 | ARM64_TLBI_VAE3ISNXS = AARCH64_TLBI_VAE3ISNXS, |
| 353 | ARM64_TLBI_VAE3NXS = AARCH64_TLBI_VAE3NXS, |
| 354 | ARM64_TLBI_VAE3OS = AARCH64_TLBI_VAE3OS, |
| 355 | ARM64_TLBI_VAE3OSNXS = AARCH64_TLBI_VAE3OSNXS, |
| 356 | ARM64_TLBI_VALE1 = AARCH64_TLBI_VALE1, |
| 357 | ARM64_TLBI_VALE1IS = AARCH64_TLBI_VALE1IS, |
| 358 | ARM64_TLBI_VALE1ISNXS = AARCH64_TLBI_VALE1ISNXS, |
| 359 | ARM64_TLBI_VALE1NXS = AARCH64_TLBI_VALE1NXS, |
| 360 | ARM64_TLBI_VALE1OS = AARCH64_TLBI_VALE1OS, |
| 361 | ARM64_TLBI_VALE1OSNXS = AARCH64_TLBI_VALE1OSNXS, |
| 362 | ARM64_TLBI_VALE2 = AARCH64_TLBI_VALE2, |
| 363 | ARM64_TLBI_VALE2IS = AARCH64_TLBI_VALE2IS, |
| 364 | ARM64_TLBI_VALE2ISNXS = AARCH64_TLBI_VALE2ISNXS, |
| 365 | ARM64_TLBI_VALE2NXS = AARCH64_TLBI_VALE2NXS, |
| 366 | ARM64_TLBI_VALE2OS = AARCH64_TLBI_VALE2OS, |
| 367 | ARM64_TLBI_VALE2OSNXS = AARCH64_TLBI_VALE2OSNXS, |
| 368 | ARM64_TLBI_VALE3 = AARCH64_TLBI_VALE3, |
| 369 | ARM64_TLBI_VALE3IS = AARCH64_TLBI_VALE3IS, |
| 370 | ARM64_TLBI_VALE3ISNXS = AARCH64_TLBI_VALE3ISNXS, |
| 371 | ARM64_TLBI_VALE3NXS = AARCH64_TLBI_VALE3NXS, |
| 372 | ARM64_TLBI_VALE3OS = AARCH64_TLBI_VALE3OS, |
| 373 | ARM64_TLBI_VALE3OSNXS = AARCH64_TLBI_VALE3OSNXS, |
| 374 | ARM64_TLBI_VMALLE1 = AARCH64_TLBI_VMALLE1, |
| 375 | ARM64_TLBI_VMALLE1IS = AARCH64_TLBI_VMALLE1IS, |
| 376 | ARM64_TLBI_VMALLE1ISNXS = AARCH64_TLBI_VMALLE1ISNXS, |
| 377 | ARM64_TLBI_VMALLE1NXS = AARCH64_TLBI_VMALLE1NXS, |
| 378 | ARM64_TLBI_VMALLE1OS = AARCH64_TLBI_VMALLE1OS, |
| 379 | ARM64_TLBI_VMALLE1OSNXS = AARCH64_TLBI_VMALLE1OSNXS, |
| 380 | ARM64_TLBI_VMALLS12E1 = AARCH64_TLBI_VMALLS12E1, |
| 381 | ARM64_TLBI_VMALLS12E1IS = AARCH64_TLBI_VMALLS12E1IS, |
| 382 | ARM64_TLBI_VMALLS12E1ISNXS = AARCH64_TLBI_VMALLS12E1ISNXS, |
| 383 | ARM64_TLBI_VMALLS12E1NXS = AARCH64_TLBI_VMALLS12E1NXS, |
| 384 | ARM64_TLBI_VMALLS12E1OS = AARCH64_TLBI_VMALLS12E1OS, |
| 385 | ARM64_TLBI_VMALLS12E1OSNXS = AARCH64_TLBI_VMALLS12E1OSNXS, |
| 386 | ARM64_TLBI_VMALLWS2E1 = AARCH64_TLBI_VMALLWS2E1, |
| 387 | ARM64_TLBI_VMALLWS2E1IS = AARCH64_TLBI_VMALLWS2E1IS, |
| 388 | ARM64_TLBI_VMALLWS2E1ISNXS = AARCH64_TLBI_VMALLWS2E1ISNXS, |
| 389 | ARM64_TLBI_VMALLWS2E1NXS = AARCH64_TLBI_VMALLWS2E1NXS, |
| 390 | ARM64_TLBI_VMALLWS2E1OS = AARCH64_TLBI_VMALLWS2E1OS, |
| 391 | ARM64_TLBI_VMALLWS2E1OSNXS = AARCH64_TLBI_VMALLWS2E1OSNXS, |
| 392 | |
| 393 | ARM64_TLBI_ENDING = AARCH64_TLBI_ENDING, |
| 394 | } arm64_tlbi; |
| 395 | |
| 396 | typedef enum { |
| 397 | |
| 398 | ARM64_AT_S12E0R = AARCH64_AT_S12E0R, |
| 399 | ARM64_AT_S12E0W = AARCH64_AT_S12E0W, |
| 400 | ARM64_AT_S12E1R = AARCH64_AT_S12E1R, |
| 401 | ARM64_AT_S12E1W = AARCH64_AT_S12E1W, |
| 402 | ARM64_AT_S1E0R = AARCH64_AT_S1E0R, |
| 403 | ARM64_AT_S1E0W = AARCH64_AT_S1E0W, |
| 404 | ARM64_AT_S1E1A = AARCH64_AT_S1E1A, |
| 405 | ARM64_AT_S1E1R = AARCH64_AT_S1E1R, |
| 406 | ARM64_AT_S1E1RP = AARCH64_AT_S1E1RP, |
| 407 | ARM64_AT_S1E1W = AARCH64_AT_S1E1W, |
| 408 | ARM64_AT_S1E1WP = AARCH64_AT_S1E1WP, |
| 409 | ARM64_AT_S1E2A = AARCH64_AT_S1E2A, |
| 410 | ARM64_AT_S1E2R = AARCH64_AT_S1E2R, |
| 411 | ARM64_AT_S1E2W = AARCH64_AT_S1E2W, |
| 412 | ARM64_AT_S1E3A = AARCH64_AT_S1E3A, |
| 413 | ARM64_AT_S1E3R = AARCH64_AT_S1E3R, |
| 414 | ARM64_AT_S1E3W = AARCH64_AT_S1E3W, |
| 415 | |
| 416 | ARM64_AT_ENDING = AARCH64_AT_ENDING, |
| 417 | } arm64_at; |
| 418 | |
| 419 | typedef enum { |
| 420 | |
| 421 | ARM64_BTI_C = AARCH64_BTI_C, |
| 422 | ARM64_BTI_J = AARCH64_BTI_J, |
| 423 | ARM64_BTI_JC = AARCH64_BTI_JC, |
| 424 | |
| 425 | ARM64_BTI_ENDING = AARCH64_BTI_ENDING, |
| 426 | } arm64_bti; |
| 427 | |
| 428 | typedef enum { |
| 429 | |
| 430 | ARM64_DB_ISH = AARCH64_DB_ISH, |
| 431 | ARM64_DB_ISHLD = AARCH64_DB_ISHLD, |
| 432 | ARM64_DB_ISHST = AARCH64_DB_ISHST, |
| 433 | ARM64_DB_LD = AARCH64_DB_LD, |
| 434 | ARM64_DB_NSH = AARCH64_DB_NSH, |
| 435 | ARM64_DB_NSHLD = AARCH64_DB_NSHLD, |
| 436 | ARM64_DB_NSHST = AARCH64_DB_NSHST, |
| 437 | ARM64_DB_OSH = AARCH64_DB_OSH, |
| 438 | ARM64_DB_OSHLD = AARCH64_DB_OSHLD, |
| 439 | ARM64_DB_OSHST = AARCH64_DB_OSHST, |
| 440 | ARM64_DB_ST = AARCH64_DB_ST, |
| 441 | ARM64_DB_SY = AARCH64_DB_SY, |
| 442 | |
| 443 | ARM64_DB_ENDING = AARCH64_DB_ENDING, |
| 444 | } arm64_db; |
| 445 | |
| 446 | typedef enum { |
| 447 | |
| 448 | ARM64_DBNXS_ISHNXS = AARCH64_DBNXS_ISHNXS, |
| 449 | ARM64_DBNXS_NSHNXS = AARCH64_DBNXS_NSHNXS, |
| 450 | ARM64_DBNXS_OSHNXS = AARCH64_DBNXS_OSHNXS, |
| 451 | ARM64_DBNXS_SYNXS = AARCH64_DBNXS_SYNXS, |
| 452 | |
| 453 | ARM64_DBNXS_ENDING = AARCH64_DBNXS_ENDING, |
| 454 | } arm64_dbnxs; |
| 455 | |
| 456 | typedef enum { |
| 457 | |
| 458 | ARM64_DC_CGDSW = AARCH64_DC_CGDSW, |
| 459 | ARM64_DC_CGDVAC = AARCH64_DC_CGDVAC, |
| 460 | ARM64_DC_CGDVADP = AARCH64_DC_CGDVADP, |
| 461 | ARM64_DC_CGDVAP = AARCH64_DC_CGDVAP, |
| 462 | ARM64_DC_CGSW = AARCH64_DC_CGSW, |
| 463 | ARM64_DC_CGVAC = AARCH64_DC_CGVAC, |
| 464 | ARM64_DC_CGVADP = AARCH64_DC_CGVADP, |
| 465 | ARM64_DC_CGVAP = AARCH64_DC_CGVAP, |
| 466 | ARM64_DC_CIGDPAE = AARCH64_DC_CIGDPAE, |
| 467 | ARM64_DC_CIGDSW = AARCH64_DC_CIGDSW, |
| 468 | ARM64_DC_CIGDVAC = AARCH64_DC_CIGDVAC, |
| 469 | ARM64_DC_CIGSW = AARCH64_DC_CIGSW, |
| 470 | ARM64_DC_CIGVAC = AARCH64_DC_CIGVAC, |
| 471 | ARM64_DC_CIPAE = AARCH64_DC_CIPAE, |
| 472 | ARM64_DC_CISW = AARCH64_DC_CISW, |
| 473 | ARM64_DC_CIVAC = AARCH64_DC_CIVAC, |
| 474 | ARM64_DC_CSW = AARCH64_DC_CSW, |
| 475 | ARM64_DC_CVAC = AARCH64_DC_CVAC, |
| 476 | ARM64_DC_CVADP = AARCH64_DC_CVADP, |
| 477 | ARM64_DC_CVAP = AARCH64_DC_CVAP, |
| 478 | ARM64_DC_CVAU = AARCH64_DC_CVAU, |
| 479 | ARM64_DC_GVA = AARCH64_DC_GVA, |
| 480 | ARM64_DC_GZVA = AARCH64_DC_GZVA, |
| 481 | ARM64_DC_IGDSW = AARCH64_DC_IGDSW, |
| 482 | ARM64_DC_IGDVAC = AARCH64_DC_IGDVAC, |
| 483 | ARM64_DC_IGSW = AARCH64_DC_IGSW, |
| 484 | ARM64_DC_IGVAC = AARCH64_DC_IGVAC, |
| 485 | ARM64_DC_ISW = AARCH64_DC_ISW, |
| 486 | ARM64_DC_IVAC = AARCH64_DC_IVAC, |
| 487 | ARM64_DC_ZVA = AARCH64_DC_ZVA, |
| 488 | |
| 489 | ARM64_DC_ENDING = AARCH64_DC_ENDING, |
| 490 | } arm64_dc; |
| 491 | |
| 492 | typedef enum { |
| 493 | |
| 494 | ARM64_EXACTFPIMM_HALF = AARCH64_EXACTFPIMM_HALF, |
| 495 | ARM64_EXACTFPIMM_ONE = AARCH64_EXACTFPIMM_ONE, |
| 496 | ARM64_EXACTFPIMM_TWO = AARCH64_EXACTFPIMM_TWO, |
| 497 | ARM64_EXACTFPIMM_ZERO = AARCH64_EXACTFPIMM_ZERO, |
| 498 | |
| 499 | ARM64_EXACTFPIMM_INVALID = AARCH64_EXACTFPIMM_INVALID, |
| 500 | |
| 501 | ARM64_EXACTFPIMM_ENDING = AARCH64_EXACTFPIMM_ENDING, |
| 502 | } arm64_exactfpimm; |
| 503 | |
| 504 | typedef enum { |
| 505 | |
| 506 | ARM64_IC_IALLU = AARCH64_IC_IALLU, |
| 507 | ARM64_IC_IALLUIS = AARCH64_IC_IALLUIS, |
| 508 | ARM64_IC_IVAU = AARCH64_IC_IVAU, |
| 509 | |
| 510 | ARM64_IC_ENDING = AARCH64_IC_ENDING, |
| 511 | } arm64_ic; |
| 512 | |
| 513 | typedef enum { |
| 514 | |
| 515 | ARM64_ISB_SY = AARCH64_ISB_SY, |
| 516 | |
| 517 | ARM64_ISB_ENDING = AARCH64_ISB_ENDING, |
| 518 | } arm64_isb; |
| 519 | |
| 520 | typedef enum { |
| 521 | |
| 522 | ARM64_PRFM_PLDL1KEEP = AARCH64_PRFM_PLDL1KEEP, |
| 523 | ARM64_PRFM_PLDL1STRM = AARCH64_PRFM_PLDL1STRM, |
| 524 | ARM64_PRFM_PLDL2KEEP = AARCH64_PRFM_PLDL2KEEP, |
| 525 | ARM64_PRFM_PLDL2STRM = AARCH64_PRFM_PLDL2STRM, |
| 526 | ARM64_PRFM_PLDL3KEEP = AARCH64_PRFM_PLDL3KEEP, |
| 527 | ARM64_PRFM_PLDL3STRM = AARCH64_PRFM_PLDL3STRM, |
| 528 | ARM64_PRFM_PLDSLCKEEP = AARCH64_PRFM_PLDSLCKEEP, |
| 529 | ARM64_PRFM_PLDSLCSTRM = AARCH64_PRFM_PLDSLCSTRM, |
| 530 | ARM64_PRFM_PLIL1KEEP = AARCH64_PRFM_PLIL1KEEP, |
| 531 | ARM64_PRFM_PLIL1STRM = AARCH64_PRFM_PLIL1STRM, |
| 532 | ARM64_PRFM_PLIL2KEEP = AARCH64_PRFM_PLIL2KEEP, |
| 533 | ARM64_PRFM_PLIL2STRM = AARCH64_PRFM_PLIL2STRM, |
| 534 | ARM64_PRFM_PLIL3KEEP = AARCH64_PRFM_PLIL3KEEP, |
| 535 | ARM64_PRFM_PLIL3STRM = AARCH64_PRFM_PLIL3STRM, |
| 536 | ARM64_PRFM_PLISLCKEEP = AARCH64_PRFM_PLISLCKEEP, |
| 537 | ARM64_PRFM_PLISLCSTRM = AARCH64_PRFM_PLISLCSTRM, |
| 538 | ARM64_PRFM_PSTL1KEEP = AARCH64_PRFM_PSTL1KEEP, |
| 539 | ARM64_PRFM_PSTL1STRM = AARCH64_PRFM_PSTL1STRM, |
| 540 | ARM64_PRFM_PSTL2KEEP = AARCH64_PRFM_PSTL2KEEP, |
| 541 | ARM64_PRFM_PSTL2STRM = AARCH64_PRFM_PSTL2STRM, |
| 542 | ARM64_PRFM_PSTL3KEEP = AARCH64_PRFM_PSTL3KEEP, |
| 543 | ARM64_PRFM_PSTL3STRM = AARCH64_PRFM_PSTL3STRM, |
| 544 | ARM64_PRFM_PSTSLCKEEP = AARCH64_PRFM_PSTSLCKEEP, |
| 545 | ARM64_PRFM_PSTSLCSTRM = AARCH64_PRFM_PSTSLCSTRM, |
| 546 | |
| 547 | ARM64_PRFM_ENDING = AARCH64_PRFM_ENDING, |
| 548 | } arm64_prfm; |
| 549 | |
| 550 | typedef enum { |
| 551 | |
| 552 | ARM64_PSB_CSYNC = AARCH64_PSB_CSYNC, |
| 553 | |
| 554 | ARM64_PSB_ENDING = AARCH64_PSB_ENDING, |
| 555 | } arm64_psb; |
| 556 | |
| 557 | typedef enum { |
| 558 | |
| 559 | ARM64_PSTATEIMM0_1_ALLINT = AARCH64_PSTATEIMM0_1_ALLINT, |
| 560 | ARM64_PSTATEIMM0_1_PM = AARCH64_PSTATEIMM0_1_PM, |
| 561 | |
| 562 | ARM64_PSTATEIMM0_1_ENDING = AARCH64_PSTATEIMM0_1_ENDING, |
| 563 | } arm64_pstateimm0_1; |
| 564 | |
| 565 | typedef enum { |
| 566 | |
| 567 | ARM64_PSTATEIMM0_15_DAIFCLR = AARCH64_PSTATEIMM0_15_DAIFCLR, |
| 568 | ARM64_PSTATEIMM0_15_DAIFSET = AARCH64_PSTATEIMM0_15_DAIFSET, |
| 569 | ARM64_PSTATEIMM0_15_DIT = AARCH64_PSTATEIMM0_15_DIT, |
| 570 | ARM64_PSTATEIMM0_15_PAN = AARCH64_PSTATEIMM0_15_PAN, |
| 571 | ARM64_PSTATEIMM0_15_SPSEL = AARCH64_PSTATEIMM0_15_SPSEL, |
| 572 | ARM64_PSTATEIMM0_15_SSBS = AARCH64_PSTATEIMM0_15_SSBS, |
| 573 | ARM64_PSTATEIMM0_15_TCO = AARCH64_PSTATEIMM0_15_TCO, |
| 574 | ARM64_PSTATEIMM0_15_UAO = AARCH64_PSTATEIMM0_15_UAO, |
| 575 | |
| 576 | ARM64_PSTATEIMM0_15_ENDING = AARCH64_PSTATEIMM0_15_ENDING, |
| 577 | } arm64_pstateimm0_15; |
| 578 | |
| 579 | typedef enum { |
| 580 | |
| 581 | ARM64_RPRFM_PLDKEEP = AARCH64_RPRFM_PLDKEEP, |
| 582 | ARM64_RPRFM_PLDSTRM = AARCH64_RPRFM_PLDSTRM, |
| 583 | ARM64_RPRFM_PSTKEEP = AARCH64_RPRFM_PSTKEEP, |
| 584 | ARM64_RPRFM_PSTSTRM = AARCH64_RPRFM_PSTSTRM, |
| 585 | |
| 586 | ARM64_RPRFM_ENDING = AARCH64_RPRFM_ENDING, |
| 587 | } arm64_rprfm; |
| 588 | |
| 589 | typedef enum { |
| 590 | |
| 591 | ARM64_SVCR_SVCRSM = AARCH64_SVCR_SVCRSM, |
| 592 | ARM64_SVCR_SVCRSMZA = AARCH64_SVCR_SVCRSMZA, |
| 593 | ARM64_SVCR_SVCRZA = AARCH64_SVCR_SVCRZA, |
| 594 | |
| 595 | ARM64_SVCR_ENDING = AARCH64_SVCR_ENDING, |
| 596 | } arm64_svcr; |
| 597 | |
| 598 | typedef enum { |
| 599 | |
| 600 | ARM64_SVEPREDPAT_ALL = AARCH64_SVEPREDPAT_ALL, |
| 601 | ARM64_SVEPREDPAT_MUL3 = AARCH64_SVEPREDPAT_MUL3, |
| 602 | ARM64_SVEPREDPAT_MUL4 = AARCH64_SVEPREDPAT_MUL4, |
| 603 | ARM64_SVEPREDPAT_POW2 = AARCH64_SVEPREDPAT_POW2, |
| 604 | ARM64_SVEPREDPAT_VL1 = AARCH64_SVEPREDPAT_VL1, |
| 605 | ARM64_SVEPREDPAT_VL128 = AARCH64_SVEPREDPAT_VL128, |
| 606 | ARM64_SVEPREDPAT_VL16 = AARCH64_SVEPREDPAT_VL16, |
| 607 | ARM64_SVEPREDPAT_VL2 = AARCH64_SVEPREDPAT_VL2, |
| 608 | ARM64_SVEPREDPAT_VL256 = AARCH64_SVEPREDPAT_VL256, |
| 609 | ARM64_SVEPREDPAT_VL3 = AARCH64_SVEPREDPAT_VL3, |
| 610 | ARM64_SVEPREDPAT_VL32 = AARCH64_SVEPREDPAT_VL32, |
| 611 | ARM64_SVEPREDPAT_VL4 = AARCH64_SVEPREDPAT_VL4, |
| 612 | ARM64_SVEPREDPAT_VL5 = AARCH64_SVEPREDPAT_VL5, |
| 613 | ARM64_SVEPREDPAT_VL6 = AARCH64_SVEPREDPAT_VL6, |
| 614 | ARM64_SVEPREDPAT_VL64 = AARCH64_SVEPREDPAT_VL64, |
| 615 | ARM64_SVEPREDPAT_VL7 = AARCH64_SVEPREDPAT_VL7, |
| 616 | ARM64_SVEPREDPAT_VL8 = AARCH64_SVEPREDPAT_VL8, |
| 617 | |
| 618 | ARM64_SVEPREDPAT_ENDING = AARCH64_SVEPREDPAT_ENDING, |
| 619 | } arm64_svepredpat; |
| 620 | |
| 621 | typedef enum { |
| 622 | |
| 623 | ARM64_SVEPRFM_PLDL1KEEP = AARCH64_SVEPRFM_PLDL1KEEP, |
| 624 | ARM64_SVEPRFM_PLDL1STRM = AARCH64_SVEPRFM_PLDL1STRM, |
| 625 | ARM64_SVEPRFM_PLDL2KEEP = AARCH64_SVEPRFM_PLDL2KEEP, |
| 626 | ARM64_SVEPRFM_PLDL2STRM = AARCH64_SVEPRFM_PLDL2STRM, |
| 627 | ARM64_SVEPRFM_PLDL3KEEP = AARCH64_SVEPRFM_PLDL3KEEP, |
| 628 | ARM64_SVEPRFM_PLDL3STRM = AARCH64_SVEPRFM_PLDL3STRM, |
| 629 | ARM64_SVEPRFM_PSTL1KEEP = AARCH64_SVEPRFM_PSTL1KEEP, |
| 630 | ARM64_SVEPRFM_PSTL1STRM = AARCH64_SVEPRFM_PSTL1STRM, |
| 631 | ARM64_SVEPRFM_PSTL2KEEP = AARCH64_SVEPRFM_PSTL2KEEP, |
| 632 | ARM64_SVEPRFM_PSTL2STRM = AARCH64_SVEPRFM_PSTL2STRM, |
| 633 | ARM64_SVEPRFM_PSTL3KEEP = AARCH64_SVEPRFM_PSTL3KEEP, |
| 634 | ARM64_SVEPRFM_PSTL3STRM = AARCH64_SVEPRFM_PSTL3STRM, |
| 635 | |
| 636 | ARM64_SVEPRFM_ENDING = AARCH64_SVEPRFM_ENDING, |
| 637 | } arm64_sveprfm; |
| 638 | |
| 639 | typedef enum { |
| 640 | |
| 641 | ARM64_SVEVECLENSPECIFIER_VLX2 = AARCH64_SVEVECLENSPECIFIER_VLX2, |
| 642 | ARM64_SVEVECLENSPECIFIER_VLX4 = AARCH64_SVEVECLENSPECIFIER_VLX4, |
| 643 | |
| 644 | ARM64_SVEVECLENSPECIFIER_ENDING = AARCH64_SVEVECLENSPECIFIER_ENDING, |
| 645 | } arm64_sveveclenspecifier; |
| 646 | |
| 647 | typedef enum { |
| 648 | ARM64_SYSREG_INVALID = AARCH64_SYSREG_INVALID, |
| 649 | |
| 650 | ARM64_SYSREG_ACCDATA_EL1 = AARCH64_SYSREG_ACCDATA_EL1, |
| 651 | ARM64_SYSREG_ACTLR_EL1 = AARCH64_SYSREG_ACTLR_EL1, |
| 652 | ARM64_SYSREG_ACTLR_EL2 = AARCH64_SYSREG_ACTLR_EL2, |
| 653 | ARM64_SYSREG_ACTLR_EL3 = AARCH64_SYSREG_ACTLR_EL3, |
| 654 | ARM64_SYSREG_AFSR0_EL1 = AARCH64_SYSREG_AFSR0_EL1, |
| 655 | ARM64_SYSREG_AFSR0_EL12 = AARCH64_SYSREG_AFSR0_EL12, |
| 656 | ARM64_SYSREG_AFSR0_EL2 = AARCH64_SYSREG_AFSR0_EL2, |
| 657 | ARM64_SYSREG_AFSR0_EL3 = AARCH64_SYSREG_AFSR0_EL3, |
| 658 | ARM64_SYSREG_AFSR1_EL1 = AARCH64_SYSREG_AFSR1_EL1, |
| 659 | ARM64_SYSREG_AFSR1_EL12 = AARCH64_SYSREG_AFSR1_EL12, |
| 660 | ARM64_SYSREG_AFSR1_EL2 = AARCH64_SYSREG_AFSR1_EL2, |
| 661 | ARM64_SYSREG_AFSR1_EL3 = AARCH64_SYSREG_AFSR1_EL3, |
| 662 | ARM64_SYSREG_AIDR_EL1 = AARCH64_SYSREG_AIDR_EL1, |
| 663 | ARM64_SYSREG_ALLINT = AARCH64_SYSREG_ALLINT, |
| 664 | ARM64_SYSREG_AMAIR2_EL1 = AARCH64_SYSREG_AMAIR2_EL1, |
| 665 | ARM64_SYSREG_AMAIR2_EL12 = AARCH64_SYSREG_AMAIR2_EL12, |
| 666 | ARM64_SYSREG_AMAIR2_EL2 = AARCH64_SYSREG_AMAIR2_EL2, |
| 667 | ARM64_SYSREG_AMAIR2_EL3 = AARCH64_SYSREG_AMAIR2_EL3, |
| 668 | ARM64_SYSREG_AMAIR_EL1 = AARCH64_SYSREG_AMAIR_EL1, |
| 669 | ARM64_SYSREG_AMAIR_EL12 = AARCH64_SYSREG_AMAIR_EL12, |
| 670 | ARM64_SYSREG_AMAIR_EL2 = AARCH64_SYSREG_AMAIR_EL2, |
| 671 | ARM64_SYSREG_AMAIR_EL3 = AARCH64_SYSREG_AMAIR_EL3, |
| 672 | ARM64_SYSREG_AMCFGR_EL0 = AARCH64_SYSREG_AMCFGR_EL0, |
| 673 | ARM64_SYSREG_AMCG1IDR_EL0 = AARCH64_SYSREG_AMCG1IDR_EL0, |
| 674 | ARM64_SYSREG_AMCGCR_EL0 = AARCH64_SYSREG_AMCGCR_EL0, |
| 675 | ARM64_SYSREG_AMCNTENCLR0_EL0 = AARCH64_SYSREG_AMCNTENCLR0_EL0, |
| 676 | ARM64_SYSREG_AMCNTENCLR1_EL0 = AARCH64_SYSREG_AMCNTENCLR1_EL0, |
| 677 | ARM64_SYSREG_AMCNTENSET0_EL0 = AARCH64_SYSREG_AMCNTENSET0_EL0, |
| 678 | ARM64_SYSREG_AMCNTENSET1_EL0 = AARCH64_SYSREG_AMCNTENSET1_EL0, |
| 679 | ARM64_SYSREG_AMCR_EL0 = AARCH64_SYSREG_AMCR_EL0, |
| 680 | ARM64_SYSREG_AMEVCNTR00_EL0 = AARCH64_SYSREG_AMEVCNTR00_EL0, |
| 681 | ARM64_SYSREG_AMEVCNTR01_EL0 = AARCH64_SYSREG_AMEVCNTR01_EL0, |
| 682 | ARM64_SYSREG_AMEVCNTR02_EL0 = AARCH64_SYSREG_AMEVCNTR02_EL0, |
| 683 | ARM64_SYSREG_AMEVCNTR03_EL0 = AARCH64_SYSREG_AMEVCNTR03_EL0, |
| 684 | ARM64_SYSREG_AMEVCNTR10_EL0 = AARCH64_SYSREG_AMEVCNTR10_EL0, |
| 685 | ARM64_SYSREG_AMEVCNTR110_EL0 = AARCH64_SYSREG_AMEVCNTR110_EL0, |
| 686 | ARM64_SYSREG_AMEVCNTR111_EL0 = AARCH64_SYSREG_AMEVCNTR111_EL0, |
| 687 | ARM64_SYSREG_AMEVCNTR112_EL0 = AARCH64_SYSREG_AMEVCNTR112_EL0, |
| 688 | ARM64_SYSREG_AMEVCNTR113_EL0 = AARCH64_SYSREG_AMEVCNTR113_EL0, |
| 689 | ARM64_SYSREG_AMEVCNTR114_EL0 = AARCH64_SYSREG_AMEVCNTR114_EL0, |
| 690 | ARM64_SYSREG_AMEVCNTR115_EL0 = AARCH64_SYSREG_AMEVCNTR115_EL0, |
| 691 | ARM64_SYSREG_AMEVCNTR11_EL0 = AARCH64_SYSREG_AMEVCNTR11_EL0, |
| 692 | ARM64_SYSREG_AMEVCNTR12_EL0 = AARCH64_SYSREG_AMEVCNTR12_EL0, |
| 693 | ARM64_SYSREG_AMEVCNTR13_EL0 = AARCH64_SYSREG_AMEVCNTR13_EL0, |
| 694 | ARM64_SYSREG_AMEVCNTR14_EL0 = AARCH64_SYSREG_AMEVCNTR14_EL0, |
| 695 | ARM64_SYSREG_AMEVCNTR15_EL0 = AARCH64_SYSREG_AMEVCNTR15_EL0, |
| 696 | ARM64_SYSREG_AMEVCNTR16_EL0 = AARCH64_SYSREG_AMEVCNTR16_EL0, |
| 697 | ARM64_SYSREG_AMEVCNTR17_EL0 = AARCH64_SYSREG_AMEVCNTR17_EL0, |
| 698 | ARM64_SYSREG_AMEVCNTR18_EL0 = AARCH64_SYSREG_AMEVCNTR18_EL0, |
| 699 | ARM64_SYSREG_AMEVCNTR19_EL0 = AARCH64_SYSREG_AMEVCNTR19_EL0, |
| 700 | ARM64_SYSREG_AMEVCNTVOFF00_EL2 = AARCH64_SYSREG_AMEVCNTVOFF00_EL2, |
| 701 | ARM64_SYSREG_AMEVCNTVOFF010_EL2 = AARCH64_SYSREG_AMEVCNTVOFF010_EL2, |
| 702 | ARM64_SYSREG_AMEVCNTVOFF011_EL2 = AARCH64_SYSREG_AMEVCNTVOFF011_EL2, |
| 703 | ARM64_SYSREG_AMEVCNTVOFF012_EL2 = AARCH64_SYSREG_AMEVCNTVOFF012_EL2, |
| 704 | ARM64_SYSREG_AMEVCNTVOFF013_EL2 = AARCH64_SYSREG_AMEVCNTVOFF013_EL2, |
| 705 | ARM64_SYSREG_AMEVCNTVOFF014_EL2 = AARCH64_SYSREG_AMEVCNTVOFF014_EL2, |
| 706 | ARM64_SYSREG_AMEVCNTVOFF015_EL2 = AARCH64_SYSREG_AMEVCNTVOFF015_EL2, |
| 707 | ARM64_SYSREG_AMEVCNTVOFF01_EL2 = AARCH64_SYSREG_AMEVCNTVOFF01_EL2, |
| 708 | ARM64_SYSREG_AMEVCNTVOFF02_EL2 = AARCH64_SYSREG_AMEVCNTVOFF02_EL2, |
| 709 | ARM64_SYSREG_AMEVCNTVOFF03_EL2 = AARCH64_SYSREG_AMEVCNTVOFF03_EL2, |
| 710 | ARM64_SYSREG_AMEVCNTVOFF04_EL2 = AARCH64_SYSREG_AMEVCNTVOFF04_EL2, |
| 711 | ARM64_SYSREG_AMEVCNTVOFF05_EL2 = AARCH64_SYSREG_AMEVCNTVOFF05_EL2, |
| 712 | ARM64_SYSREG_AMEVCNTVOFF06_EL2 = AARCH64_SYSREG_AMEVCNTVOFF06_EL2, |
| 713 | ARM64_SYSREG_AMEVCNTVOFF07_EL2 = AARCH64_SYSREG_AMEVCNTVOFF07_EL2, |
| 714 | ARM64_SYSREG_AMEVCNTVOFF08_EL2 = AARCH64_SYSREG_AMEVCNTVOFF08_EL2, |
| 715 | ARM64_SYSREG_AMEVCNTVOFF09_EL2 = AARCH64_SYSREG_AMEVCNTVOFF09_EL2, |
| 716 | ARM64_SYSREG_AMEVCNTVOFF10_EL2 = AARCH64_SYSREG_AMEVCNTVOFF10_EL2, |
| 717 | ARM64_SYSREG_AMEVCNTVOFF110_EL2 = AARCH64_SYSREG_AMEVCNTVOFF110_EL2, |
| 718 | ARM64_SYSREG_AMEVCNTVOFF111_EL2 = AARCH64_SYSREG_AMEVCNTVOFF111_EL2, |
| 719 | ARM64_SYSREG_AMEVCNTVOFF112_EL2 = AARCH64_SYSREG_AMEVCNTVOFF112_EL2, |
| 720 | ARM64_SYSREG_AMEVCNTVOFF113_EL2 = AARCH64_SYSREG_AMEVCNTVOFF113_EL2, |
| 721 | ARM64_SYSREG_AMEVCNTVOFF114_EL2 = AARCH64_SYSREG_AMEVCNTVOFF114_EL2, |
| 722 | ARM64_SYSREG_AMEVCNTVOFF115_EL2 = AARCH64_SYSREG_AMEVCNTVOFF115_EL2, |
| 723 | ARM64_SYSREG_AMEVCNTVOFF11_EL2 = AARCH64_SYSREG_AMEVCNTVOFF11_EL2, |
| 724 | ARM64_SYSREG_AMEVCNTVOFF12_EL2 = AARCH64_SYSREG_AMEVCNTVOFF12_EL2, |
| 725 | ARM64_SYSREG_AMEVCNTVOFF13_EL2 = AARCH64_SYSREG_AMEVCNTVOFF13_EL2, |
| 726 | ARM64_SYSREG_AMEVCNTVOFF14_EL2 = AARCH64_SYSREG_AMEVCNTVOFF14_EL2, |
| 727 | ARM64_SYSREG_AMEVCNTVOFF15_EL2 = AARCH64_SYSREG_AMEVCNTVOFF15_EL2, |
| 728 | ARM64_SYSREG_AMEVCNTVOFF16_EL2 = AARCH64_SYSREG_AMEVCNTVOFF16_EL2, |
| 729 | ARM64_SYSREG_AMEVCNTVOFF17_EL2 = AARCH64_SYSREG_AMEVCNTVOFF17_EL2, |
| 730 | ARM64_SYSREG_AMEVCNTVOFF18_EL2 = AARCH64_SYSREG_AMEVCNTVOFF18_EL2, |
| 731 | ARM64_SYSREG_AMEVCNTVOFF19_EL2 = AARCH64_SYSREG_AMEVCNTVOFF19_EL2, |
| 732 | ARM64_SYSREG_AMEVTYPER00_EL0 = AARCH64_SYSREG_AMEVTYPER00_EL0, |
| 733 | ARM64_SYSREG_AMEVTYPER01_EL0 = AARCH64_SYSREG_AMEVTYPER01_EL0, |
| 734 | ARM64_SYSREG_AMEVTYPER02_EL0 = AARCH64_SYSREG_AMEVTYPER02_EL0, |
| 735 | ARM64_SYSREG_AMEVTYPER03_EL0 = AARCH64_SYSREG_AMEVTYPER03_EL0, |
| 736 | ARM64_SYSREG_AMEVTYPER10_EL0 = AARCH64_SYSREG_AMEVTYPER10_EL0, |
| 737 | ARM64_SYSREG_AMEVTYPER110_EL0 = AARCH64_SYSREG_AMEVTYPER110_EL0, |
| 738 | ARM64_SYSREG_AMEVTYPER111_EL0 = AARCH64_SYSREG_AMEVTYPER111_EL0, |
| 739 | ARM64_SYSREG_AMEVTYPER112_EL0 = AARCH64_SYSREG_AMEVTYPER112_EL0, |
| 740 | ARM64_SYSREG_AMEVTYPER113_EL0 = AARCH64_SYSREG_AMEVTYPER113_EL0, |
| 741 | ARM64_SYSREG_AMEVTYPER114_EL0 = AARCH64_SYSREG_AMEVTYPER114_EL0, |
| 742 | ARM64_SYSREG_AMEVTYPER115_EL0 = AARCH64_SYSREG_AMEVTYPER115_EL0, |
| 743 | ARM64_SYSREG_AMEVTYPER11_EL0 = AARCH64_SYSREG_AMEVTYPER11_EL0, |
| 744 | ARM64_SYSREG_AMEVTYPER12_EL0 = AARCH64_SYSREG_AMEVTYPER12_EL0, |
| 745 | ARM64_SYSREG_AMEVTYPER13_EL0 = AARCH64_SYSREG_AMEVTYPER13_EL0, |
| 746 | ARM64_SYSREG_AMEVTYPER14_EL0 = AARCH64_SYSREG_AMEVTYPER14_EL0, |
| 747 | ARM64_SYSREG_AMEVTYPER15_EL0 = AARCH64_SYSREG_AMEVTYPER15_EL0, |
| 748 | ARM64_SYSREG_AMEVTYPER16_EL0 = AARCH64_SYSREG_AMEVTYPER16_EL0, |
| 749 | ARM64_SYSREG_AMEVTYPER17_EL0 = AARCH64_SYSREG_AMEVTYPER17_EL0, |
| 750 | ARM64_SYSREG_AMEVTYPER18_EL0 = AARCH64_SYSREG_AMEVTYPER18_EL0, |
| 751 | ARM64_SYSREG_AMEVTYPER19_EL0 = AARCH64_SYSREG_AMEVTYPER19_EL0, |
| 752 | ARM64_SYSREG_AMUSERENR_EL0 = AARCH64_SYSREG_AMUSERENR_EL0, |
| 753 | ARM64_SYSREG_APDAKEYHI_EL1 = AARCH64_SYSREG_APDAKEYHI_EL1, |
| 754 | ARM64_SYSREG_APDAKEYLO_EL1 = AARCH64_SYSREG_APDAKEYLO_EL1, |
| 755 | ARM64_SYSREG_APDBKEYHI_EL1 = AARCH64_SYSREG_APDBKEYHI_EL1, |
| 756 | ARM64_SYSREG_APDBKEYLO_EL1 = AARCH64_SYSREG_APDBKEYLO_EL1, |
| 757 | ARM64_SYSREG_APGAKEYHI_EL1 = AARCH64_SYSREG_APGAKEYHI_EL1, |
| 758 | ARM64_SYSREG_APGAKEYLO_EL1 = AARCH64_SYSREG_APGAKEYLO_EL1, |
| 759 | ARM64_SYSREG_APIAKEYHI_EL1 = AARCH64_SYSREG_APIAKEYHI_EL1, |
| 760 | ARM64_SYSREG_APIAKEYLO_EL1 = AARCH64_SYSREG_APIAKEYLO_EL1, |
| 761 | ARM64_SYSREG_APIBKEYHI_EL1 = AARCH64_SYSREG_APIBKEYHI_EL1, |
| 762 | ARM64_SYSREG_APIBKEYLO_EL1 = AARCH64_SYSREG_APIBKEYLO_EL1, |
| 763 | ARM64_SYSREG_BRBCR_EL1 = AARCH64_SYSREG_BRBCR_EL1, |
| 764 | ARM64_SYSREG_BRBCR_EL12 = AARCH64_SYSREG_BRBCR_EL12, |
| 765 | ARM64_SYSREG_BRBCR_EL2 = AARCH64_SYSREG_BRBCR_EL2, |
| 766 | ARM64_SYSREG_BRBFCR_EL1 = AARCH64_SYSREG_BRBFCR_EL1, |
| 767 | ARM64_SYSREG_BRBIDR0_EL1 = AARCH64_SYSREG_BRBIDR0_EL1, |
| 768 | ARM64_SYSREG_BRBINF0_EL1 = AARCH64_SYSREG_BRBINF0_EL1, |
| 769 | ARM64_SYSREG_BRBINF10_EL1 = AARCH64_SYSREG_BRBINF10_EL1, |
| 770 | ARM64_SYSREG_BRBINF11_EL1 = AARCH64_SYSREG_BRBINF11_EL1, |
| 771 | ARM64_SYSREG_BRBINF12_EL1 = AARCH64_SYSREG_BRBINF12_EL1, |
| 772 | ARM64_SYSREG_BRBINF13_EL1 = AARCH64_SYSREG_BRBINF13_EL1, |
| 773 | ARM64_SYSREG_BRBINF14_EL1 = AARCH64_SYSREG_BRBINF14_EL1, |
| 774 | ARM64_SYSREG_BRBINF15_EL1 = AARCH64_SYSREG_BRBINF15_EL1, |
| 775 | ARM64_SYSREG_BRBINF16_EL1 = AARCH64_SYSREG_BRBINF16_EL1, |
| 776 | ARM64_SYSREG_BRBINF17_EL1 = AARCH64_SYSREG_BRBINF17_EL1, |
| 777 | ARM64_SYSREG_BRBINF18_EL1 = AARCH64_SYSREG_BRBINF18_EL1, |
| 778 | ARM64_SYSREG_BRBINF19_EL1 = AARCH64_SYSREG_BRBINF19_EL1, |
| 779 | ARM64_SYSREG_BRBINF1_EL1 = AARCH64_SYSREG_BRBINF1_EL1, |
| 780 | ARM64_SYSREG_BRBINF20_EL1 = AARCH64_SYSREG_BRBINF20_EL1, |
| 781 | ARM64_SYSREG_BRBINF21_EL1 = AARCH64_SYSREG_BRBINF21_EL1, |
| 782 | ARM64_SYSREG_BRBINF22_EL1 = AARCH64_SYSREG_BRBINF22_EL1, |
| 783 | ARM64_SYSREG_BRBINF23_EL1 = AARCH64_SYSREG_BRBINF23_EL1, |
| 784 | ARM64_SYSREG_BRBINF24_EL1 = AARCH64_SYSREG_BRBINF24_EL1, |
| 785 | ARM64_SYSREG_BRBINF25_EL1 = AARCH64_SYSREG_BRBINF25_EL1, |
| 786 | ARM64_SYSREG_BRBINF26_EL1 = AARCH64_SYSREG_BRBINF26_EL1, |
| 787 | ARM64_SYSREG_BRBINF27_EL1 = AARCH64_SYSREG_BRBINF27_EL1, |
| 788 | ARM64_SYSREG_BRBINF28_EL1 = AARCH64_SYSREG_BRBINF28_EL1, |
| 789 | ARM64_SYSREG_BRBINF29_EL1 = AARCH64_SYSREG_BRBINF29_EL1, |
| 790 | ARM64_SYSREG_BRBINF2_EL1 = AARCH64_SYSREG_BRBINF2_EL1, |
| 791 | ARM64_SYSREG_BRBINF30_EL1 = AARCH64_SYSREG_BRBINF30_EL1, |
| 792 | ARM64_SYSREG_BRBINF31_EL1 = AARCH64_SYSREG_BRBINF31_EL1, |
| 793 | ARM64_SYSREG_BRBINF3_EL1 = AARCH64_SYSREG_BRBINF3_EL1, |
| 794 | ARM64_SYSREG_BRBINF4_EL1 = AARCH64_SYSREG_BRBINF4_EL1, |
| 795 | ARM64_SYSREG_BRBINF5_EL1 = AARCH64_SYSREG_BRBINF5_EL1, |
| 796 | ARM64_SYSREG_BRBINF6_EL1 = AARCH64_SYSREG_BRBINF6_EL1, |
| 797 | ARM64_SYSREG_BRBINF7_EL1 = AARCH64_SYSREG_BRBINF7_EL1, |
| 798 | ARM64_SYSREG_BRBINF8_EL1 = AARCH64_SYSREG_BRBINF8_EL1, |
| 799 | ARM64_SYSREG_BRBINF9_EL1 = AARCH64_SYSREG_BRBINF9_EL1, |
| 800 | ARM64_SYSREG_BRBINFINJ_EL1 = AARCH64_SYSREG_BRBINFINJ_EL1, |
| 801 | ARM64_SYSREG_BRBSRC0_EL1 = AARCH64_SYSREG_BRBSRC0_EL1, |
| 802 | ARM64_SYSREG_BRBSRC10_EL1 = AARCH64_SYSREG_BRBSRC10_EL1, |
| 803 | ARM64_SYSREG_BRBSRC11_EL1 = AARCH64_SYSREG_BRBSRC11_EL1, |
| 804 | ARM64_SYSREG_BRBSRC12_EL1 = AARCH64_SYSREG_BRBSRC12_EL1, |
| 805 | ARM64_SYSREG_BRBSRC13_EL1 = AARCH64_SYSREG_BRBSRC13_EL1, |
| 806 | ARM64_SYSREG_BRBSRC14_EL1 = AARCH64_SYSREG_BRBSRC14_EL1, |
| 807 | ARM64_SYSREG_BRBSRC15_EL1 = AARCH64_SYSREG_BRBSRC15_EL1, |
| 808 | ARM64_SYSREG_BRBSRC16_EL1 = AARCH64_SYSREG_BRBSRC16_EL1, |
| 809 | ARM64_SYSREG_BRBSRC17_EL1 = AARCH64_SYSREG_BRBSRC17_EL1, |
| 810 | ARM64_SYSREG_BRBSRC18_EL1 = AARCH64_SYSREG_BRBSRC18_EL1, |
| 811 | ARM64_SYSREG_BRBSRC19_EL1 = AARCH64_SYSREG_BRBSRC19_EL1, |
| 812 | ARM64_SYSREG_BRBSRC1_EL1 = AARCH64_SYSREG_BRBSRC1_EL1, |
| 813 | ARM64_SYSREG_BRBSRC20_EL1 = AARCH64_SYSREG_BRBSRC20_EL1, |
| 814 | ARM64_SYSREG_BRBSRC21_EL1 = AARCH64_SYSREG_BRBSRC21_EL1, |
| 815 | ARM64_SYSREG_BRBSRC22_EL1 = AARCH64_SYSREG_BRBSRC22_EL1, |
| 816 | ARM64_SYSREG_BRBSRC23_EL1 = AARCH64_SYSREG_BRBSRC23_EL1, |
| 817 | ARM64_SYSREG_BRBSRC24_EL1 = AARCH64_SYSREG_BRBSRC24_EL1, |
| 818 | ARM64_SYSREG_BRBSRC25_EL1 = AARCH64_SYSREG_BRBSRC25_EL1, |
| 819 | ARM64_SYSREG_BRBSRC26_EL1 = AARCH64_SYSREG_BRBSRC26_EL1, |
| 820 | ARM64_SYSREG_BRBSRC27_EL1 = AARCH64_SYSREG_BRBSRC27_EL1, |
| 821 | ARM64_SYSREG_BRBSRC28_EL1 = AARCH64_SYSREG_BRBSRC28_EL1, |
| 822 | ARM64_SYSREG_BRBSRC29_EL1 = AARCH64_SYSREG_BRBSRC29_EL1, |
| 823 | ARM64_SYSREG_BRBSRC2_EL1 = AARCH64_SYSREG_BRBSRC2_EL1, |
| 824 | ARM64_SYSREG_BRBSRC30_EL1 = AARCH64_SYSREG_BRBSRC30_EL1, |
| 825 | ARM64_SYSREG_BRBSRC31_EL1 = AARCH64_SYSREG_BRBSRC31_EL1, |
| 826 | ARM64_SYSREG_BRBSRC3_EL1 = AARCH64_SYSREG_BRBSRC3_EL1, |
| 827 | ARM64_SYSREG_BRBSRC4_EL1 = AARCH64_SYSREG_BRBSRC4_EL1, |
| 828 | ARM64_SYSREG_BRBSRC5_EL1 = AARCH64_SYSREG_BRBSRC5_EL1, |
| 829 | ARM64_SYSREG_BRBSRC6_EL1 = AARCH64_SYSREG_BRBSRC6_EL1, |
| 830 | ARM64_SYSREG_BRBSRC7_EL1 = AARCH64_SYSREG_BRBSRC7_EL1, |
| 831 | ARM64_SYSREG_BRBSRC8_EL1 = AARCH64_SYSREG_BRBSRC8_EL1, |
| 832 | ARM64_SYSREG_BRBSRC9_EL1 = AARCH64_SYSREG_BRBSRC9_EL1, |
| 833 | ARM64_SYSREG_BRBSRCINJ_EL1 = AARCH64_SYSREG_BRBSRCINJ_EL1, |
| 834 | ARM64_SYSREG_BRBTGT0_EL1 = AARCH64_SYSREG_BRBTGT0_EL1, |
| 835 | ARM64_SYSREG_BRBTGT10_EL1 = AARCH64_SYSREG_BRBTGT10_EL1, |
| 836 | ARM64_SYSREG_BRBTGT11_EL1 = AARCH64_SYSREG_BRBTGT11_EL1, |
| 837 | ARM64_SYSREG_BRBTGT12_EL1 = AARCH64_SYSREG_BRBTGT12_EL1, |
| 838 | ARM64_SYSREG_BRBTGT13_EL1 = AARCH64_SYSREG_BRBTGT13_EL1, |
| 839 | ARM64_SYSREG_BRBTGT14_EL1 = AARCH64_SYSREG_BRBTGT14_EL1, |
| 840 | ARM64_SYSREG_BRBTGT15_EL1 = AARCH64_SYSREG_BRBTGT15_EL1, |
| 841 | ARM64_SYSREG_BRBTGT16_EL1 = AARCH64_SYSREG_BRBTGT16_EL1, |
| 842 | ARM64_SYSREG_BRBTGT17_EL1 = AARCH64_SYSREG_BRBTGT17_EL1, |
| 843 | ARM64_SYSREG_BRBTGT18_EL1 = AARCH64_SYSREG_BRBTGT18_EL1, |
| 844 | ARM64_SYSREG_BRBTGT19_EL1 = AARCH64_SYSREG_BRBTGT19_EL1, |
| 845 | ARM64_SYSREG_BRBTGT1_EL1 = AARCH64_SYSREG_BRBTGT1_EL1, |
| 846 | ARM64_SYSREG_BRBTGT20_EL1 = AARCH64_SYSREG_BRBTGT20_EL1, |
| 847 | ARM64_SYSREG_BRBTGT21_EL1 = AARCH64_SYSREG_BRBTGT21_EL1, |
| 848 | ARM64_SYSREG_BRBTGT22_EL1 = AARCH64_SYSREG_BRBTGT22_EL1, |
| 849 | ARM64_SYSREG_BRBTGT23_EL1 = AARCH64_SYSREG_BRBTGT23_EL1, |
| 850 | ARM64_SYSREG_BRBTGT24_EL1 = AARCH64_SYSREG_BRBTGT24_EL1, |
| 851 | ARM64_SYSREG_BRBTGT25_EL1 = AARCH64_SYSREG_BRBTGT25_EL1, |
| 852 | ARM64_SYSREG_BRBTGT26_EL1 = AARCH64_SYSREG_BRBTGT26_EL1, |
| 853 | ARM64_SYSREG_BRBTGT27_EL1 = AARCH64_SYSREG_BRBTGT27_EL1, |
| 854 | ARM64_SYSREG_BRBTGT28_EL1 = AARCH64_SYSREG_BRBTGT28_EL1, |
| 855 | ARM64_SYSREG_BRBTGT29_EL1 = AARCH64_SYSREG_BRBTGT29_EL1, |
| 856 | ARM64_SYSREG_BRBTGT2_EL1 = AARCH64_SYSREG_BRBTGT2_EL1, |
| 857 | ARM64_SYSREG_BRBTGT30_EL1 = AARCH64_SYSREG_BRBTGT30_EL1, |
| 858 | ARM64_SYSREG_BRBTGT31_EL1 = AARCH64_SYSREG_BRBTGT31_EL1, |
| 859 | ARM64_SYSREG_BRBTGT3_EL1 = AARCH64_SYSREG_BRBTGT3_EL1, |
| 860 | ARM64_SYSREG_BRBTGT4_EL1 = AARCH64_SYSREG_BRBTGT4_EL1, |
| 861 | ARM64_SYSREG_BRBTGT5_EL1 = AARCH64_SYSREG_BRBTGT5_EL1, |
| 862 | ARM64_SYSREG_BRBTGT6_EL1 = AARCH64_SYSREG_BRBTGT6_EL1, |
| 863 | ARM64_SYSREG_BRBTGT7_EL1 = AARCH64_SYSREG_BRBTGT7_EL1, |
| 864 | ARM64_SYSREG_BRBTGT8_EL1 = AARCH64_SYSREG_BRBTGT8_EL1, |
| 865 | ARM64_SYSREG_BRBTGT9_EL1 = AARCH64_SYSREG_BRBTGT9_EL1, |
| 866 | ARM64_SYSREG_BRBTGTINJ_EL1 = AARCH64_SYSREG_BRBTGTINJ_EL1, |
| 867 | ARM64_SYSREG_BRBTS_EL1 = AARCH64_SYSREG_BRBTS_EL1, |
| 868 | ARM64_SYSREG_CCSIDR2_EL1 = AARCH64_SYSREG_CCSIDR2_EL1, |
| 869 | ARM64_SYSREG_CCSIDR_EL1 = AARCH64_SYSREG_CCSIDR_EL1, |
| 870 | ARM64_SYSREG_CLIDR_EL1 = AARCH64_SYSREG_CLIDR_EL1, |
| 871 | ARM64_SYSREG_CNTFRQ_EL0 = AARCH64_SYSREG_CNTFRQ_EL0, |
| 872 | ARM64_SYSREG_CNTHCTL_EL2 = AARCH64_SYSREG_CNTHCTL_EL2, |
| 873 | ARM64_SYSREG_CNTHPS_CTL_EL2 = AARCH64_SYSREG_CNTHPS_CTL_EL2, |
| 874 | ARM64_SYSREG_CNTHPS_CVAL_EL2 = AARCH64_SYSREG_CNTHPS_CVAL_EL2, |
| 875 | ARM64_SYSREG_CNTHPS_TVAL_EL2 = AARCH64_SYSREG_CNTHPS_TVAL_EL2, |
| 876 | ARM64_SYSREG_CNTHP_CTL_EL2 = AARCH64_SYSREG_CNTHP_CTL_EL2, |
| 877 | ARM64_SYSREG_CNTHP_CVAL_EL2 = AARCH64_SYSREG_CNTHP_CVAL_EL2, |
| 878 | ARM64_SYSREG_CNTHP_TVAL_EL2 = AARCH64_SYSREG_CNTHP_TVAL_EL2, |
| 879 | ARM64_SYSREG_CNTHVS_CTL_EL2 = AARCH64_SYSREG_CNTHVS_CTL_EL2, |
| 880 | ARM64_SYSREG_CNTHVS_CVAL_EL2 = AARCH64_SYSREG_CNTHVS_CVAL_EL2, |
| 881 | ARM64_SYSREG_CNTHVS_TVAL_EL2 = AARCH64_SYSREG_CNTHVS_TVAL_EL2, |
| 882 | ARM64_SYSREG_CNTHV_CTL_EL2 = AARCH64_SYSREG_CNTHV_CTL_EL2, |
| 883 | ARM64_SYSREG_CNTHV_CVAL_EL2 = AARCH64_SYSREG_CNTHV_CVAL_EL2, |
| 884 | ARM64_SYSREG_CNTHV_TVAL_EL2 = AARCH64_SYSREG_CNTHV_TVAL_EL2, |
| 885 | ARM64_SYSREG_CNTISCALE_EL2 = AARCH64_SYSREG_CNTISCALE_EL2, |
| 886 | ARM64_SYSREG_CNTKCTL_EL1 = AARCH64_SYSREG_CNTKCTL_EL1, |
| 887 | ARM64_SYSREG_CNTKCTL_EL12 = AARCH64_SYSREG_CNTKCTL_EL12, |
| 888 | ARM64_SYSREG_CNTPCTSS_EL0 = AARCH64_SYSREG_CNTPCTSS_EL0, |
| 889 | ARM64_SYSREG_CNTPCT_EL0 = AARCH64_SYSREG_CNTPCT_EL0, |
| 890 | ARM64_SYSREG_CNTPOFF_EL2 = AARCH64_SYSREG_CNTPOFF_EL2, |
| 891 | ARM64_SYSREG_CNTPS_CTL_EL1 = AARCH64_SYSREG_CNTPS_CTL_EL1, |
| 892 | ARM64_SYSREG_CNTPS_CVAL_EL1 = AARCH64_SYSREG_CNTPS_CVAL_EL1, |
| 893 | ARM64_SYSREG_CNTPS_TVAL_EL1 = AARCH64_SYSREG_CNTPS_TVAL_EL1, |
| 894 | ARM64_SYSREG_CNTP_CTL_EL0 = AARCH64_SYSREG_CNTP_CTL_EL0, |
| 895 | ARM64_SYSREG_CNTP_CTL_EL02 = AARCH64_SYSREG_CNTP_CTL_EL02, |
| 896 | ARM64_SYSREG_CNTP_CVAL_EL0 = AARCH64_SYSREG_CNTP_CVAL_EL0, |
| 897 | ARM64_SYSREG_CNTP_CVAL_EL02 = AARCH64_SYSREG_CNTP_CVAL_EL02, |
| 898 | ARM64_SYSREG_CNTP_TVAL_EL0 = AARCH64_SYSREG_CNTP_TVAL_EL0, |
| 899 | ARM64_SYSREG_CNTP_TVAL_EL02 = AARCH64_SYSREG_CNTP_TVAL_EL02, |
| 900 | ARM64_SYSREG_CNTSCALE_EL2 = AARCH64_SYSREG_CNTSCALE_EL2, |
| 901 | ARM64_SYSREG_CNTVCTSS_EL0 = AARCH64_SYSREG_CNTVCTSS_EL0, |
| 902 | ARM64_SYSREG_CNTVCT_EL0 = AARCH64_SYSREG_CNTVCT_EL0, |
| 903 | ARM64_SYSREG_CNTVFRQ_EL2 = AARCH64_SYSREG_CNTVFRQ_EL2, |
| 904 | ARM64_SYSREG_CNTVOFF_EL2 = AARCH64_SYSREG_CNTVOFF_EL2, |
| 905 | ARM64_SYSREG_CNTV_CTL_EL0 = AARCH64_SYSREG_CNTV_CTL_EL0, |
| 906 | ARM64_SYSREG_CNTV_CTL_EL02 = AARCH64_SYSREG_CNTV_CTL_EL02, |
| 907 | ARM64_SYSREG_CNTV_CVAL_EL0 = AARCH64_SYSREG_CNTV_CVAL_EL0, |
| 908 | ARM64_SYSREG_CNTV_CVAL_EL02 = AARCH64_SYSREG_CNTV_CVAL_EL02, |
| 909 | ARM64_SYSREG_CNTV_TVAL_EL0 = AARCH64_SYSREG_CNTV_TVAL_EL0, |
| 910 | ARM64_SYSREG_CNTV_TVAL_EL02 = AARCH64_SYSREG_CNTV_TVAL_EL02, |
| 911 | ARM64_SYSREG_CONTEXTIDR_EL1 = AARCH64_SYSREG_CONTEXTIDR_EL1, |
| 912 | ARM64_SYSREG_CONTEXTIDR_EL12 = AARCH64_SYSREG_CONTEXTIDR_EL12, |
| 913 | ARM64_SYSREG_CONTEXTIDR_EL2 = AARCH64_SYSREG_CONTEXTIDR_EL2, |
| 914 | ARM64_SYSREG_CPACR_EL1 = AARCH64_SYSREG_CPACR_EL1, |
| 915 | ARM64_SYSREG_CPACR_EL12 = AARCH64_SYSREG_CPACR_EL12, |
| 916 | ARM64_SYSREG_CPM_IOACC_CTL_EL3 = AARCH64_SYSREG_CPM_IOACC_CTL_EL3, |
| 917 | ARM64_SYSREG_CPTR_EL2 = AARCH64_SYSREG_CPTR_EL2, |
| 918 | ARM64_SYSREG_CPTR_EL3 = AARCH64_SYSREG_CPTR_EL3, |
| 919 | ARM64_SYSREG_CSSELR_EL1 = AARCH64_SYSREG_CSSELR_EL1, |
| 920 | ARM64_SYSREG_CTR_EL0 = AARCH64_SYSREG_CTR_EL0, |
| 921 | ARM64_SYSREG_CURRENTEL = AARCH64_SYSREG_CURRENTEL, |
| 922 | ARM64_SYSREG_DACR32_EL2 = AARCH64_SYSREG_DACR32_EL2, |
| 923 | ARM64_SYSREG_DAIF = AARCH64_SYSREG_DAIF, |
| 924 | ARM64_SYSREG_DBGAUTHSTATUS_EL1 = AARCH64_SYSREG_DBGAUTHSTATUS_EL1, |
| 925 | ARM64_SYSREG_DBGBCR0_EL1 = AARCH64_SYSREG_DBGBCR0_EL1, |
| 926 | ARM64_SYSREG_DBGBCR10_EL1 = AARCH64_SYSREG_DBGBCR10_EL1, |
| 927 | ARM64_SYSREG_DBGBCR11_EL1 = AARCH64_SYSREG_DBGBCR11_EL1, |
| 928 | ARM64_SYSREG_DBGBCR12_EL1 = AARCH64_SYSREG_DBGBCR12_EL1, |
| 929 | ARM64_SYSREG_DBGBCR13_EL1 = AARCH64_SYSREG_DBGBCR13_EL1, |
| 930 | ARM64_SYSREG_DBGBCR14_EL1 = AARCH64_SYSREG_DBGBCR14_EL1, |
| 931 | ARM64_SYSREG_DBGBCR15_EL1 = AARCH64_SYSREG_DBGBCR15_EL1, |
| 932 | ARM64_SYSREG_DBGBCR1_EL1 = AARCH64_SYSREG_DBGBCR1_EL1, |
| 933 | ARM64_SYSREG_DBGBCR2_EL1 = AARCH64_SYSREG_DBGBCR2_EL1, |
| 934 | ARM64_SYSREG_DBGBCR3_EL1 = AARCH64_SYSREG_DBGBCR3_EL1, |
| 935 | ARM64_SYSREG_DBGBCR4_EL1 = AARCH64_SYSREG_DBGBCR4_EL1, |
| 936 | ARM64_SYSREG_DBGBCR5_EL1 = AARCH64_SYSREG_DBGBCR5_EL1, |
| 937 | ARM64_SYSREG_DBGBCR6_EL1 = AARCH64_SYSREG_DBGBCR6_EL1, |
| 938 | ARM64_SYSREG_DBGBCR7_EL1 = AARCH64_SYSREG_DBGBCR7_EL1, |
| 939 | ARM64_SYSREG_DBGBCR8_EL1 = AARCH64_SYSREG_DBGBCR8_EL1, |
| 940 | ARM64_SYSREG_DBGBCR9_EL1 = AARCH64_SYSREG_DBGBCR9_EL1, |
| 941 | ARM64_SYSREG_DBGBVR0_EL1 = AARCH64_SYSREG_DBGBVR0_EL1, |
| 942 | ARM64_SYSREG_DBGBVR10_EL1 = AARCH64_SYSREG_DBGBVR10_EL1, |
| 943 | ARM64_SYSREG_DBGBVR11_EL1 = AARCH64_SYSREG_DBGBVR11_EL1, |
| 944 | ARM64_SYSREG_DBGBVR12_EL1 = AARCH64_SYSREG_DBGBVR12_EL1, |
| 945 | ARM64_SYSREG_DBGBVR13_EL1 = AARCH64_SYSREG_DBGBVR13_EL1, |
| 946 | ARM64_SYSREG_DBGBVR14_EL1 = AARCH64_SYSREG_DBGBVR14_EL1, |
| 947 | ARM64_SYSREG_DBGBVR15_EL1 = AARCH64_SYSREG_DBGBVR15_EL1, |
| 948 | ARM64_SYSREG_DBGBVR1_EL1 = AARCH64_SYSREG_DBGBVR1_EL1, |
| 949 | ARM64_SYSREG_DBGBVR2_EL1 = AARCH64_SYSREG_DBGBVR2_EL1, |
| 950 | ARM64_SYSREG_DBGBVR3_EL1 = AARCH64_SYSREG_DBGBVR3_EL1, |
| 951 | ARM64_SYSREG_DBGBVR4_EL1 = AARCH64_SYSREG_DBGBVR4_EL1, |
| 952 | ARM64_SYSREG_DBGBVR5_EL1 = AARCH64_SYSREG_DBGBVR5_EL1, |
| 953 | ARM64_SYSREG_DBGBVR6_EL1 = AARCH64_SYSREG_DBGBVR6_EL1, |
| 954 | ARM64_SYSREG_DBGBVR7_EL1 = AARCH64_SYSREG_DBGBVR7_EL1, |
| 955 | ARM64_SYSREG_DBGBVR8_EL1 = AARCH64_SYSREG_DBGBVR8_EL1, |
| 956 | ARM64_SYSREG_DBGBVR9_EL1 = AARCH64_SYSREG_DBGBVR9_EL1, |
| 957 | ARM64_SYSREG_DBGCLAIMCLR_EL1 = AARCH64_SYSREG_DBGCLAIMCLR_EL1, |
| 958 | ARM64_SYSREG_DBGCLAIMSET_EL1 = AARCH64_SYSREG_DBGCLAIMSET_EL1, |
| 959 | ARM64_SYSREG_DBGDTRRX_EL0 = AARCH64_SYSREG_DBGDTRRX_EL0, |
| 960 | ARM64_SYSREG_DBGDTRTX_EL0 = AARCH64_SYSREG_DBGDTRTX_EL0, |
| 961 | ARM64_SYSREG_DBGDTR_EL0 = AARCH64_SYSREG_DBGDTR_EL0, |
| 962 | ARM64_SYSREG_DBGPRCR_EL1 = AARCH64_SYSREG_DBGPRCR_EL1, |
| 963 | ARM64_SYSREG_DBGVCR32_EL2 = AARCH64_SYSREG_DBGVCR32_EL2, |
| 964 | ARM64_SYSREG_DBGWCR0_EL1 = AARCH64_SYSREG_DBGWCR0_EL1, |
| 965 | ARM64_SYSREG_DBGWCR10_EL1 = AARCH64_SYSREG_DBGWCR10_EL1, |
| 966 | ARM64_SYSREG_DBGWCR11_EL1 = AARCH64_SYSREG_DBGWCR11_EL1, |
| 967 | ARM64_SYSREG_DBGWCR12_EL1 = AARCH64_SYSREG_DBGWCR12_EL1, |
| 968 | ARM64_SYSREG_DBGWCR13_EL1 = AARCH64_SYSREG_DBGWCR13_EL1, |
| 969 | ARM64_SYSREG_DBGWCR14_EL1 = AARCH64_SYSREG_DBGWCR14_EL1, |
| 970 | ARM64_SYSREG_DBGWCR15_EL1 = AARCH64_SYSREG_DBGWCR15_EL1, |
| 971 | ARM64_SYSREG_DBGWCR1_EL1 = AARCH64_SYSREG_DBGWCR1_EL1, |
| 972 | ARM64_SYSREG_DBGWCR2_EL1 = AARCH64_SYSREG_DBGWCR2_EL1, |
| 973 | ARM64_SYSREG_DBGWCR3_EL1 = AARCH64_SYSREG_DBGWCR3_EL1, |
| 974 | ARM64_SYSREG_DBGWCR4_EL1 = AARCH64_SYSREG_DBGWCR4_EL1, |
| 975 | ARM64_SYSREG_DBGWCR5_EL1 = AARCH64_SYSREG_DBGWCR5_EL1, |
| 976 | ARM64_SYSREG_DBGWCR6_EL1 = AARCH64_SYSREG_DBGWCR6_EL1, |
| 977 | ARM64_SYSREG_DBGWCR7_EL1 = AARCH64_SYSREG_DBGWCR7_EL1, |
| 978 | ARM64_SYSREG_DBGWCR8_EL1 = AARCH64_SYSREG_DBGWCR8_EL1, |
| 979 | ARM64_SYSREG_DBGWCR9_EL1 = AARCH64_SYSREG_DBGWCR9_EL1, |
| 980 | ARM64_SYSREG_DBGWVR0_EL1 = AARCH64_SYSREG_DBGWVR0_EL1, |
| 981 | ARM64_SYSREG_DBGWVR10_EL1 = AARCH64_SYSREG_DBGWVR10_EL1, |
| 982 | ARM64_SYSREG_DBGWVR11_EL1 = AARCH64_SYSREG_DBGWVR11_EL1, |
| 983 | ARM64_SYSREG_DBGWVR12_EL1 = AARCH64_SYSREG_DBGWVR12_EL1, |
| 984 | ARM64_SYSREG_DBGWVR13_EL1 = AARCH64_SYSREG_DBGWVR13_EL1, |
| 985 | ARM64_SYSREG_DBGWVR14_EL1 = AARCH64_SYSREG_DBGWVR14_EL1, |
| 986 | ARM64_SYSREG_DBGWVR15_EL1 = AARCH64_SYSREG_DBGWVR15_EL1, |
| 987 | ARM64_SYSREG_DBGWVR1_EL1 = AARCH64_SYSREG_DBGWVR1_EL1, |
| 988 | ARM64_SYSREG_DBGWVR2_EL1 = AARCH64_SYSREG_DBGWVR2_EL1, |
| 989 | ARM64_SYSREG_DBGWVR3_EL1 = AARCH64_SYSREG_DBGWVR3_EL1, |
| 990 | ARM64_SYSREG_DBGWVR4_EL1 = AARCH64_SYSREG_DBGWVR4_EL1, |
| 991 | ARM64_SYSREG_DBGWVR5_EL1 = AARCH64_SYSREG_DBGWVR5_EL1, |
| 992 | ARM64_SYSREG_DBGWVR6_EL1 = AARCH64_SYSREG_DBGWVR6_EL1, |
| 993 | ARM64_SYSREG_DBGWVR7_EL1 = AARCH64_SYSREG_DBGWVR7_EL1, |
| 994 | ARM64_SYSREG_DBGWVR8_EL1 = AARCH64_SYSREG_DBGWVR8_EL1, |
| 995 | ARM64_SYSREG_DBGWVR9_EL1 = AARCH64_SYSREG_DBGWVR9_EL1, |
| 996 | ARM64_SYSREG_DCZID_EL0 = AARCH64_SYSREG_DCZID_EL0, |
| 997 | ARM64_SYSREG_DISR_EL1 = AARCH64_SYSREG_DISR_EL1, |
| 998 | ARM64_SYSREG_DIT = AARCH64_SYSREG_DIT, |
| 999 | ARM64_SYSREG_DLR_EL0 = AARCH64_SYSREG_DLR_EL0, |
| 1000 | ARM64_SYSREG_DSPSR_EL0 = AARCH64_SYSREG_DSPSR_EL0, |
| 1001 | ARM64_SYSREG_ELR_EL1 = AARCH64_SYSREG_ELR_EL1, |
| 1002 | ARM64_SYSREG_ELR_EL12 = AARCH64_SYSREG_ELR_EL12, |
| 1003 | ARM64_SYSREG_ELR_EL2 = AARCH64_SYSREG_ELR_EL2, |
| 1004 | ARM64_SYSREG_ELR_EL3 = AARCH64_SYSREG_ELR_EL3, |
| 1005 | ARM64_SYSREG_ERRIDR_EL1 = AARCH64_SYSREG_ERRIDR_EL1, |
| 1006 | ARM64_SYSREG_ERRSELR_EL1 = AARCH64_SYSREG_ERRSELR_EL1, |
| 1007 | ARM64_SYSREG_ERXADDR_EL1 = AARCH64_SYSREG_ERXADDR_EL1, |
| 1008 | ARM64_SYSREG_ERXCTLR_EL1 = AARCH64_SYSREG_ERXCTLR_EL1, |
| 1009 | ARM64_SYSREG_ERXFR_EL1 = AARCH64_SYSREG_ERXFR_EL1, |
| 1010 | ARM64_SYSREG_ERXGSR_EL1 = AARCH64_SYSREG_ERXGSR_EL1, |
| 1011 | ARM64_SYSREG_ERXMISC0_EL1 = AARCH64_SYSREG_ERXMISC0_EL1, |
| 1012 | ARM64_SYSREG_ERXMISC1_EL1 = AARCH64_SYSREG_ERXMISC1_EL1, |
| 1013 | ARM64_SYSREG_ERXMISC2_EL1 = AARCH64_SYSREG_ERXMISC2_EL1, |
| 1014 | ARM64_SYSREG_ERXMISC3_EL1 = AARCH64_SYSREG_ERXMISC3_EL1, |
| 1015 | ARM64_SYSREG_ERXPFGCDN_EL1 = AARCH64_SYSREG_ERXPFGCDN_EL1, |
| 1016 | ARM64_SYSREG_ERXPFGCTL_EL1 = AARCH64_SYSREG_ERXPFGCTL_EL1, |
| 1017 | ARM64_SYSREG_ERXPFGF_EL1 = AARCH64_SYSREG_ERXPFGF_EL1, |
| 1018 | ARM64_SYSREG_ERXSTATUS_EL1 = AARCH64_SYSREG_ERXSTATUS_EL1, |
| 1019 | ARM64_SYSREG_ESR_EL1 = AARCH64_SYSREG_ESR_EL1, |
| 1020 | ARM64_SYSREG_ESR_EL12 = AARCH64_SYSREG_ESR_EL12, |
| 1021 | ARM64_SYSREG_ESR_EL2 = AARCH64_SYSREG_ESR_EL2, |
| 1022 | ARM64_SYSREG_ESR_EL3 = AARCH64_SYSREG_ESR_EL3, |
| 1023 | ARM64_SYSREG_FAR_EL1 = AARCH64_SYSREG_FAR_EL1, |
| 1024 | ARM64_SYSREG_FAR_EL12 = AARCH64_SYSREG_FAR_EL12, |
| 1025 | ARM64_SYSREG_FAR_EL2 = AARCH64_SYSREG_FAR_EL2, |
| 1026 | ARM64_SYSREG_FAR_EL3 = AARCH64_SYSREG_FAR_EL3, |
| 1027 | ARM64_SYSREG_FGWTE3_EL3 = AARCH64_SYSREG_FGWTE3_EL3, |
| 1028 | ARM64_SYSREG_FPCR = AARCH64_SYSREG_FPCR, |
| 1029 | ARM64_SYSREG_FPEXC32_EL2 = AARCH64_SYSREG_FPEXC32_EL2, |
| 1030 | ARM64_SYSREG_FPMR = AARCH64_SYSREG_FPMR, |
| 1031 | ARM64_SYSREG_FPSR = AARCH64_SYSREG_FPSR, |
| 1032 | ARM64_SYSREG_GCR_EL1 = AARCH64_SYSREG_GCR_EL1, |
| 1033 | ARM64_SYSREG_GCSCRE0_EL1 = AARCH64_SYSREG_GCSCRE0_EL1, |
| 1034 | ARM64_SYSREG_GCSCR_EL1 = AARCH64_SYSREG_GCSCR_EL1, |
| 1035 | ARM64_SYSREG_GCSCR_EL12 = AARCH64_SYSREG_GCSCR_EL12, |
| 1036 | ARM64_SYSREG_GCSCR_EL2 = AARCH64_SYSREG_GCSCR_EL2, |
| 1037 | ARM64_SYSREG_GCSCR_EL3 = AARCH64_SYSREG_GCSCR_EL3, |
| 1038 | ARM64_SYSREG_GCSPR_EL0 = AARCH64_SYSREG_GCSPR_EL0, |
| 1039 | ARM64_SYSREG_GCSPR_EL1 = AARCH64_SYSREG_GCSPR_EL1, |
| 1040 | ARM64_SYSREG_GCSPR_EL12 = AARCH64_SYSREG_GCSPR_EL12, |
| 1041 | ARM64_SYSREG_GCSPR_EL2 = AARCH64_SYSREG_GCSPR_EL2, |
| 1042 | ARM64_SYSREG_GCSPR_EL3 = AARCH64_SYSREG_GCSPR_EL3, |
| 1043 | ARM64_SYSREG_GMID_EL1 = AARCH64_SYSREG_GMID_EL1, |
| 1044 | ARM64_SYSREG_GPCCR_EL3 = AARCH64_SYSREG_GPCCR_EL3, |
| 1045 | ARM64_SYSREG_GPTBR_EL3 = AARCH64_SYSREG_GPTBR_EL3, |
| 1046 | ARM64_SYSREG_HACDBSBR_EL2 = AARCH64_SYSREG_HACDBSBR_EL2, |
| 1047 | ARM64_SYSREG_HACDBSCONS_EL2 = AARCH64_SYSREG_HACDBSCONS_EL2, |
| 1048 | ARM64_SYSREG_HACR_EL2 = AARCH64_SYSREG_HACR_EL2, |
| 1049 | ARM64_SYSREG_HAFGRTR_EL2 = AARCH64_SYSREG_HAFGRTR_EL2, |
| 1050 | ARM64_SYSREG_HCRX_EL2 = AARCH64_SYSREG_HCRX_EL2, |
| 1051 | ARM64_SYSREG_HCR_EL2 = AARCH64_SYSREG_HCR_EL2, |
| 1052 | ARM64_SYSREG_HDBSSBR_EL2 = AARCH64_SYSREG_HDBSSBR_EL2, |
| 1053 | ARM64_SYSREG_HDBSSPROD_EL2 = AARCH64_SYSREG_HDBSSPROD_EL2, |
| 1054 | ARM64_SYSREG_HDFGRTR2_EL2 = AARCH64_SYSREG_HDFGRTR2_EL2, |
| 1055 | ARM64_SYSREG_HDFGRTR_EL2 = AARCH64_SYSREG_HDFGRTR_EL2, |
| 1056 | ARM64_SYSREG_HDFGWTR2_EL2 = AARCH64_SYSREG_HDFGWTR2_EL2, |
| 1057 | ARM64_SYSREG_HDFGWTR_EL2 = AARCH64_SYSREG_HDFGWTR_EL2, |
| 1058 | ARM64_SYSREG_HFGITR2_EL2 = AARCH64_SYSREG_HFGITR2_EL2, |
| 1059 | ARM64_SYSREG_HFGITR_EL2 = AARCH64_SYSREG_HFGITR_EL2, |
| 1060 | ARM64_SYSREG_HFGRTR2_EL2 = AARCH64_SYSREG_HFGRTR2_EL2, |
| 1061 | ARM64_SYSREG_HFGRTR_EL2 = AARCH64_SYSREG_HFGRTR_EL2, |
| 1062 | ARM64_SYSREG_HFGWTR2_EL2 = AARCH64_SYSREG_HFGWTR2_EL2, |
| 1063 | ARM64_SYSREG_HFGWTR_EL2 = AARCH64_SYSREG_HFGWTR_EL2, |
| 1064 | ARM64_SYSREG_HPFAR_EL2 = AARCH64_SYSREG_HPFAR_EL2, |
| 1065 | ARM64_SYSREG_HSTR_EL2 = AARCH64_SYSREG_HSTR_EL2, |
| 1066 | ARM64_SYSREG_ICC_AP0R0_EL1 = AARCH64_SYSREG_ICC_AP0R0_EL1, |
| 1067 | ARM64_SYSREG_ICC_AP0R1_EL1 = AARCH64_SYSREG_ICC_AP0R1_EL1, |
| 1068 | ARM64_SYSREG_ICC_AP0R2_EL1 = AARCH64_SYSREG_ICC_AP0R2_EL1, |
| 1069 | ARM64_SYSREG_ICC_AP0R3_EL1 = AARCH64_SYSREG_ICC_AP0R3_EL1, |
| 1070 | ARM64_SYSREG_ICC_AP1R0_EL1 = AARCH64_SYSREG_ICC_AP1R0_EL1, |
| 1071 | ARM64_SYSREG_ICC_AP1R1_EL1 = AARCH64_SYSREG_ICC_AP1R1_EL1, |
| 1072 | ARM64_SYSREG_ICC_AP1R2_EL1 = AARCH64_SYSREG_ICC_AP1R2_EL1, |
| 1073 | ARM64_SYSREG_ICC_AP1R3_EL1 = AARCH64_SYSREG_ICC_AP1R3_EL1, |
| 1074 | ARM64_SYSREG_ICC_ASGI1R_EL1 = AARCH64_SYSREG_ICC_ASGI1R_EL1, |
| 1075 | ARM64_SYSREG_ICC_BPR0_EL1 = AARCH64_SYSREG_ICC_BPR0_EL1, |
| 1076 | ARM64_SYSREG_ICC_BPR1_EL1 = AARCH64_SYSREG_ICC_BPR1_EL1, |
| 1077 | ARM64_SYSREG_ICC_CTLR_EL1 = AARCH64_SYSREG_ICC_CTLR_EL1, |
| 1078 | ARM64_SYSREG_ICC_CTLR_EL3 = AARCH64_SYSREG_ICC_CTLR_EL3, |
| 1079 | ARM64_SYSREG_ICC_DIR_EL1 = AARCH64_SYSREG_ICC_DIR_EL1, |
| 1080 | ARM64_SYSREG_ICC_EOIR0_EL1 = AARCH64_SYSREG_ICC_EOIR0_EL1, |
| 1081 | ARM64_SYSREG_ICC_EOIR1_EL1 = AARCH64_SYSREG_ICC_EOIR1_EL1, |
| 1082 | ARM64_SYSREG_ICC_HPPIR0_EL1 = AARCH64_SYSREG_ICC_HPPIR0_EL1, |
| 1083 | ARM64_SYSREG_ICC_HPPIR1_EL1 = AARCH64_SYSREG_ICC_HPPIR1_EL1, |
| 1084 | ARM64_SYSREG_ICC_IAR0_EL1 = AARCH64_SYSREG_ICC_IAR0_EL1, |
| 1085 | ARM64_SYSREG_ICC_IAR1_EL1 = AARCH64_SYSREG_ICC_IAR1_EL1, |
| 1086 | ARM64_SYSREG_ICC_IGRPEN0_EL1 = AARCH64_SYSREG_ICC_IGRPEN0_EL1, |
| 1087 | ARM64_SYSREG_ICC_IGRPEN1_EL1 = AARCH64_SYSREG_ICC_IGRPEN1_EL1, |
| 1088 | ARM64_SYSREG_ICC_IGRPEN1_EL3 = AARCH64_SYSREG_ICC_IGRPEN1_EL3, |
| 1089 | ARM64_SYSREG_ICC_NMIAR1_EL1 = AARCH64_SYSREG_ICC_NMIAR1_EL1, |
| 1090 | ARM64_SYSREG_ICC_PMR_EL1 = AARCH64_SYSREG_ICC_PMR_EL1, |
| 1091 | ARM64_SYSREG_ICC_RPR_EL1 = AARCH64_SYSREG_ICC_RPR_EL1, |
| 1092 | ARM64_SYSREG_ICC_SGI0R_EL1 = AARCH64_SYSREG_ICC_SGI0R_EL1, |
| 1093 | ARM64_SYSREG_ICC_SGI1R_EL1 = AARCH64_SYSREG_ICC_SGI1R_EL1, |
| 1094 | ARM64_SYSREG_ICC_SRE_EL1 = AARCH64_SYSREG_ICC_SRE_EL1, |
| 1095 | ARM64_SYSREG_ICC_SRE_EL2 = AARCH64_SYSREG_ICC_SRE_EL2, |
| 1096 | ARM64_SYSREG_ICC_SRE_EL3 = AARCH64_SYSREG_ICC_SRE_EL3, |
| 1097 | ARM64_SYSREG_ICH_AP0R0_EL2 = AARCH64_SYSREG_ICH_AP0R0_EL2, |
| 1098 | ARM64_SYSREG_ICH_AP0R1_EL2 = AARCH64_SYSREG_ICH_AP0R1_EL2, |
| 1099 | ARM64_SYSREG_ICH_AP0R2_EL2 = AARCH64_SYSREG_ICH_AP0R2_EL2, |
| 1100 | ARM64_SYSREG_ICH_AP0R3_EL2 = AARCH64_SYSREG_ICH_AP0R3_EL2, |
| 1101 | ARM64_SYSREG_ICH_AP1R0_EL2 = AARCH64_SYSREG_ICH_AP1R0_EL2, |
| 1102 | ARM64_SYSREG_ICH_AP1R1_EL2 = AARCH64_SYSREG_ICH_AP1R1_EL2, |
| 1103 | ARM64_SYSREG_ICH_AP1R2_EL2 = AARCH64_SYSREG_ICH_AP1R2_EL2, |
| 1104 | ARM64_SYSREG_ICH_AP1R3_EL2 = AARCH64_SYSREG_ICH_AP1R3_EL2, |
| 1105 | ARM64_SYSREG_ICH_EISR_EL2 = AARCH64_SYSREG_ICH_EISR_EL2, |
| 1106 | ARM64_SYSREG_ICH_ELRSR_EL2 = AARCH64_SYSREG_ICH_ELRSR_EL2, |
| 1107 | ARM64_SYSREG_ICH_HCR_EL2 = AARCH64_SYSREG_ICH_HCR_EL2, |
| 1108 | ARM64_SYSREG_ICH_LR0_EL2 = AARCH64_SYSREG_ICH_LR0_EL2, |
| 1109 | ARM64_SYSREG_ICH_LR10_EL2 = AARCH64_SYSREG_ICH_LR10_EL2, |
| 1110 | ARM64_SYSREG_ICH_LR11_EL2 = AARCH64_SYSREG_ICH_LR11_EL2, |
| 1111 | ARM64_SYSREG_ICH_LR12_EL2 = AARCH64_SYSREG_ICH_LR12_EL2, |
| 1112 | ARM64_SYSREG_ICH_LR13_EL2 = AARCH64_SYSREG_ICH_LR13_EL2, |
| 1113 | ARM64_SYSREG_ICH_LR14_EL2 = AARCH64_SYSREG_ICH_LR14_EL2, |
| 1114 | ARM64_SYSREG_ICH_LR15_EL2 = AARCH64_SYSREG_ICH_LR15_EL2, |
| 1115 | ARM64_SYSREG_ICH_LR1_EL2 = AARCH64_SYSREG_ICH_LR1_EL2, |
| 1116 | ARM64_SYSREG_ICH_LR2_EL2 = AARCH64_SYSREG_ICH_LR2_EL2, |
| 1117 | ARM64_SYSREG_ICH_LR3_EL2 = AARCH64_SYSREG_ICH_LR3_EL2, |
| 1118 | ARM64_SYSREG_ICH_LR4_EL2 = AARCH64_SYSREG_ICH_LR4_EL2, |
| 1119 | ARM64_SYSREG_ICH_LR5_EL2 = AARCH64_SYSREG_ICH_LR5_EL2, |
| 1120 | ARM64_SYSREG_ICH_LR6_EL2 = AARCH64_SYSREG_ICH_LR6_EL2, |
| 1121 | ARM64_SYSREG_ICH_LR7_EL2 = AARCH64_SYSREG_ICH_LR7_EL2, |
| 1122 | ARM64_SYSREG_ICH_LR8_EL2 = AARCH64_SYSREG_ICH_LR8_EL2, |
| 1123 | ARM64_SYSREG_ICH_LR9_EL2 = AARCH64_SYSREG_ICH_LR9_EL2, |
| 1124 | ARM64_SYSREG_ICH_MISR_EL2 = AARCH64_SYSREG_ICH_MISR_EL2, |
| 1125 | ARM64_SYSREG_ICH_VMCR_EL2 = AARCH64_SYSREG_ICH_VMCR_EL2, |
| 1126 | ARM64_SYSREG_ICH_VTR_EL2 = AARCH64_SYSREG_ICH_VTR_EL2, |
| 1127 | ARM64_SYSREG_ID_AA64AFR0_EL1 = AARCH64_SYSREG_ID_AA64AFR0_EL1, |
| 1128 | ARM64_SYSREG_ID_AA64AFR1_EL1 = AARCH64_SYSREG_ID_AA64AFR1_EL1, |
| 1129 | ARM64_SYSREG_ID_AA64DFR0_EL1 = AARCH64_SYSREG_ID_AA64DFR0_EL1, |
| 1130 | ARM64_SYSREG_ID_AA64DFR1_EL1 = AARCH64_SYSREG_ID_AA64DFR1_EL1, |
| 1131 | ARM64_SYSREG_ID_AA64DFR2_EL1 = AARCH64_SYSREG_ID_AA64DFR2_EL1, |
| 1132 | ARM64_SYSREG_ID_AA64FPFR0_EL1 = AARCH64_SYSREG_ID_AA64FPFR0_EL1, |
| 1133 | ARM64_SYSREG_ID_AA64ISAR0_EL1 = AARCH64_SYSREG_ID_AA64ISAR0_EL1, |
| 1134 | ARM64_SYSREG_ID_AA64ISAR1_EL1 = AARCH64_SYSREG_ID_AA64ISAR1_EL1, |
| 1135 | ARM64_SYSREG_ID_AA64ISAR2_EL1 = AARCH64_SYSREG_ID_AA64ISAR2_EL1, |
| 1136 | ARM64_SYSREG_ID_AA64ISAR3_EL1 = AARCH64_SYSREG_ID_AA64ISAR3_EL1, |
| 1137 | ARM64_SYSREG_ID_AA64MMFR0_EL1 = AARCH64_SYSREG_ID_AA64MMFR0_EL1, |
| 1138 | ARM64_SYSREG_ID_AA64MMFR1_EL1 = AARCH64_SYSREG_ID_AA64MMFR1_EL1, |
| 1139 | ARM64_SYSREG_ID_AA64MMFR2_EL1 = AARCH64_SYSREG_ID_AA64MMFR2_EL1, |
| 1140 | ARM64_SYSREG_ID_AA64MMFR3_EL1 = AARCH64_SYSREG_ID_AA64MMFR3_EL1, |
| 1141 | ARM64_SYSREG_ID_AA64MMFR4_EL1 = AARCH64_SYSREG_ID_AA64MMFR4_EL1, |
| 1142 | ARM64_SYSREG_ID_AA64PFR0_EL1 = AARCH64_SYSREG_ID_AA64PFR0_EL1, |
| 1143 | ARM64_SYSREG_ID_AA64PFR1_EL1 = AARCH64_SYSREG_ID_AA64PFR1_EL1, |
| 1144 | ARM64_SYSREG_ID_AA64PFR2_EL1 = AARCH64_SYSREG_ID_AA64PFR2_EL1, |
| 1145 | ARM64_SYSREG_ID_AA64SMFR0_EL1 = AARCH64_SYSREG_ID_AA64SMFR0_EL1, |
| 1146 | ARM64_SYSREG_ID_AA64ZFR0_EL1 = AARCH64_SYSREG_ID_AA64ZFR0_EL1, |
| 1147 | ARM64_SYSREG_ID_AFR0_EL1 = AARCH64_SYSREG_ID_AFR0_EL1, |
| 1148 | ARM64_SYSREG_ID_DFR0_EL1 = AARCH64_SYSREG_ID_DFR0_EL1, |
| 1149 | ARM64_SYSREG_ID_DFR1_EL1 = AARCH64_SYSREG_ID_DFR1_EL1, |
| 1150 | ARM64_SYSREG_ID_ISAR0_EL1 = AARCH64_SYSREG_ID_ISAR0_EL1, |
| 1151 | ARM64_SYSREG_ID_ISAR1_EL1 = AARCH64_SYSREG_ID_ISAR1_EL1, |
| 1152 | ARM64_SYSREG_ID_ISAR2_EL1 = AARCH64_SYSREG_ID_ISAR2_EL1, |
| 1153 | ARM64_SYSREG_ID_ISAR3_EL1 = AARCH64_SYSREG_ID_ISAR3_EL1, |
| 1154 | ARM64_SYSREG_ID_ISAR4_EL1 = AARCH64_SYSREG_ID_ISAR4_EL1, |
| 1155 | ARM64_SYSREG_ID_ISAR5_EL1 = AARCH64_SYSREG_ID_ISAR5_EL1, |
| 1156 | ARM64_SYSREG_ID_ISAR6_EL1 = AARCH64_SYSREG_ID_ISAR6_EL1, |
| 1157 | ARM64_SYSREG_ID_MMFR0_EL1 = AARCH64_SYSREG_ID_MMFR0_EL1, |
| 1158 | ARM64_SYSREG_ID_MMFR1_EL1 = AARCH64_SYSREG_ID_MMFR1_EL1, |
| 1159 | ARM64_SYSREG_ID_MMFR2_EL1 = AARCH64_SYSREG_ID_MMFR2_EL1, |
| 1160 | ARM64_SYSREG_ID_MMFR3_EL1 = AARCH64_SYSREG_ID_MMFR3_EL1, |
| 1161 | ARM64_SYSREG_ID_MMFR4_EL1 = AARCH64_SYSREG_ID_MMFR4_EL1, |
| 1162 | ARM64_SYSREG_ID_MMFR5_EL1 = AARCH64_SYSREG_ID_MMFR5_EL1, |
| 1163 | ARM64_SYSREG_ID_PFR0_EL1 = AARCH64_SYSREG_ID_PFR0_EL1, |
| 1164 | ARM64_SYSREG_ID_PFR1_EL1 = AARCH64_SYSREG_ID_PFR1_EL1, |
| 1165 | ARM64_SYSREG_ID_PFR2_EL1 = AARCH64_SYSREG_ID_PFR2_EL1, |
| 1166 | ARM64_SYSREG_IFSR32_EL2 = AARCH64_SYSREG_IFSR32_EL2, |
| 1167 | ARM64_SYSREG_ISR_EL1 = AARCH64_SYSREG_ISR_EL1, |
| 1168 | ARM64_SYSREG_LORC_EL1 = AARCH64_SYSREG_LORC_EL1, |
| 1169 | ARM64_SYSREG_LOREA_EL1 = AARCH64_SYSREG_LOREA_EL1, |
| 1170 | ARM64_SYSREG_LORID_EL1 = AARCH64_SYSREG_LORID_EL1, |
| 1171 | ARM64_SYSREG_LORN_EL1 = AARCH64_SYSREG_LORN_EL1, |
| 1172 | ARM64_SYSREG_LORSA_EL1 = AARCH64_SYSREG_LORSA_EL1, |
| 1173 | ARM64_SYSREG_MAIR2_EL1 = AARCH64_SYSREG_MAIR2_EL1, |
| 1174 | ARM64_SYSREG_MAIR2_EL12 = AARCH64_SYSREG_MAIR2_EL12, |
| 1175 | ARM64_SYSREG_MAIR2_EL2 = AARCH64_SYSREG_MAIR2_EL2, |
| 1176 | ARM64_SYSREG_MAIR2_EL3 = AARCH64_SYSREG_MAIR2_EL3, |
| 1177 | ARM64_SYSREG_MAIR_EL1 = AARCH64_SYSREG_MAIR_EL1, |
| 1178 | ARM64_SYSREG_MAIR_EL12 = AARCH64_SYSREG_MAIR_EL12, |
| 1179 | ARM64_SYSREG_MAIR_EL2 = AARCH64_SYSREG_MAIR_EL2, |
| 1180 | ARM64_SYSREG_MAIR_EL3 = AARCH64_SYSREG_MAIR_EL3, |
| 1181 | ARM64_SYSREG_MDCCINT_EL1 = AARCH64_SYSREG_MDCCINT_EL1, |
| 1182 | ARM64_SYSREG_MDCCSR_EL0 = AARCH64_SYSREG_MDCCSR_EL0, |
| 1183 | ARM64_SYSREG_MDCR_EL2 = AARCH64_SYSREG_MDCR_EL2, |
| 1184 | ARM64_SYSREG_MDCR_EL3 = AARCH64_SYSREG_MDCR_EL3, |
| 1185 | ARM64_SYSREG_MDRAR_EL1 = AARCH64_SYSREG_MDRAR_EL1, |
| 1186 | ARM64_SYSREG_MDSCR_EL1 = AARCH64_SYSREG_MDSCR_EL1, |
| 1187 | ARM64_SYSREG_MDSELR_EL1 = AARCH64_SYSREG_MDSELR_EL1, |
| 1188 | ARM64_SYSREG_MDSTEPOP_EL1 = AARCH64_SYSREG_MDSTEPOP_EL1, |
| 1189 | ARM64_SYSREG_MECIDR_EL2 = AARCH64_SYSREG_MECIDR_EL2, |
| 1190 | ARM64_SYSREG_MECID_A0_EL2 = AARCH64_SYSREG_MECID_A0_EL2, |
| 1191 | ARM64_SYSREG_MECID_A1_EL2 = AARCH64_SYSREG_MECID_A1_EL2, |
| 1192 | ARM64_SYSREG_MECID_P0_EL2 = AARCH64_SYSREG_MECID_P0_EL2, |
| 1193 | ARM64_SYSREG_MECID_P1_EL2 = AARCH64_SYSREG_MECID_P1_EL2, |
| 1194 | ARM64_SYSREG_MECID_RL_A_EL3 = AARCH64_SYSREG_MECID_RL_A_EL3, |
| 1195 | ARM64_SYSREG_MFAR_EL3 = AARCH64_SYSREG_MFAR_EL3, |
| 1196 | ARM64_SYSREG_MIDR_EL1 = AARCH64_SYSREG_MIDR_EL1, |
| 1197 | ARM64_SYSREG_MPAM0_EL1 = AARCH64_SYSREG_MPAM0_EL1, |
| 1198 | ARM64_SYSREG_MPAM1_EL1 = AARCH64_SYSREG_MPAM1_EL1, |
| 1199 | ARM64_SYSREG_MPAM1_EL12 = AARCH64_SYSREG_MPAM1_EL12, |
| 1200 | ARM64_SYSREG_MPAM2_EL2 = AARCH64_SYSREG_MPAM2_EL2, |
| 1201 | ARM64_SYSREG_MPAM3_EL3 = AARCH64_SYSREG_MPAM3_EL3, |
| 1202 | ARM64_SYSREG_MPAMHCR_EL2 = AARCH64_SYSREG_MPAMHCR_EL2, |
| 1203 | ARM64_SYSREG_MPAMIDR_EL1 = AARCH64_SYSREG_MPAMIDR_EL1, |
| 1204 | ARM64_SYSREG_MPAMSM_EL1 = AARCH64_SYSREG_MPAMSM_EL1, |
| 1205 | ARM64_SYSREG_MPAMVPM0_EL2 = AARCH64_SYSREG_MPAMVPM0_EL2, |
| 1206 | ARM64_SYSREG_MPAMVPM1_EL2 = AARCH64_SYSREG_MPAMVPM1_EL2, |
| 1207 | ARM64_SYSREG_MPAMVPM2_EL2 = AARCH64_SYSREG_MPAMVPM2_EL2, |
| 1208 | ARM64_SYSREG_MPAMVPM3_EL2 = AARCH64_SYSREG_MPAMVPM3_EL2, |
| 1209 | ARM64_SYSREG_MPAMVPM4_EL2 = AARCH64_SYSREG_MPAMVPM4_EL2, |
| 1210 | ARM64_SYSREG_MPAMVPM5_EL2 = AARCH64_SYSREG_MPAMVPM5_EL2, |
| 1211 | ARM64_SYSREG_MPAMVPM6_EL2 = AARCH64_SYSREG_MPAMVPM6_EL2, |
| 1212 | ARM64_SYSREG_MPAMVPM7_EL2 = AARCH64_SYSREG_MPAMVPM7_EL2, |
| 1213 | ARM64_SYSREG_MPAMVPMV_EL2 = AARCH64_SYSREG_MPAMVPMV_EL2, |
| 1214 | ARM64_SYSREG_MPIDR_EL1 = AARCH64_SYSREG_MPIDR_EL1, |
| 1215 | ARM64_SYSREG_MPUIR_EL1 = AARCH64_SYSREG_MPUIR_EL1, |
| 1216 | ARM64_SYSREG_MPUIR_EL2 = AARCH64_SYSREG_MPUIR_EL2, |
| 1217 | ARM64_SYSREG_MVFR0_EL1 = AARCH64_SYSREG_MVFR0_EL1, |
| 1218 | ARM64_SYSREG_MVFR1_EL1 = AARCH64_SYSREG_MVFR1_EL1, |
| 1219 | ARM64_SYSREG_MVFR2_EL1 = AARCH64_SYSREG_MVFR2_EL1, |
| 1220 | ARM64_SYSREG_NZCV = AARCH64_SYSREG_NZCV, |
| 1221 | ARM64_SYSREG_OSDLR_EL1 = AARCH64_SYSREG_OSDLR_EL1, |
| 1222 | ARM64_SYSREG_OSDTRRX_EL1 = AARCH64_SYSREG_OSDTRRX_EL1, |
| 1223 | ARM64_SYSREG_OSDTRTX_EL1 = AARCH64_SYSREG_OSDTRTX_EL1, |
| 1224 | ARM64_SYSREG_OSECCR_EL1 = AARCH64_SYSREG_OSECCR_EL1, |
| 1225 | ARM64_SYSREG_OSLAR_EL1 = AARCH64_SYSREG_OSLAR_EL1, |
| 1226 | ARM64_SYSREG_OSLSR_EL1 = AARCH64_SYSREG_OSLSR_EL1, |
| 1227 | ARM64_SYSREG_PAN = AARCH64_SYSREG_PAN, |
| 1228 | ARM64_SYSREG_PAR_EL1 = AARCH64_SYSREG_PAR_EL1, |
| 1229 | ARM64_SYSREG_PFAR_EL1 = AARCH64_SYSREG_PFAR_EL1, |
| 1230 | ARM64_SYSREG_PFAR_EL12 = AARCH64_SYSREG_PFAR_EL12, |
| 1231 | ARM64_SYSREG_PFAR_EL2 = AARCH64_SYSREG_PFAR_EL2, |
| 1232 | ARM64_SYSREG_PIRE0_EL1 = AARCH64_SYSREG_PIRE0_EL1, |
| 1233 | ARM64_SYSREG_PIRE0_EL12 = AARCH64_SYSREG_PIRE0_EL12, |
| 1234 | ARM64_SYSREG_PIRE0_EL2 = AARCH64_SYSREG_PIRE0_EL2, |
| 1235 | ARM64_SYSREG_PIR_EL1 = AARCH64_SYSREG_PIR_EL1, |
| 1236 | ARM64_SYSREG_PIR_EL12 = AARCH64_SYSREG_PIR_EL12, |
| 1237 | ARM64_SYSREG_PIR_EL2 = AARCH64_SYSREG_PIR_EL2, |
| 1238 | ARM64_SYSREG_PIR_EL3 = AARCH64_SYSREG_PIR_EL3, |
| 1239 | ARM64_SYSREG_PM = AARCH64_SYSREG_PM, |
| 1240 | ARM64_SYSREG_PMBIDR_EL1 = AARCH64_SYSREG_PMBIDR_EL1, |
| 1241 | ARM64_SYSREG_PMBLIMITR_EL1 = AARCH64_SYSREG_PMBLIMITR_EL1, |
| 1242 | ARM64_SYSREG_PMBPTR_EL1 = AARCH64_SYSREG_PMBPTR_EL1, |
| 1243 | ARM64_SYSREG_PMBSR_EL1 = AARCH64_SYSREG_PMBSR_EL1, |
| 1244 | ARM64_SYSREG_PMCCFILTR_EL0 = AARCH64_SYSREG_PMCCFILTR_EL0, |
| 1245 | ARM64_SYSREG_PMCCNTR_EL0 = AARCH64_SYSREG_PMCCNTR_EL0, |
| 1246 | ARM64_SYSREG_PMCCNTSVR_EL1 = AARCH64_SYSREG_PMCCNTSVR_EL1, |
| 1247 | ARM64_SYSREG_PMCEID0_EL0 = AARCH64_SYSREG_PMCEID0_EL0, |
| 1248 | ARM64_SYSREG_PMCEID1_EL0 = AARCH64_SYSREG_PMCEID1_EL0, |
| 1249 | ARM64_SYSREG_PMCNTENCLR_EL0 = AARCH64_SYSREG_PMCNTENCLR_EL0, |
| 1250 | ARM64_SYSREG_PMCNTENSET_EL0 = AARCH64_SYSREG_PMCNTENSET_EL0, |
| 1251 | ARM64_SYSREG_PMCR_EL0 = AARCH64_SYSREG_PMCR_EL0, |
| 1252 | ARM64_SYSREG_PMECR_EL1 = AARCH64_SYSREG_PMECR_EL1, |
| 1253 | ARM64_SYSREG_PMEVCNTR0_EL0 = AARCH64_SYSREG_PMEVCNTR0_EL0, |
| 1254 | ARM64_SYSREG_PMEVCNTR10_EL0 = AARCH64_SYSREG_PMEVCNTR10_EL0, |
| 1255 | ARM64_SYSREG_PMEVCNTR11_EL0 = AARCH64_SYSREG_PMEVCNTR11_EL0, |
| 1256 | ARM64_SYSREG_PMEVCNTR12_EL0 = AARCH64_SYSREG_PMEVCNTR12_EL0, |
| 1257 | ARM64_SYSREG_PMEVCNTR13_EL0 = AARCH64_SYSREG_PMEVCNTR13_EL0, |
| 1258 | ARM64_SYSREG_PMEVCNTR14_EL0 = AARCH64_SYSREG_PMEVCNTR14_EL0, |
| 1259 | ARM64_SYSREG_PMEVCNTR15_EL0 = AARCH64_SYSREG_PMEVCNTR15_EL0, |
| 1260 | ARM64_SYSREG_PMEVCNTR16_EL0 = AARCH64_SYSREG_PMEVCNTR16_EL0, |
| 1261 | ARM64_SYSREG_PMEVCNTR17_EL0 = AARCH64_SYSREG_PMEVCNTR17_EL0, |
| 1262 | ARM64_SYSREG_PMEVCNTR18_EL0 = AARCH64_SYSREG_PMEVCNTR18_EL0, |
| 1263 | ARM64_SYSREG_PMEVCNTR19_EL0 = AARCH64_SYSREG_PMEVCNTR19_EL0, |
| 1264 | ARM64_SYSREG_PMEVCNTR1_EL0 = AARCH64_SYSREG_PMEVCNTR1_EL0, |
| 1265 | ARM64_SYSREG_PMEVCNTR20_EL0 = AARCH64_SYSREG_PMEVCNTR20_EL0, |
| 1266 | ARM64_SYSREG_PMEVCNTR21_EL0 = AARCH64_SYSREG_PMEVCNTR21_EL0, |
| 1267 | ARM64_SYSREG_PMEVCNTR22_EL0 = AARCH64_SYSREG_PMEVCNTR22_EL0, |
| 1268 | ARM64_SYSREG_PMEVCNTR23_EL0 = AARCH64_SYSREG_PMEVCNTR23_EL0, |
| 1269 | ARM64_SYSREG_PMEVCNTR24_EL0 = AARCH64_SYSREG_PMEVCNTR24_EL0, |
| 1270 | ARM64_SYSREG_PMEVCNTR25_EL0 = AARCH64_SYSREG_PMEVCNTR25_EL0, |
| 1271 | ARM64_SYSREG_PMEVCNTR26_EL0 = AARCH64_SYSREG_PMEVCNTR26_EL0, |
| 1272 | ARM64_SYSREG_PMEVCNTR27_EL0 = AARCH64_SYSREG_PMEVCNTR27_EL0, |
| 1273 | ARM64_SYSREG_PMEVCNTR28_EL0 = AARCH64_SYSREG_PMEVCNTR28_EL0, |
| 1274 | ARM64_SYSREG_PMEVCNTR29_EL0 = AARCH64_SYSREG_PMEVCNTR29_EL0, |
| 1275 | ARM64_SYSREG_PMEVCNTR2_EL0 = AARCH64_SYSREG_PMEVCNTR2_EL0, |
| 1276 | ARM64_SYSREG_PMEVCNTR30_EL0 = AARCH64_SYSREG_PMEVCNTR30_EL0, |
| 1277 | ARM64_SYSREG_PMEVCNTR3_EL0 = AARCH64_SYSREG_PMEVCNTR3_EL0, |
| 1278 | ARM64_SYSREG_PMEVCNTR4_EL0 = AARCH64_SYSREG_PMEVCNTR4_EL0, |
| 1279 | ARM64_SYSREG_PMEVCNTR5_EL0 = AARCH64_SYSREG_PMEVCNTR5_EL0, |
| 1280 | ARM64_SYSREG_PMEVCNTR6_EL0 = AARCH64_SYSREG_PMEVCNTR6_EL0, |
| 1281 | ARM64_SYSREG_PMEVCNTR7_EL0 = AARCH64_SYSREG_PMEVCNTR7_EL0, |
| 1282 | ARM64_SYSREG_PMEVCNTR8_EL0 = AARCH64_SYSREG_PMEVCNTR8_EL0, |
| 1283 | ARM64_SYSREG_PMEVCNTR9_EL0 = AARCH64_SYSREG_PMEVCNTR9_EL0, |
| 1284 | ARM64_SYSREG_PMEVCNTSVR0_EL1 = AARCH64_SYSREG_PMEVCNTSVR0_EL1, |
| 1285 | ARM64_SYSREG_PMEVCNTSVR10_EL1 = AARCH64_SYSREG_PMEVCNTSVR10_EL1, |
| 1286 | ARM64_SYSREG_PMEVCNTSVR11_EL1 = AARCH64_SYSREG_PMEVCNTSVR11_EL1, |
| 1287 | ARM64_SYSREG_PMEVCNTSVR12_EL1 = AARCH64_SYSREG_PMEVCNTSVR12_EL1, |
| 1288 | ARM64_SYSREG_PMEVCNTSVR13_EL1 = AARCH64_SYSREG_PMEVCNTSVR13_EL1, |
| 1289 | ARM64_SYSREG_PMEVCNTSVR14_EL1 = AARCH64_SYSREG_PMEVCNTSVR14_EL1, |
| 1290 | ARM64_SYSREG_PMEVCNTSVR15_EL1 = AARCH64_SYSREG_PMEVCNTSVR15_EL1, |
| 1291 | ARM64_SYSREG_PMEVCNTSVR16_EL1 = AARCH64_SYSREG_PMEVCNTSVR16_EL1, |
| 1292 | ARM64_SYSREG_PMEVCNTSVR17_EL1 = AARCH64_SYSREG_PMEVCNTSVR17_EL1, |
| 1293 | ARM64_SYSREG_PMEVCNTSVR18_EL1 = AARCH64_SYSREG_PMEVCNTSVR18_EL1, |
| 1294 | ARM64_SYSREG_PMEVCNTSVR19_EL1 = AARCH64_SYSREG_PMEVCNTSVR19_EL1, |
| 1295 | ARM64_SYSREG_PMEVCNTSVR1_EL1 = AARCH64_SYSREG_PMEVCNTSVR1_EL1, |
| 1296 | ARM64_SYSREG_PMEVCNTSVR20_EL1 = AARCH64_SYSREG_PMEVCNTSVR20_EL1, |
| 1297 | ARM64_SYSREG_PMEVCNTSVR21_EL1 = AARCH64_SYSREG_PMEVCNTSVR21_EL1, |
| 1298 | ARM64_SYSREG_PMEVCNTSVR22_EL1 = AARCH64_SYSREG_PMEVCNTSVR22_EL1, |
| 1299 | ARM64_SYSREG_PMEVCNTSVR23_EL1 = AARCH64_SYSREG_PMEVCNTSVR23_EL1, |
| 1300 | ARM64_SYSREG_PMEVCNTSVR24_EL1 = AARCH64_SYSREG_PMEVCNTSVR24_EL1, |
| 1301 | ARM64_SYSREG_PMEVCNTSVR25_EL1 = AARCH64_SYSREG_PMEVCNTSVR25_EL1, |
| 1302 | ARM64_SYSREG_PMEVCNTSVR26_EL1 = AARCH64_SYSREG_PMEVCNTSVR26_EL1, |
| 1303 | ARM64_SYSREG_PMEVCNTSVR27_EL1 = AARCH64_SYSREG_PMEVCNTSVR27_EL1, |
| 1304 | ARM64_SYSREG_PMEVCNTSVR28_EL1 = AARCH64_SYSREG_PMEVCNTSVR28_EL1, |
| 1305 | ARM64_SYSREG_PMEVCNTSVR29_EL1 = AARCH64_SYSREG_PMEVCNTSVR29_EL1, |
| 1306 | ARM64_SYSREG_PMEVCNTSVR2_EL1 = AARCH64_SYSREG_PMEVCNTSVR2_EL1, |
| 1307 | ARM64_SYSREG_PMEVCNTSVR30_EL1 = AARCH64_SYSREG_PMEVCNTSVR30_EL1, |
| 1308 | ARM64_SYSREG_PMEVCNTSVR3_EL1 = AARCH64_SYSREG_PMEVCNTSVR3_EL1, |
| 1309 | ARM64_SYSREG_PMEVCNTSVR4_EL1 = AARCH64_SYSREG_PMEVCNTSVR4_EL1, |
| 1310 | ARM64_SYSREG_PMEVCNTSVR5_EL1 = AARCH64_SYSREG_PMEVCNTSVR5_EL1, |
| 1311 | ARM64_SYSREG_PMEVCNTSVR6_EL1 = AARCH64_SYSREG_PMEVCNTSVR6_EL1, |
| 1312 | ARM64_SYSREG_PMEVCNTSVR7_EL1 = AARCH64_SYSREG_PMEVCNTSVR7_EL1, |
| 1313 | ARM64_SYSREG_PMEVCNTSVR8_EL1 = AARCH64_SYSREG_PMEVCNTSVR8_EL1, |
| 1314 | ARM64_SYSREG_PMEVCNTSVR9_EL1 = AARCH64_SYSREG_PMEVCNTSVR9_EL1, |
| 1315 | ARM64_SYSREG_PMEVTYPER0_EL0 = AARCH64_SYSREG_PMEVTYPER0_EL0, |
| 1316 | ARM64_SYSREG_PMEVTYPER10_EL0 = AARCH64_SYSREG_PMEVTYPER10_EL0, |
| 1317 | ARM64_SYSREG_PMEVTYPER11_EL0 = AARCH64_SYSREG_PMEVTYPER11_EL0, |
| 1318 | ARM64_SYSREG_PMEVTYPER12_EL0 = AARCH64_SYSREG_PMEVTYPER12_EL0, |
| 1319 | ARM64_SYSREG_PMEVTYPER13_EL0 = AARCH64_SYSREG_PMEVTYPER13_EL0, |
| 1320 | ARM64_SYSREG_PMEVTYPER14_EL0 = AARCH64_SYSREG_PMEVTYPER14_EL0, |
| 1321 | ARM64_SYSREG_PMEVTYPER15_EL0 = AARCH64_SYSREG_PMEVTYPER15_EL0, |
| 1322 | ARM64_SYSREG_PMEVTYPER16_EL0 = AARCH64_SYSREG_PMEVTYPER16_EL0, |
| 1323 | ARM64_SYSREG_PMEVTYPER17_EL0 = AARCH64_SYSREG_PMEVTYPER17_EL0, |
| 1324 | ARM64_SYSREG_PMEVTYPER18_EL0 = AARCH64_SYSREG_PMEVTYPER18_EL0, |
| 1325 | ARM64_SYSREG_PMEVTYPER19_EL0 = AARCH64_SYSREG_PMEVTYPER19_EL0, |
| 1326 | ARM64_SYSREG_PMEVTYPER1_EL0 = AARCH64_SYSREG_PMEVTYPER1_EL0, |
| 1327 | ARM64_SYSREG_PMEVTYPER20_EL0 = AARCH64_SYSREG_PMEVTYPER20_EL0, |
| 1328 | ARM64_SYSREG_PMEVTYPER21_EL0 = AARCH64_SYSREG_PMEVTYPER21_EL0, |
| 1329 | ARM64_SYSREG_PMEVTYPER22_EL0 = AARCH64_SYSREG_PMEVTYPER22_EL0, |
| 1330 | ARM64_SYSREG_PMEVTYPER23_EL0 = AARCH64_SYSREG_PMEVTYPER23_EL0, |
| 1331 | ARM64_SYSREG_PMEVTYPER24_EL0 = AARCH64_SYSREG_PMEVTYPER24_EL0, |
| 1332 | ARM64_SYSREG_PMEVTYPER25_EL0 = AARCH64_SYSREG_PMEVTYPER25_EL0, |
| 1333 | ARM64_SYSREG_PMEVTYPER26_EL0 = AARCH64_SYSREG_PMEVTYPER26_EL0, |
| 1334 | ARM64_SYSREG_PMEVTYPER27_EL0 = AARCH64_SYSREG_PMEVTYPER27_EL0, |
| 1335 | ARM64_SYSREG_PMEVTYPER28_EL0 = AARCH64_SYSREG_PMEVTYPER28_EL0, |
| 1336 | ARM64_SYSREG_PMEVTYPER29_EL0 = AARCH64_SYSREG_PMEVTYPER29_EL0, |
| 1337 | ARM64_SYSREG_PMEVTYPER2_EL0 = AARCH64_SYSREG_PMEVTYPER2_EL0, |
| 1338 | ARM64_SYSREG_PMEVTYPER30_EL0 = AARCH64_SYSREG_PMEVTYPER30_EL0, |
| 1339 | ARM64_SYSREG_PMEVTYPER3_EL0 = AARCH64_SYSREG_PMEVTYPER3_EL0, |
| 1340 | ARM64_SYSREG_PMEVTYPER4_EL0 = AARCH64_SYSREG_PMEVTYPER4_EL0, |
| 1341 | ARM64_SYSREG_PMEVTYPER5_EL0 = AARCH64_SYSREG_PMEVTYPER5_EL0, |
| 1342 | ARM64_SYSREG_PMEVTYPER6_EL0 = AARCH64_SYSREG_PMEVTYPER6_EL0, |
| 1343 | ARM64_SYSREG_PMEVTYPER7_EL0 = AARCH64_SYSREG_PMEVTYPER7_EL0, |
| 1344 | ARM64_SYSREG_PMEVTYPER8_EL0 = AARCH64_SYSREG_PMEVTYPER8_EL0, |
| 1345 | ARM64_SYSREG_PMEVTYPER9_EL0 = AARCH64_SYSREG_PMEVTYPER9_EL0, |
| 1346 | ARM64_SYSREG_PMIAR_EL1 = AARCH64_SYSREG_PMIAR_EL1, |
| 1347 | ARM64_SYSREG_PMICFILTR_EL0 = AARCH64_SYSREG_PMICFILTR_EL0, |
| 1348 | ARM64_SYSREG_PMICNTR_EL0 = AARCH64_SYSREG_PMICNTR_EL0, |
| 1349 | ARM64_SYSREG_PMICNTSVR_EL1 = AARCH64_SYSREG_PMICNTSVR_EL1, |
| 1350 | ARM64_SYSREG_PMINTENCLR_EL1 = AARCH64_SYSREG_PMINTENCLR_EL1, |
| 1351 | ARM64_SYSREG_PMINTENSET_EL1 = AARCH64_SYSREG_PMINTENSET_EL1, |
| 1352 | ARM64_SYSREG_PMMIR_EL1 = AARCH64_SYSREG_PMMIR_EL1, |
| 1353 | ARM64_SYSREG_PMOVSCLR_EL0 = AARCH64_SYSREG_PMOVSCLR_EL0, |
| 1354 | ARM64_SYSREG_PMOVSSET_EL0 = AARCH64_SYSREG_PMOVSSET_EL0, |
| 1355 | ARM64_SYSREG_PMSCR_EL1 = AARCH64_SYSREG_PMSCR_EL1, |
| 1356 | ARM64_SYSREG_PMSCR_EL12 = AARCH64_SYSREG_PMSCR_EL12, |
| 1357 | ARM64_SYSREG_PMSCR_EL2 = AARCH64_SYSREG_PMSCR_EL2, |
| 1358 | ARM64_SYSREG_PMSDSFR_EL1 = AARCH64_SYSREG_PMSDSFR_EL1, |
| 1359 | ARM64_SYSREG_PMSELR_EL0 = AARCH64_SYSREG_PMSELR_EL0, |
| 1360 | ARM64_SYSREG_PMSEVFR_EL1 = AARCH64_SYSREG_PMSEVFR_EL1, |
| 1361 | ARM64_SYSREG_PMSFCR_EL1 = AARCH64_SYSREG_PMSFCR_EL1, |
| 1362 | ARM64_SYSREG_PMSICR_EL1 = AARCH64_SYSREG_PMSICR_EL1, |
| 1363 | ARM64_SYSREG_PMSIDR_EL1 = AARCH64_SYSREG_PMSIDR_EL1, |
| 1364 | ARM64_SYSREG_PMSIRR_EL1 = AARCH64_SYSREG_PMSIRR_EL1, |
| 1365 | ARM64_SYSREG_PMSLATFR_EL1 = AARCH64_SYSREG_PMSLATFR_EL1, |
| 1366 | ARM64_SYSREG_PMSNEVFR_EL1 = AARCH64_SYSREG_PMSNEVFR_EL1, |
| 1367 | ARM64_SYSREG_PMSSCR_EL1 = AARCH64_SYSREG_PMSSCR_EL1, |
| 1368 | ARM64_SYSREG_PMSWINC_EL0 = AARCH64_SYSREG_PMSWINC_EL0, |
| 1369 | ARM64_SYSREG_PMUACR_EL1 = AARCH64_SYSREG_PMUACR_EL1, |
| 1370 | ARM64_SYSREG_PMUSERENR_EL0 = AARCH64_SYSREG_PMUSERENR_EL0, |
| 1371 | ARM64_SYSREG_PMXEVCNTR_EL0 = AARCH64_SYSREG_PMXEVCNTR_EL0, |
| 1372 | ARM64_SYSREG_PMXEVTYPER_EL0 = AARCH64_SYSREG_PMXEVTYPER_EL0, |
| 1373 | ARM64_SYSREG_PMZR_EL0 = AARCH64_SYSREG_PMZR_EL0, |
| 1374 | ARM64_SYSREG_POR_EL0 = AARCH64_SYSREG_POR_EL0, |
| 1375 | ARM64_SYSREG_POR_EL1 = AARCH64_SYSREG_POR_EL1, |
| 1376 | ARM64_SYSREG_POR_EL12 = AARCH64_SYSREG_POR_EL12, |
| 1377 | ARM64_SYSREG_POR_EL2 = AARCH64_SYSREG_POR_EL2, |
| 1378 | ARM64_SYSREG_POR_EL3 = AARCH64_SYSREG_POR_EL3, |
| 1379 | ARM64_SYSREG_PRBAR10_EL1 = AARCH64_SYSREG_PRBAR10_EL1, |
| 1380 | ARM64_SYSREG_PRBAR10_EL2 = AARCH64_SYSREG_PRBAR10_EL2, |
| 1381 | ARM64_SYSREG_PRBAR11_EL1 = AARCH64_SYSREG_PRBAR11_EL1, |
| 1382 | ARM64_SYSREG_PRBAR11_EL2 = AARCH64_SYSREG_PRBAR11_EL2, |
| 1383 | ARM64_SYSREG_PRBAR12_EL1 = AARCH64_SYSREG_PRBAR12_EL1, |
| 1384 | ARM64_SYSREG_PRBAR12_EL2 = AARCH64_SYSREG_PRBAR12_EL2, |
| 1385 | ARM64_SYSREG_PRBAR13_EL1 = AARCH64_SYSREG_PRBAR13_EL1, |
| 1386 | ARM64_SYSREG_PRBAR13_EL2 = AARCH64_SYSREG_PRBAR13_EL2, |
| 1387 | ARM64_SYSREG_PRBAR14_EL1 = AARCH64_SYSREG_PRBAR14_EL1, |
| 1388 | ARM64_SYSREG_PRBAR14_EL2 = AARCH64_SYSREG_PRBAR14_EL2, |
| 1389 | ARM64_SYSREG_PRBAR15_EL1 = AARCH64_SYSREG_PRBAR15_EL1, |
| 1390 | ARM64_SYSREG_PRBAR15_EL2 = AARCH64_SYSREG_PRBAR15_EL2, |
| 1391 | ARM64_SYSREG_PRBAR1_EL1 = AARCH64_SYSREG_PRBAR1_EL1, |
| 1392 | ARM64_SYSREG_PRBAR1_EL2 = AARCH64_SYSREG_PRBAR1_EL2, |
| 1393 | ARM64_SYSREG_PRBAR2_EL1 = AARCH64_SYSREG_PRBAR2_EL1, |
| 1394 | ARM64_SYSREG_PRBAR2_EL2 = AARCH64_SYSREG_PRBAR2_EL2, |
| 1395 | ARM64_SYSREG_PRBAR3_EL1 = AARCH64_SYSREG_PRBAR3_EL1, |
| 1396 | ARM64_SYSREG_PRBAR3_EL2 = AARCH64_SYSREG_PRBAR3_EL2, |
| 1397 | ARM64_SYSREG_PRBAR4_EL1 = AARCH64_SYSREG_PRBAR4_EL1, |
| 1398 | ARM64_SYSREG_PRBAR4_EL2 = AARCH64_SYSREG_PRBAR4_EL2, |
| 1399 | ARM64_SYSREG_PRBAR5_EL1 = AARCH64_SYSREG_PRBAR5_EL1, |
| 1400 | ARM64_SYSREG_PRBAR5_EL2 = AARCH64_SYSREG_PRBAR5_EL2, |
| 1401 | ARM64_SYSREG_PRBAR6_EL1 = AARCH64_SYSREG_PRBAR6_EL1, |
| 1402 | ARM64_SYSREG_PRBAR6_EL2 = AARCH64_SYSREG_PRBAR6_EL2, |
| 1403 | ARM64_SYSREG_PRBAR7_EL1 = AARCH64_SYSREG_PRBAR7_EL1, |
| 1404 | ARM64_SYSREG_PRBAR7_EL2 = AARCH64_SYSREG_PRBAR7_EL2, |
| 1405 | ARM64_SYSREG_PRBAR8_EL1 = AARCH64_SYSREG_PRBAR8_EL1, |
| 1406 | ARM64_SYSREG_PRBAR8_EL2 = AARCH64_SYSREG_PRBAR8_EL2, |
| 1407 | ARM64_SYSREG_PRBAR9_EL1 = AARCH64_SYSREG_PRBAR9_EL1, |
| 1408 | ARM64_SYSREG_PRBAR9_EL2 = AARCH64_SYSREG_PRBAR9_EL2, |
| 1409 | ARM64_SYSREG_PRBAR_EL1 = AARCH64_SYSREG_PRBAR_EL1, |
| 1410 | ARM64_SYSREG_PRBAR_EL2 = AARCH64_SYSREG_PRBAR_EL2, |
| 1411 | ARM64_SYSREG_PRENR_EL1 = AARCH64_SYSREG_PRENR_EL1, |
| 1412 | ARM64_SYSREG_PRENR_EL2 = AARCH64_SYSREG_PRENR_EL2, |
| 1413 | ARM64_SYSREG_PRLAR10_EL1 = AARCH64_SYSREG_PRLAR10_EL1, |
| 1414 | ARM64_SYSREG_PRLAR10_EL2 = AARCH64_SYSREG_PRLAR10_EL2, |
| 1415 | ARM64_SYSREG_PRLAR11_EL1 = AARCH64_SYSREG_PRLAR11_EL1, |
| 1416 | ARM64_SYSREG_PRLAR11_EL2 = AARCH64_SYSREG_PRLAR11_EL2, |
| 1417 | ARM64_SYSREG_PRLAR12_EL1 = AARCH64_SYSREG_PRLAR12_EL1, |
| 1418 | ARM64_SYSREG_PRLAR12_EL2 = AARCH64_SYSREG_PRLAR12_EL2, |
| 1419 | ARM64_SYSREG_PRLAR13_EL1 = AARCH64_SYSREG_PRLAR13_EL1, |
| 1420 | ARM64_SYSREG_PRLAR13_EL2 = AARCH64_SYSREG_PRLAR13_EL2, |
| 1421 | ARM64_SYSREG_PRLAR14_EL1 = AARCH64_SYSREG_PRLAR14_EL1, |
| 1422 | ARM64_SYSREG_PRLAR14_EL2 = AARCH64_SYSREG_PRLAR14_EL2, |
| 1423 | ARM64_SYSREG_PRLAR15_EL1 = AARCH64_SYSREG_PRLAR15_EL1, |
| 1424 | ARM64_SYSREG_PRLAR15_EL2 = AARCH64_SYSREG_PRLAR15_EL2, |
| 1425 | ARM64_SYSREG_PRLAR1_EL1 = AARCH64_SYSREG_PRLAR1_EL1, |
| 1426 | ARM64_SYSREG_PRLAR1_EL2 = AARCH64_SYSREG_PRLAR1_EL2, |
| 1427 | ARM64_SYSREG_PRLAR2_EL1 = AARCH64_SYSREG_PRLAR2_EL1, |
| 1428 | ARM64_SYSREG_PRLAR2_EL2 = AARCH64_SYSREG_PRLAR2_EL2, |
| 1429 | ARM64_SYSREG_PRLAR3_EL1 = AARCH64_SYSREG_PRLAR3_EL1, |
| 1430 | ARM64_SYSREG_PRLAR3_EL2 = AARCH64_SYSREG_PRLAR3_EL2, |
| 1431 | ARM64_SYSREG_PRLAR4_EL1 = AARCH64_SYSREG_PRLAR4_EL1, |
| 1432 | ARM64_SYSREG_PRLAR4_EL2 = AARCH64_SYSREG_PRLAR4_EL2, |
| 1433 | ARM64_SYSREG_PRLAR5_EL1 = AARCH64_SYSREG_PRLAR5_EL1, |
| 1434 | ARM64_SYSREG_PRLAR5_EL2 = AARCH64_SYSREG_PRLAR5_EL2, |
| 1435 | ARM64_SYSREG_PRLAR6_EL1 = AARCH64_SYSREG_PRLAR6_EL1, |
| 1436 | ARM64_SYSREG_PRLAR6_EL2 = AARCH64_SYSREG_PRLAR6_EL2, |
| 1437 | ARM64_SYSREG_PRLAR7_EL1 = AARCH64_SYSREG_PRLAR7_EL1, |
| 1438 | ARM64_SYSREG_PRLAR7_EL2 = AARCH64_SYSREG_PRLAR7_EL2, |
| 1439 | ARM64_SYSREG_PRLAR8_EL1 = AARCH64_SYSREG_PRLAR8_EL1, |
| 1440 | ARM64_SYSREG_PRLAR8_EL2 = AARCH64_SYSREG_PRLAR8_EL2, |
| 1441 | ARM64_SYSREG_PRLAR9_EL1 = AARCH64_SYSREG_PRLAR9_EL1, |
| 1442 | ARM64_SYSREG_PRLAR9_EL2 = AARCH64_SYSREG_PRLAR9_EL2, |
| 1443 | ARM64_SYSREG_PRLAR_EL1 = AARCH64_SYSREG_PRLAR_EL1, |
| 1444 | ARM64_SYSREG_PRLAR_EL2 = AARCH64_SYSREG_PRLAR_EL2, |
| 1445 | ARM64_SYSREG_PRSELR_EL1 = AARCH64_SYSREG_PRSELR_EL1, |
| 1446 | ARM64_SYSREG_PRSELR_EL2 = AARCH64_SYSREG_PRSELR_EL2, |
| 1447 | ARM64_SYSREG_RCWMASK_EL1 = AARCH64_SYSREG_RCWMASK_EL1, |
| 1448 | ARM64_SYSREG_RCWSMASK_EL1 = AARCH64_SYSREG_RCWSMASK_EL1, |
| 1449 | ARM64_SYSREG_REVIDR_EL1 = AARCH64_SYSREG_REVIDR_EL1, |
| 1450 | ARM64_SYSREG_RGSR_EL1 = AARCH64_SYSREG_RGSR_EL1, |
| 1451 | ARM64_SYSREG_RMR_EL1 = AARCH64_SYSREG_RMR_EL1, |
| 1452 | ARM64_SYSREG_RMR_EL2 = AARCH64_SYSREG_RMR_EL2, |
| 1453 | ARM64_SYSREG_RMR_EL3 = AARCH64_SYSREG_RMR_EL3, |
| 1454 | ARM64_SYSREG_RNDR = AARCH64_SYSREG_RNDR, |
| 1455 | ARM64_SYSREG_RNDRRS = AARCH64_SYSREG_RNDRRS, |
| 1456 | ARM64_SYSREG_RVBAR_EL1 = AARCH64_SYSREG_RVBAR_EL1, |
| 1457 | ARM64_SYSREG_RVBAR_EL2 = AARCH64_SYSREG_RVBAR_EL2, |
| 1458 | ARM64_SYSREG_RVBAR_EL3 = AARCH64_SYSREG_RVBAR_EL3, |
| 1459 | ARM64_SYSREG_S2PIR_EL2 = AARCH64_SYSREG_S2PIR_EL2, |
| 1460 | ARM64_SYSREG_S2POR_EL1 = AARCH64_SYSREG_S2POR_EL1, |
| 1461 | ARM64_SYSREG_SCR_EL3 = AARCH64_SYSREG_SCR_EL3, |
| 1462 | ARM64_SYSREG_SCTLR2_EL1 = AARCH64_SYSREG_SCTLR2_EL1, |
| 1463 | ARM64_SYSREG_SCTLR2_EL12 = AARCH64_SYSREG_SCTLR2_EL12, |
| 1464 | ARM64_SYSREG_SCTLR2_EL2 = AARCH64_SYSREG_SCTLR2_EL2, |
| 1465 | ARM64_SYSREG_SCTLR2_EL3 = AARCH64_SYSREG_SCTLR2_EL3, |
| 1466 | ARM64_SYSREG_SCTLR_EL1 = AARCH64_SYSREG_SCTLR_EL1, |
| 1467 | ARM64_SYSREG_SCTLR_EL12 = AARCH64_SYSREG_SCTLR_EL12, |
| 1468 | ARM64_SYSREG_SCTLR_EL2 = AARCH64_SYSREG_SCTLR_EL2, |
| 1469 | ARM64_SYSREG_SCTLR_EL3 = AARCH64_SYSREG_SCTLR_EL3, |
| 1470 | ARM64_SYSREG_SCXTNUM_EL0 = AARCH64_SYSREG_SCXTNUM_EL0, |
| 1471 | ARM64_SYSREG_SCXTNUM_EL1 = AARCH64_SYSREG_SCXTNUM_EL1, |
| 1472 | ARM64_SYSREG_SCXTNUM_EL12 = AARCH64_SYSREG_SCXTNUM_EL12, |
| 1473 | ARM64_SYSREG_SCXTNUM_EL2 = AARCH64_SYSREG_SCXTNUM_EL2, |
| 1474 | ARM64_SYSREG_SCXTNUM_EL3 = AARCH64_SYSREG_SCXTNUM_EL3, |
| 1475 | ARM64_SYSREG_SDER32_EL2 = AARCH64_SYSREG_SDER32_EL2, |
| 1476 | ARM64_SYSREG_SDER32_EL3 = AARCH64_SYSREG_SDER32_EL3, |
| 1477 | ARM64_SYSREG_SMCR_EL1 = AARCH64_SYSREG_SMCR_EL1, |
| 1478 | ARM64_SYSREG_SMCR_EL12 = AARCH64_SYSREG_SMCR_EL12, |
| 1479 | ARM64_SYSREG_SMCR_EL2 = AARCH64_SYSREG_SMCR_EL2, |
| 1480 | ARM64_SYSREG_SMCR_EL3 = AARCH64_SYSREG_SMCR_EL3, |
| 1481 | ARM64_SYSREG_SMIDR_EL1 = AARCH64_SYSREG_SMIDR_EL1, |
| 1482 | ARM64_SYSREG_SMPRIMAP_EL2 = AARCH64_SYSREG_SMPRIMAP_EL2, |
| 1483 | ARM64_SYSREG_SMPRI_EL1 = AARCH64_SYSREG_SMPRI_EL1, |
| 1484 | ARM64_SYSREG_SPMACCESSR_EL1 = AARCH64_SYSREG_SPMACCESSR_EL1, |
| 1485 | ARM64_SYSREG_SPMACCESSR_EL12 = AARCH64_SYSREG_SPMACCESSR_EL12, |
| 1486 | ARM64_SYSREG_SPMACCESSR_EL2 = AARCH64_SYSREG_SPMACCESSR_EL2, |
| 1487 | ARM64_SYSREG_SPMACCESSR_EL3 = AARCH64_SYSREG_SPMACCESSR_EL3, |
| 1488 | ARM64_SYSREG_SPMCFGR_EL1 = AARCH64_SYSREG_SPMCFGR_EL1, |
| 1489 | ARM64_SYSREG_SPMCGCR0_EL1 = AARCH64_SYSREG_SPMCGCR0_EL1, |
| 1490 | ARM64_SYSREG_SPMCGCR1_EL1 = AARCH64_SYSREG_SPMCGCR1_EL1, |
| 1491 | ARM64_SYSREG_SPMCNTENCLR_EL0 = AARCH64_SYSREG_SPMCNTENCLR_EL0, |
| 1492 | ARM64_SYSREG_SPMCNTENSET_EL0 = AARCH64_SYSREG_SPMCNTENSET_EL0, |
| 1493 | ARM64_SYSREG_SPMCR_EL0 = AARCH64_SYSREG_SPMCR_EL0, |
| 1494 | ARM64_SYSREG_SPMDEVAFF_EL1 = AARCH64_SYSREG_SPMDEVAFF_EL1, |
| 1495 | ARM64_SYSREG_SPMDEVARCH_EL1 = AARCH64_SYSREG_SPMDEVARCH_EL1, |
| 1496 | ARM64_SYSREG_SPMEVCNTR0_EL0 = AARCH64_SYSREG_SPMEVCNTR0_EL0, |
| 1497 | ARM64_SYSREG_SPMEVCNTR10_EL0 = AARCH64_SYSREG_SPMEVCNTR10_EL0, |
| 1498 | ARM64_SYSREG_SPMEVCNTR11_EL0 = AARCH64_SYSREG_SPMEVCNTR11_EL0, |
| 1499 | ARM64_SYSREG_SPMEVCNTR12_EL0 = AARCH64_SYSREG_SPMEVCNTR12_EL0, |
| 1500 | ARM64_SYSREG_SPMEVCNTR13_EL0 = AARCH64_SYSREG_SPMEVCNTR13_EL0, |
| 1501 | ARM64_SYSREG_SPMEVCNTR14_EL0 = AARCH64_SYSREG_SPMEVCNTR14_EL0, |
| 1502 | ARM64_SYSREG_SPMEVCNTR15_EL0 = AARCH64_SYSREG_SPMEVCNTR15_EL0, |
| 1503 | ARM64_SYSREG_SPMEVCNTR1_EL0 = AARCH64_SYSREG_SPMEVCNTR1_EL0, |
| 1504 | ARM64_SYSREG_SPMEVCNTR2_EL0 = AARCH64_SYSREG_SPMEVCNTR2_EL0, |
| 1505 | ARM64_SYSREG_SPMEVCNTR3_EL0 = AARCH64_SYSREG_SPMEVCNTR3_EL0, |
| 1506 | ARM64_SYSREG_SPMEVCNTR4_EL0 = AARCH64_SYSREG_SPMEVCNTR4_EL0, |
| 1507 | ARM64_SYSREG_SPMEVCNTR5_EL0 = AARCH64_SYSREG_SPMEVCNTR5_EL0, |
| 1508 | ARM64_SYSREG_SPMEVCNTR6_EL0 = AARCH64_SYSREG_SPMEVCNTR6_EL0, |
| 1509 | ARM64_SYSREG_SPMEVCNTR7_EL0 = AARCH64_SYSREG_SPMEVCNTR7_EL0, |
| 1510 | ARM64_SYSREG_SPMEVCNTR8_EL0 = AARCH64_SYSREG_SPMEVCNTR8_EL0, |
| 1511 | ARM64_SYSREG_SPMEVCNTR9_EL0 = AARCH64_SYSREG_SPMEVCNTR9_EL0, |
| 1512 | ARM64_SYSREG_SPMEVFILT2R0_EL0 = AARCH64_SYSREG_SPMEVFILT2R0_EL0, |
| 1513 | ARM64_SYSREG_SPMEVFILT2R10_EL0 = AARCH64_SYSREG_SPMEVFILT2R10_EL0, |
| 1514 | ARM64_SYSREG_SPMEVFILT2R11_EL0 = AARCH64_SYSREG_SPMEVFILT2R11_EL0, |
| 1515 | ARM64_SYSREG_SPMEVFILT2R12_EL0 = AARCH64_SYSREG_SPMEVFILT2R12_EL0, |
| 1516 | ARM64_SYSREG_SPMEVFILT2R13_EL0 = AARCH64_SYSREG_SPMEVFILT2R13_EL0, |
| 1517 | ARM64_SYSREG_SPMEVFILT2R14_EL0 = AARCH64_SYSREG_SPMEVFILT2R14_EL0, |
| 1518 | ARM64_SYSREG_SPMEVFILT2R15_EL0 = AARCH64_SYSREG_SPMEVFILT2R15_EL0, |
| 1519 | ARM64_SYSREG_SPMEVFILT2R1_EL0 = AARCH64_SYSREG_SPMEVFILT2R1_EL0, |
| 1520 | ARM64_SYSREG_SPMEVFILT2R2_EL0 = AARCH64_SYSREG_SPMEVFILT2R2_EL0, |
| 1521 | ARM64_SYSREG_SPMEVFILT2R3_EL0 = AARCH64_SYSREG_SPMEVFILT2R3_EL0, |
| 1522 | ARM64_SYSREG_SPMEVFILT2R4_EL0 = AARCH64_SYSREG_SPMEVFILT2R4_EL0, |
| 1523 | ARM64_SYSREG_SPMEVFILT2R5_EL0 = AARCH64_SYSREG_SPMEVFILT2R5_EL0, |
| 1524 | ARM64_SYSREG_SPMEVFILT2R6_EL0 = AARCH64_SYSREG_SPMEVFILT2R6_EL0, |
| 1525 | ARM64_SYSREG_SPMEVFILT2R7_EL0 = AARCH64_SYSREG_SPMEVFILT2R7_EL0, |
| 1526 | ARM64_SYSREG_SPMEVFILT2R8_EL0 = AARCH64_SYSREG_SPMEVFILT2R8_EL0, |
| 1527 | ARM64_SYSREG_SPMEVFILT2R9_EL0 = AARCH64_SYSREG_SPMEVFILT2R9_EL0, |
| 1528 | ARM64_SYSREG_SPMEVFILTR0_EL0 = AARCH64_SYSREG_SPMEVFILTR0_EL0, |
| 1529 | ARM64_SYSREG_SPMEVFILTR10_EL0 = AARCH64_SYSREG_SPMEVFILTR10_EL0, |
| 1530 | ARM64_SYSREG_SPMEVFILTR11_EL0 = AARCH64_SYSREG_SPMEVFILTR11_EL0, |
| 1531 | ARM64_SYSREG_SPMEVFILTR12_EL0 = AARCH64_SYSREG_SPMEVFILTR12_EL0, |
| 1532 | ARM64_SYSREG_SPMEVFILTR13_EL0 = AARCH64_SYSREG_SPMEVFILTR13_EL0, |
| 1533 | ARM64_SYSREG_SPMEVFILTR14_EL0 = AARCH64_SYSREG_SPMEVFILTR14_EL0, |
| 1534 | ARM64_SYSREG_SPMEVFILTR15_EL0 = AARCH64_SYSREG_SPMEVFILTR15_EL0, |
| 1535 | ARM64_SYSREG_SPMEVFILTR1_EL0 = AARCH64_SYSREG_SPMEVFILTR1_EL0, |
| 1536 | ARM64_SYSREG_SPMEVFILTR2_EL0 = AARCH64_SYSREG_SPMEVFILTR2_EL0, |
| 1537 | ARM64_SYSREG_SPMEVFILTR3_EL0 = AARCH64_SYSREG_SPMEVFILTR3_EL0, |
| 1538 | ARM64_SYSREG_SPMEVFILTR4_EL0 = AARCH64_SYSREG_SPMEVFILTR4_EL0, |
| 1539 | ARM64_SYSREG_SPMEVFILTR5_EL0 = AARCH64_SYSREG_SPMEVFILTR5_EL0, |
| 1540 | ARM64_SYSREG_SPMEVFILTR6_EL0 = AARCH64_SYSREG_SPMEVFILTR6_EL0, |
| 1541 | ARM64_SYSREG_SPMEVFILTR7_EL0 = AARCH64_SYSREG_SPMEVFILTR7_EL0, |
| 1542 | ARM64_SYSREG_SPMEVFILTR8_EL0 = AARCH64_SYSREG_SPMEVFILTR8_EL0, |
| 1543 | ARM64_SYSREG_SPMEVFILTR9_EL0 = AARCH64_SYSREG_SPMEVFILTR9_EL0, |
| 1544 | ARM64_SYSREG_SPMEVTYPER0_EL0 = AARCH64_SYSREG_SPMEVTYPER0_EL0, |
| 1545 | ARM64_SYSREG_SPMEVTYPER10_EL0 = AARCH64_SYSREG_SPMEVTYPER10_EL0, |
| 1546 | ARM64_SYSREG_SPMEVTYPER11_EL0 = AARCH64_SYSREG_SPMEVTYPER11_EL0, |
| 1547 | ARM64_SYSREG_SPMEVTYPER12_EL0 = AARCH64_SYSREG_SPMEVTYPER12_EL0, |
| 1548 | ARM64_SYSREG_SPMEVTYPER13_EL0 = AARCH64_SYSREG_SPMEVTYPER13_EL0, |
| 1549 | ARM64_SYSREG_SPMEVTYPER14_EL0 = AARCH64_SYSREG_SPMEVTYPER14_EL0, |
| 1550 | ARM64_SYSREG_SPMEVTYPER15_EL0 = AARCH64_SYSREG_SPMEVTYPER15_EL0, |
| 1551 | ARM64_SYSREG_SPMEVTYPER1_EL0 = AARCH64_SYSREG_SPMEVTYPER1_EL0, |
| 1552 | ARM64_SYSREG_SPMEVTYPER2_EL0 = AARCH64_SYSREG_SPMEVTYPER2_EL0, |
| 1553 | ARM64_SYSREG_SPMEVTYPER3_EL0 = AARCH64_SYSREG_SPMEVTYPER3_EL0, |
| 1554 | ARM64_SYSREG_SPMEVTYPER4_EL0 = AARCH64_SYSREG_SPMEVTYPER4_EL0, |
| 1555 | ARM64_SYSREG_SPMEVTYPER5_EL0 = AARCH64_SYSREG_SPMEVTYPER5_EL0, |
| 1556 | ARM64_SYSREG_SPMEVTYPER6_EL0 = AARCH64_SYSREG_SPMEVTYPER6_EL0, |
| 1557 | ARM64_SYSREG_SPMEVTYPER7_EL0 = AARCH64_SYSREG_SPMEVTYPER7_EL0, |
| 1558 | ARM64_SYSREG_SPMEVTYPER8_EL0 = AARCH64_SYSREG_SPMEVTYPER8_EL0, |
| 1559 | ARM64_SYSREG_SPMEVTYPER9_EL0 = AARCH64_SYSREG_SPMEVTYPER9_EL0, |
| 1560 | ARM64_SYSREG_SPMIIDR_EL1 = AARCH64_SYSREG_SPMIIDR_EL1, |
| 1561 | ARM64_SYSREG_SPMINTENCLR_EL1 = AARCH64_SYSREG_SPMINTENCLR_EL1, |
| 1562 | ARM64_SYSREG_SPMINTENSET_EL1 = AARCH64_SYSREG_SPMINTENSET_EL1, |
| 1563 | ARM64_SYSREG_SPMOVSCLR_EL0 = AARCH64_SYSREG_SPMOVSCLR_EL0, |
| 1564 | ARM64_SYSREG_SPMOVSSET_EL0 = AARCH64_SYSREG_SPMOVSSET_EL0, |
| 1565 | ARM64_SYSREG_SPMROOTCR_EL3 = AARCH64_SYSREG_SPMROOTCR_EL3, |
| 1566 | ARM64_SYSREG_SPMSCR_EL1 = AARCH64_SYSREG_SPMSCR_EL1, |
| 1567 | ARM64_SYSREG_SPMSELR_EL0 = AARCH64_SYSREG_SPMSELR_EL0, |
| 1568 | ARM64_SYSREG_SPMZR_EL0 = AARCH64_SYSREG_SPMZR_EL0, |
| 1569 | ARM64_SYSREG_SPSEL = AARCH64_SYSREG_SPSEL, |
| 1570 | ARM64_SYSREG_SPSR_ABT = AARCH64_SYSREG_SPSR_ABT, |
| 1571 | ARM64_SYSREG_SPSR_EL1 = AARCH64_SYSREG_SPSR_EL1, |
| 1572 | ARM64_SYSREG_SPSR_EL12 = AARCH64_SYSREG_SPSR_EL12, |
| 1573 | ARM64_SYSREG_SPSR_EL2 = AARCH64_SYSREG_SPSR_EL2, |
| 1574 | ARM64_SYSREG_SPSR_EL3 = AARCH64_SYSREG_SPSR_EL3, |
| 1575 | ARM64_SYSREG_SPSR_FIQ = AARCH64_SYSREG_SPSR_FIQ, |
| 1576 | ARM64_SYSREG_SPSR_IRQ = AARCH64_SYSREG_SPSR_IRQ, |
| 1577 | ARM64_SYSREG_SPSR_UND = AARCH64_SYSREG_SPSR_UND, |
| 1578 | ARM64_SYSREG_SP_EL0 = AARCH64_SYSREG_SP_EL0, |
| 1579 | ARM64_SYSREG_SP_EL1 = AARCH64_SYSREG_SP_EL1, |
| 1580 | ARM64_SYSREG_SP_EL2 = AARCH64_SYSREG_SP_EL2, |
| 1581 | ARM64_SYSREG_SSBS = AARCH64_SYSREG_SSBS, |
| 1582 | ARM64_SYSREG_SVCR = AARCH64_SYSREG_SVCR, |
| 1583 | ARM64_SYSREG_TCO = AARCH64_SYSREG_TCO, |
| 1584 | ARM64_SYSREG_TCR2_EL1 = AARCH64_SYSREG_TCR2_EL1, |
| 1585 | ARM64_SYSREG_TCR2_EL12 = AARCH64_SYSREG_TCR2_EL12, |
| 1586 | ARM64_SYSREG_TCR2_EL2 = AARCH64_SYSREG_TCR2_EL2, |
| 1587 | ARM64_SYSREG_TCR_EL1 = AARCH64_SYSREG_TCR_EL1, |
| 1588 | ARM64_SYSREG_TCR_EL12 = AARCH64_SYSREG_TCR_EL12, |
| 1589 | ARM64_SYSREG_TCR_EL2 = AARCH64_SYSREG_TCR_EL2, |
| 1590 | ARM64_SYSREG_TCR_EL3 = AARCH64_SYSREG_TCR_EL3, |
| 1591 | ARM64_SYSREG_TEECR32_EL1 = AARCH64_SYSREG_TEECR32_EL1, |
| 1592 | ARM64_SYSREG_TEEHBR32_EL1 = AARCH64_SYSREG_TEEHBR32_EL1, |
| 1593 | ARM64_SYSREG_TFSRE0_EL1 = AARCH64_SYSREG_TFSRE0_EL1, |
| 1594 | ARM64_SYSREG_TFSR_EL1 = AARCH64_SYSREG_TFSR_EL1, |
| 1595 | ARM64_SYSREG_TFSR_EL12 = AARCH64_SYSREG_TFSR_EL12, |
| 1596 | ARM64_SYSREG_TFSR_EL2 = AARCH64_SYSREG_TFSR_EL2, |
| 1597 | ARM64_SYSREG_TFSR_EL3 = AARCH64_SYSREG_TFSR_EL3, |
| 1598 | ARM64_SYSREG_TPIDR2_EL0 = AARCH64_SYSREG_TPIDR2_EL0, |
| 1599 | ARM64_SYSREG_TPIDRRO_EL0 = AARCH64_SYSREG_TPIDRRO_EL0, |
| 1600 | ARM64_SYSREG_TPIDR_EL0 = AARCH64_SYSREG_TPIDR_EL0, |
| 1601 | ARM64_SYSREG_TPIDR_EL1 = AARCH64_SYSREG_TPIDR_EL1, |
| 1602 | ARM64_SYSREG_TPIDR_EL2 = AARCH64_SYSREG_TPIDR_EL2, |
| 1603 | ARM64_SYSREG_TPIDR_EL3 = AARCH64_SYSREG_TPIDR_EL3, |
| 1604 | ARM64_SYSREG_TRBBASER_EL1 = AARCH64_SYSREG_TRBBASER_EL1, |
| 1605 | ARM64_SYSREG_TRBIDR_EL1 = AARCH64_SYSREG_TRBIDR_EL1, |
| 1606 | ARM64_SYSREG_TRBLIMITR_EL1 = AARCH64_SYSREG_TRBLIMITR_EL1, |
| 1607 | ARM64_SYSREG_TRBMAR_EL1 = AARCH64_SYSREG_TRBMAR_EL1, |
| 1608 | ARM64_SYSREG_TRBPTR_EL1 = AARCH64_SYSREG_TRBPTR_EL1, |
| 1609 | ARM64_SYSREG_TRBSR_EL1 = AARCH64_SYSREG_TRBSR_EL1, |
| 1610 | ARM64_SYSREG_TRBTRG_EL1 = AARCH64_SYSREG_TRBTRG_EL1, |
| 1611 | ARM64_SYSREG_TRCACATR0 = AARCH64_SYSREG_TRCACATR0, |
| 1612 | ARM64_SYSREG_TRCACATR1 = AARCH64_SYSREG_TRCACATR1, |
| 1613 | ARM64_SYSREG_TRCACATR10 = AARCH64_SYSREG_TRCACATR10, |
| 1614 | ARM64_SYSREG_TRCACATR11 = AARCH64_SYSREG_TRCACATR11, |
| 1615 | ARM64_SYSREG_TRCACATR12 = AARCH64_SYSREG_TRCACATR12, |
| 1616 | ARM64_SYSREG_TRCACATR13 = AARCH64_SYSREG_TRCACATR13, |
| 1617 | ARM64_SYSREG_TRCACATR14 = AARCH64_SYSREG_TRCACATR14, |
| 1618 | ARM64_SYSREG_TRCACATR15 = AARCH64_SYSREG_TRCACATR15, |
| 1619 | ARM64_SYSREG_TRCACATR2 = AARCH64_SYSREG_TRCACATR2, |
| 1620 | ARM64_SYSREG_TRCACATR3 = AARCH64_SYSREG_TRCACATR3, |
| 1621 | ARM64_SYSREG_TRCACATR4 = AARCH64_SYSREG_TRCACATR4, |
| 1622 | ARM64_SYSREG_TRCACATR5 = AARCH64_SYSREG_TRCACATR5, |
| 1623 | ARM64_SYSREG_TRCACATR6 = AARCH64_SYSREG_TRCACATR6, |
| 1624 | ARM64_SYSREG_TRCACATR7 = AARCH64_SYSREG_TRCACATR7, |
| 1625 | ARM64_SYSREG_TRCACATR8 = AARCH64_SYSREG_TRCACATR8, |
| 1626 | ARM64_SYSREG_TRCACATR9 = AARCH64_SYSREG_TRCACATR9, |
| 1627 | ARM64_SYSREG_TRCACVR0 = AARCH64_SYSREG_TRCACVR0, |
| 1628 | ARM64_SYSREG_TRCACVR1 = AARCH64_SYSREG_TRCACVR1, |
| 1629 | ARM64_SYSREG_TRCACVR10 = AARCH64_SYSREG_TRCACVR10, |
| 1630 | ARM64_SYSREG_TRCACVR11 = AARCH64_SYSREG_TRCACVR11, |
| 1631 | ARM64_SYSREG_TRCACVR12 = AARCH64_SYSREG_TRCACVR12, |
| 1632 | ARM64_SYSREG_TRCACVR13 = AARCH64_SYSREG_TRCACVR13, |
| 1633 | ARM64_SYSREG_TRCACVR14 = AARCH64_SYSREG_TRCACVR14, |
| 1634 | ARM64_SYSREG_TRCACVR15 = AARCH64_SYSREG_TRCACVR15, |
| 1635 | ARM64_SYSREG_TRCACVR2 = AARCH64_SYSREG_TRCACVR2, |
| 1636 | ARM64_SYSREG_TRCACVR3 = AARCH64_SYSREG_TRCACVR3, |
| 1637 | ARM64_SYSREG_TRCACVR4 = AARCH64_SYSREG_TRCACVR4, |
| 1638 | ARM64_SYSREG_TRCACVR5 = AARCH64_SYSREG_TRCACVR5, |
| 1639 | ARM64_SYSREG_TRCACVR6 = AARCH64_SYSREG_TRCACVR6, |
| 1640 | ARM64_SYSREG_TRCACVR7 = AARCH64_SYSREG_TRCACVR7, |
| 1641 | ARM64_SYSREG_TRCACVR8 = AARCH64_SYSREG_TRCACVR8, |
| 1642 | ARM64_SYSREG_TRCACVR9 = AARCH64_SYSREG_TRCACVR9, |
| 1643 | ARM64_SYSREG_TRCAUTHSTATUS = AARCH64_SYSREG_TRCAUTHSTATUS, |
| 1644 | ARM64_SYSREG_TRCAUXCTLR = AARCH64_SYSREG_TRCAUXCTLR, |
| 1645 | ARM64_SYSREG_TRCBBCTLR = AARCH64_SYSREG_TRCBBCTLR, |
| 1646 | ARM64_SYSREG_TRCCCCTLR = AARCH64_SYSREG_TRCCCCTLR, |
| 1647 | ARM64_SYSREG_TRCCIDCCTLR0 = AARCH64_SYSREG_TRCCIDCCTLR0, |
| 1648 | ARM64_SYSREG_TRCCIDCCTLR1 = AARCH64_SYSREG_TRCCIDCCTLR1, |
| 1649 | ARM64_SYSREG_TRCCIDCVR0 = AARCH64_SYSREG_TRCCIDCVR0, |
| 1650 | ARM64_SYSREG_TRCCIDCVR1 = AARCH64_SYSREG_TRCCIDCVR1, |
| 1651 | ARM64_SYSREG_TRCCIDCVR2 = AARCH64_SYSREG_TRCCIDCVR2, |
| 1652 | ARM64_SYSREG_TRCCIDCVR3 = AARCH64_SYSREG_TRCCIDCVR3, |
| 1653 | ARM64_SYSREG_TRCCIDCVR4 = AARCH64_SYSREG_TRCCIDCVR4, |
| 1654 | ARM64_SYSREG_TRCCIDCVR5 = AARCH64_SYSREG_TRCCIDCVR5, |
| 1655 | ARM64_SYSREG_TRCCIDCVR6 = AARCH64_SYSREG_TRCCIDCVR6, |
| 1656 | ARM64_SYSREG_TRCCIDCVR7 = AARCH64_SYSREG_TRCCIDCVR7, |
| 1657 | ARM64_SYSREG_TRCCIDR0 = AARCH64_SYSREG_TRCCIDR0, |
| 1658 | ARM64_SYSREG_TRCCIDR1 = AARCH64_SYSREG_TRCCIDR1, |
| 1659 | ARM64_SYSREG_TRCCIDR2 = AARCH64_SYSREG_TRCCIDR2, |
| 1660 | ARM64_SYSREG_TRCCIDR3 = AARCH64_SYSREG_TRCCIDR3, |
| 1661 | ARM64_SYSREG_TRCCLAIMCLR = AARCH64_SYSREG_TRCCLAIMCLR, |
| 1662 | ARM64_SYSREG_TRCCLAIMSET = AARCH64_SYSREG_TRCCLAIMSET, |
| 1663 | ARM64_SYSREG_TRCCNTCTLR0 = AARCH64_SYSREG_TRCCNTCTLR0, |
| 1664 | ARM64_SYSREG_TRCCNTCTLR1 = AARCH64_SYSREG_TRCCNTCTLR1, |
| 1665 | ARM64_SYSREG_TRCCNTCTLR2 = AARCH64_SYSREG_TRCCNTCTLR2, |
| 1666 | ARM64_SYSREG_TRCCNTCTLR3 = AARCH64_SYSREG_TRCCNTCTLR3, |
| 1667 | ARM64_SYSREG_TRCCNTRLDVR0 = AARCH64_SYSREG_TRCCNTRLDVR0, |
| 1668 | ARM64_SYSREG_TRCCNTRLDVR1 = AARCH64_SYSREG_TRCCNTRLDVR1, |
| 1669 | ARM64_SYSREG_TRCCNTRLDVR2 = AARCH64_SYSREG_TRCCNTRLDVR2, |
| 1670 | ARM64_SYSREG_TRCCNTRLDVR3 = AARCH64_SYSREG_TRCCNTRLDVR3, |
| 1671 | ARM64_SYSREG_TRCCNTVR0 = AARCH64_SYSREG_TRCCNTVR0, |
| 1672 | ARM64_SYSREG_TRCCNTVR1 = AARCH64_SYSREG_TRCCNTVR1, |
| 1673 | ARM64_SYSREG_TRCCNTVR2 = AARCH64_SYSREG_TRCCNTVR2, |
| 1674 | ARM64_SYSREG_TRCCNTVR3 = AARCH64_SYSREG_TRCCNTVR3, |
| 1675 | ARM64_SYSREG_TRCCONFIGR = AARCH64_SYSREG_TRCCONFIGR, |
| 1676 | ARM64_SYSREG_TRCDEVAFF0 = AARCH64_SYSREG_TRCDEVAFF0, |
| 1677 | ARM64_SYSREG_TRCDEVAFF1 = AARCH64_SYSREG_TRCDEVAFF1, |
| 1678 | ARM64_SYSREG_TRCDEVARCH = AARCH64_SYSREG_TRCDEVARCH, |
| 1679 | ARM64_SYSREG_TRCDEVID = AARCH64_SYSREG_TRCDEVID, |
| 1680 | ARM64_SYSREG_TRCDEVTYPE = AARCH64_SYSREG_TRCDEVTYPE, |
| 1681 | ARM64_SYSREG_TRCDVCMR0 = AARCH64_SYSREG_TRCDVCMR0, |
| 1682 | ARM64_SYSREG_TRCDVCMR1 = AARCH64_SYSREG_TRCDVCMR1, |
| 1683 | ARM64_SYSREG_TRCDVCMR2 = AARCH64_SYSREG_TRCDVCMR2, |
| 1684 | ARM64_SYSREG_TRCDVCMR3 = AARCH64_SYSREG_TRCDVCMR3, |
| 1685 | ARM64_SYSREG_TRCDVCMR4 = AARCH64_SYSREG_TRCDVCMR4, |
| 1686 | ARM64_SYSREG_TRCDVCMR5 = AARCH64_SYSREG_TRCDVCMR5, |
| 1687 | ARM64_SYSREG_TRCDVCMR6 = AARCH64_SYSREG_TRCDVCMR6, |
| 1688 | ARM64_SYSREG_TRCDVCMR7 = AARCH64_SYSREG_TRCDVCMR7, |
| 1689 | ARM64_SYSREG_TRCDVCVR0 = AARCH64_SYSREG_TRCDVCVR0, |
| 1690 | ARM64_SYSREG_TRCDVCVR1 = AARCH64_SYSREG_TRCDVCVR1, |
| 1691 | ARM64_SYSREG_TRCDVCVR2 = AARCH64_SYSREG_TRCDVCVR2, |
| 1692 | ARM64_SYSREG_TRCDVCVR3 = AARCH64_SYSREG_TRCDVCVR3, |
| 1693 | ARM64_SYSREG_TRCDVCVR4 = AARCH64_SYSREG_TRCDVCVR4, |
| 1694 | ARM64_SYSREG_TRCDVCVR5 = AARCH64_SYSREG_TRCDVCVR5, |
| 1695 | ARM64_SYSREG_TRCDVCVR6 = AARCH64_SYSREG_TRCDVCVR6, |
| 1696 | ARM64_SYSREG_TRCDVCVR7 = AARCH64_SYSREG_TRCDVCVR7, |
| 1697 | ARM64_SYSREG_TRCEVENTCTL0R = AARCH64_SYSREG_TRCEVENTCTL0R, |
| 1698 | ARM64_SYSREG_TRCEVENTCTL1R = AARCH64_SYSREG_TRCEVENTCTL1R, |
| 1699 | ARM64_SYSREG_TRCEXTINSELR = AARCH64_SYSREG_TRCEXTINSELR, |
| 1700 | ARM64_SYSREG_TRCEXTINSELR0 = AARCH64_SYSREG_TRCEXTINSELR0, |
| 1701 | ARM64_SYSREG_TRCEXTINSELR1 = AARCH64_SYSREG_TRCEXTINSELR1, |
| 1702 | ARM64_SYSREG_TRCEXTINSELR2 = AARCH64_SYSREG_TRCEXTINSELR2, |
| 1703 | ARM64_SYSREG_TRCEXTINSELR3 = AARCH64_SYSREG_TRCEXTINSELR3, |
| 1704 | ARM64_SYSREG_TRCIDR0 = AARCH64_SYSREG_TRCIDR0, |
| 1705 | ARM64_SYSREG_TRCIDR1 = AARCH64_SYSREG_TRCIDR1, |
| 1706 | ARM64_SYSREG_TRCIDR10 = AARCH64_SYSREG_TRCIDR10, |
| 1707 | ARM64_SYSREG_TRCIDR11 = AARCH64_SYSREG_TRCIDR11, |
| 1708 | ARM64_SYSREG_TRCIDR12 = AARCH64_SYSREG_TRCIDR12, |
| 1709 | ARM64_SYSREG_TRCIDR13 = AARCH64_SYSREG_TRCIDR13, |
| 1710 | ARM64_SYSREG_TRCIDR2 = AARCH64_SYSREG_TRCIDR2, |
| 1711 | ARM64_SYSREG_TRCIDR3 = AARCH64_SYSREG_TRCIDR3, |
| 1712 | ARM64_SYSREG_TRCIDR4 = AARCH64_SYSREG_TRCIDR4, |
| 1713 | ARM64_SYSREG_TRCIDR5 = AARCH64_SYSREG_TRCIDR5, |
| 1714 | ARM64_SYSREG_TRCIDR6 = AARCH64_SYSREG_TRCIDR6, |
| 1715 | ARM64_SYSREG_TRCIDR7 = AARCH64_SYSREG_TRCIDR7, |
| 1716 | ARM64_SYSREG_TRCIDR8 = AARCH64_SYSREG_TRCIDR8, |
| 1717 | ARM64_SYSREG_TRCIDR9 = AARCH64_SYSREG_TRCIDR9, |
| 1718 | ARM64_SYSREG_TRCIMSPEC0 = AARCH64_SYSREG_TRCIMSPEC0, |
| 1719 | ARM64_SYSREG_TRCIMSPEC1 = AARCH64_SYSREG_TRCIMSPEC1, |
| 1720 | ARM64_SYSREG_TRCIMSPEC2 = AARCH64_SYSREG_TRCIMSPEC2, |
| 1721 | ARM64_SYSREG_TRCIMSPEC3 = AARCH64_SYSREG_TRCIMSPEC3, |
| 1722 | ARM64_SYSREG_TRCIMSPEC4 = AARCH64_SYSREG_TRCIMSPEC4, |
| 1723 | ARM64_SYSREG_TRCIMSPEC5 = AARCH64_SYSREG_TRCIMSPEC5, |
| 1724 | ARM64_SYSREG_TRCIMSPEC6 = AARCH64_SYSREG_TRCIMSPEC6, |
| 1725 | ARM64_SYSREG_TRCIMSPEC7 = AARCH64_SYSREG_TRCIMSPEC7, |
| 1726 | ARM64_SYSREG_TRCITCTRL = AARCH64_SYSREG_TRCITCTRL, |
| 1727 | ARM64_SYSREG_TRCITECR_EL1 = AARCH64_SYSREG_TRCITECR_EL1, |
| 1728 | ARM64_SYSREG_TRCITECR_EL12 = AARCH64_SYSREG_TRCITECR_EL12, |
| 1729 | ARM64_SYSREG_TRCITECR_EL2 = AARCH64_SYSREG_TRCITECR_EL2, |
| 1730 | ARM64_SYSREG_TRCITEEDCR = AARCH64_SYSREG_TRCITEEDCR, |
| 1731 | ARM64_SYSREG_TRCLAR = AARCH64_SYSREG_TRCLAR, |
| 1732 | ARM64_SYSREG_TRCLSR = AARCH64_SYSREG_TRCLSR, |
| 1733 | ARM64_SYSREG_TRCOSLAR = AARCH64_SYSREG_TRCOSLAR, |
| 1734 | ARM64_SYSREG_TRCOSLSR = AARCH64_SYSREG_TRCOSLSR, |
| 1735 | ARM64_SYSREG_TRCPDCR = AARCH64_SYSREG_TRCPDCR, |
| 1736 | ARM64_SYSREG_TRCPDSR = AARCH64_SYSREG_TRCPDSR, |
| 1737 | ARM64_SYSREG_TRCPIDR0 = AARCH64_SYSREG_TRCPIDR0, |
| 1738 | ARM64_SYSREG_TRCPIDR1 = AARCH64_SYSREG_TRCPIDR1, |
| 1739 | ARM64_SYSREG_TRCPIDR2 = AARCH64_SYSREG_TRCPIDR2, |
| 1740 | ARM64_SYSREG_TRCPIDR3 = AARCH64_SYSREG_TRCPIDR3, |
| 1741 | ARM64_SYSREG_TRCPIDR4 = AARCH64_SYSREG_TRCPIDR4, |
| 1742 | ARM64_SYSREG_TRCPIDR5 = AARCH64_SYSREG_TRCPIDR5, |
| 1743 | ARM64_SYSREG_TRCPIDR6 = AARCH64_SYSREG_TRCPIDR6, |
| 1744 | ARM64_SYSREG_TRCPIDR7 = AARCH64_SYSREG_TRCPIDR7, |
| 1745 | ARM64_SYSREG_TRCPRGCTLR = AARCH64_SYSREG_TRCPRGCTLR, |
| 1746 | ARM64_SYSREG_TRCPROCSELR = AARCH64_SYSREG_TRCPROCSELR, |
| 1747 | ARM64_SYSREG_TRCQCTLR = AARCH64_SYSREG_TRCQCTLR, |
| 1748 | ARM64_SYSREG_TRCRSCTLR10 = AARCH64_SYSREG_TRCRSCTLR10, |
| 1749 | ARM64_SYSREG_TRCRSCTLR11 = AARCH64_SYSREG_TRCRSCTLR11, |
| 1750 | ARM64_SYSREG_TRCRSCTLR12 = AARCH64_SYSREG_TRCRSCTLR12, |
| 1751 | ARM64_SYSREG_TRCRSCTLR13 = AARCH64_SYSREG_TRCRSCTLR13, |
| 1752 | ARM64_SYSREG_TRCRSCTLR14 = AARCH64_SYSREG_TRCRSCTLR14, |
| 1753 | ARM64_SYSREG_TRCRSCTLR15 = AARCH64_SYSREG_TRCRSCTLR15, |
| 1754 | ARM64_SYSREG_TRCRSCTLR16 = AARCH64_SYSREG_TRCRSCTLR16, |
| 1755 | ARM64_SYSREG_TRCRSCTLR17 = AARCH64_SYSREG_TRCRSCTLR17, |
| 1756 | ARM64_SYSREG_TRCRSCTLR18 = AARCH64_SYSREG_TRCRSCTLR18, |
| 1757 | ARM64_SYSREG_TRCRSCTLR19 = AARCH64_SYSREG_TRCRSCTLR19, |
| 1758 | ARM64_SYSREG_TRCRSCTLR2 = AARCH64_SYSREG_TRCRSCTLR2, |
| 1759 | ARM64_SYSREG_TRCRSCTLR20 = AARCH64_SYSREG_TRCRSCTLR20, |
| 1760 | ARM64_SYSREG_TRCRSCTLR21 = AARCH64_SYSREG_TRCRSCTLR21, |
| 1761 | ARM64_SYSREG_TRCRSCTLR22 = AARCH64_SYSREG_TRCRSCTLR22, |
| 1762 | ARM64_SYSREG_TRCRSCTLR23 = AARCH64_SYSREG_TRCRSCTLR23, |
| 1763 | ARM64_SYSREG_TRCRSCTLR24 = AARCH64_SYSREG_TRCRSCTLR24, |
| 1764 | ARM64_SYSREG_TRCRSCTLR25 = AARCH64_SYSREG_TRCRSCTLR25, |
| 1765 | ARM64_SYSREG_TRCRSCTLR26 = AARCH64_SYSREG_TRCRSCTLR26, |
| 1766 | ARM64_SYSREG_TRCRSCTLR27 = AARCH64_SYSREG_TRCRSCTLR27, |
| 1767 | ARM64_SYSREG_TRCRSCTLR28 = AARCH64_SYSREG_TRCRSCTLR28, |
| 1768 | ARM64_SYSREG_TRCRSCTLR29 = AARCH64_SYSREG_TRCRSCTLR29, |
| 1769 | ARM64_SYSREG_TRCRSCTLR3 = AARCH64_SYSREG_TRCRSCTLR3, |
| 1770 | ARM64_SYSREG_TRCRSCTLR30 = AARCH64_SYSREG_TRCRSCTLR30, |
| 1771 | ARM64_SYSREG_TRCRSCTLR31 = AARCH64_SYSREG_TRCRSCTLR31, |
| 1772 | ARM64_SYSREG_TRCRSCTLR4 = AARCH64_SYSREG_TRCRSCTLR4, |
| 1773 | ARM64_SYSREG_TRCRSCTLR5 = AARCH64_SYSREG_TRCRSCTLR5, |
| 1774 | ARM64_SYSREG_TRCRSCTLR6 = AARCH64_SYSREG_TRCRSCTLR6, |
| 1775 | ARM64_SYSREG_TRCRSCTLR7 = AARCH64_SYSREG_TRCRSCTLR7, |
| 1776 | ARM64_SYSREG_TRCRSCTLR8 = AARCH64_SYSREG_TRCRSCTLR8, |
| 1777 | ARM64_SYSREG_TRCRSCTLR9 = AARCH64_SYSREG_TRCRSCTLR9, |
| 1778 | ARM64_SYSREG_TRCRSR = AARCH64_SYSREG_TRCRSR, |
| 1779 | ARM64_SYSREG_TRCSEQEVR0 = AARCH64_SYSREG_TRCSEQEVR0, |
| 1780 | ARM64_SYSREG_TRCSEQEVR1 = AARCH64_SYSREG_TRCSEQEVR1, |
| 1781 | ARM64_SYSREG_TRCSEQEVR2 = AARCH64_SYSREG_TRCSEQEVR2, |
| 1782 | ARM64_SYSREG_TRCSEQRSTEVR = AARCH64_SYSREG_TRCSEQRSTEVR, |
| 1783 | ARM64_SYSREG_TRCSEQSTR = AARCH64_SYSREG_TRCSEQSTR, |
| 1784 | ARM64_SYSREG_TRCSSCCR0 = AARCH64_SYSREG_TRCSSCCR0, |
| 1785 | ARM64_SYSREG_TRCSSCCR1 = AARCH64_SYSREG_TRCSSCCR1, |
| 1786 | ARM64_SYSREG_TRCSSCCR2 = AARCH64_SYSREG_TRCSSCCR2, |
| 1787 | ARM64_SYSREG_TRCSSCCR3 = AARCH64_SYSREG_TRCSSCCR3, |
| 1788 | ARM64_SYSREG_TRCSSCCR4 = AARCH64_SYSREG_TRCSSCCR4, |
| 1789 | ARM64_SYSREG_TRCSSCCR5 = AARCH64_SYSREG_TRCSSCCR5, |
| 1790 | ARM64_SYSREG_TRCSSCCR6 = AARCH64_SYSREG_TRCSSCCR6, |
| 1791 | ARM64_SYSREG_TRCSSCCR7 = AARCH64_SYSREG_TRCSSCCR7, |
| 1792 | ARM64_SYSREG_TRCSSCSR0 = AARCH64_SYSREG_TRCSSCSR0, |
| 1793 | ARM64_SYSREG_TRCSSCSR1 = AARCH64_SYSREG_TRCSSCSR1, |
| 1794 | ARM64_SYSREG_TRCSSCSR2 = AARCH64_SYSREG_TRCSSCSR2, |
| 1795 | ARM64_SYSREG_TRCSSCSR3 = AARCH64_SYSREG_TRCSSCSR3, |
| 1796 | ARM64_SYSREG_TRCSSCSR4 = AARCH64_SYSREG_TRCSSCSR4, |
| 1797 | ARM64_SYSREG_TRCSSCSR5 = AARCH64_SYSREG_TRCSSCSR5, |
| 1798 | ARM64_SYSREG_TRCSSCSR6 = AARCH64_SYSREG_TRCSSCSR6, |
| 1799 | ARM64_SYSREG_TRCSSCSR7 = AARCH64_SYSREG_TRCSSCSR7, |
| 1800 | ARM64_SYSREG_TRCSSPCICR0 = AARCH64_SYSREG_TRCSSPCICR0, |
| 1801 | ARM64_SYSREG_TRCSSPCICR1 = AARCH64_SYSREG_TRCSSPCICR1, |
| 1802 | ARM64_SYSREG_TRCSSPCICR2 = AARCH64_SYSREG_TRCSSPCICR2, |
| 1803 | ARM64_SYSREG_TRCSSPCICR3 = AARCH64_SYSREG_TRCSSPCICR3, |
| 1804 | ARM64_SYSREG_TRCSSPCICR4 = AARCH64_SYSREG_TRCSSPCICR4, |
| 1805 | ARM64_SYSREG_TRCSSPCICR5 = AARCH64_SYSREG_TRCSSPCICR5, |
| 1806 | ARM64_SYSREG_TRCSSPCICR6 = AARCH64_SYSREG_TRCSSPCICR6, |
| 1807 | ARM64_SYSREG_TRCSSPCICR7 = AARCH64_SYSREG_TRCSSPCICR7, |
| 1808 | ARM64_SYSREG_TRCSTALLCTLR = AARCH64_SYSREG_TRCSTALLCTLR, |
| 1809 | ARM64_SYSREG_TRCSTATR = AARCH64_SYSREG_TRCSTATR, |
| 1810 | ARM64_SYSREG_TRCSYNCPR = AARCH64_SYSREG_TRCSYNCPR, |
| 1811 | ARM64_SYSREG_TRCTRACEIDR = AARCH64_SYSREG_TRCTRACEIDR, |
| 1812 | ARM64_SYSREG_TRCTSCTLR = AARCH64_SYSREG_TRCTSCTLR, |
| 1813 | ARM64_SYSREG_TRCVDARCCTLR = AARCH64_SYSREG_TRCVDARCCTLR, |
| 1814 | ARM64_SYSREG_TRCVDCTLR = AARCH64_SYSREG_TRCVDCTLR, |
| 1815 | ARM64_SYSREG_TRCVDSACCTLR = AARCH64_SYSREG_TRCVDSACCTLR, |
| 1816 | ARM64_SYSREG_TRCVICTLR = AARCH64_SYSREG_TRCVICTLR, |
| 1817 | ARM64_SYSREG_TRCVIIECTLR = AARCH64_SYSREG_TRCVIIECTLR, |
| 1818 | ARM64_SYSREG_TRCVIPCSSCTLR = AARCH64_SYSREG_TRCVIPCSSCTLR, |
| 1819 | ARM64_SYSREG_TRCVISSCTLR = AARCH64_SYSREG_TRCVISSCTLR, |
| 1820 | ARM64_SYSREG_TRCVMIDCCTLR0 = AARCH64_SYSREG_TRCVMIDCCTLR0, |
| 1821 | ARM64_SYSREG_TRCVMIDCCTLR1 = AARCH64_SYSREG_TRCVMIDCCTLR1, |
| 1822 | ARM64_SYSREG_TRCVMIDCVR0 = AARCH64_SYSREG_TRCVMIDCVR0, |
| 1823 | ARM64_SYSREG_TRCVMIDCVR1 = AARCH64_SYSREG_TRCVMIDCVR1, |
| 1824 | ARM64_SYSREG_TRCVMIDCVR2 = AARCH64_SYSREG_TRCVMIDCVR2, |
| 1825 | ARM64_SYSREG_TRCVMIDCVR3 = AARCH64_SYSREG_TRCVMIDCVR3, |
| 1826 | ARM64_SYSREG_TRCVMIDCVR4 = AARCH64_SYSREG_TRCVMIDCVR4, |
| 1827 | ARM64_SYSREG_TRCVMIDCVR5 = AARCH64_SYSREG_TRCVMIDCVR5, |
| 1828 | ARM64_SYSREG_TRCVMIDCVR6 = AARCH64_SYSREG_TRCVMIDCVR6, |
| 1829 | ARM64_SYSREG_TRCVMIDCVR7 = AARCH64_SYSREG_TRCVMIDCVR7, |
| 1830 | ARM64_SYSREG_TRFCR_EL1 = AARCH64_SYSREG_TRFCR_EL1, |
| 1831 | ARM64_SYSREG_TRFCR_EL12 = AARCH64_SYSREG_TRFCR_EL12, |
| 1832 | ARM64_SYSREG_TRFCR_EL2 = AARCH64_SYSREG_TRFCR_EL2, |
| 1833 | ARM64_SYSREG_TTBR0_EL1 = AARCH64_SYSREG_TTBR0_EL1, |
| 1834 | ARM64_SYSREG_TTBR0_EL12 = AARCH64_SYSREG_TTBR0_EL12, |
| 1835 | ARM64_SYSREG_TTBR0_EL2 = AARCH64_SYSREG_TTBR0_EL2, |
| 1836 | ARM64_SYSREG_VSCTLR_EL2 = AARCH64_SYSREG_VSCTLR_EL2, |
| 1837 | ARM64_SYSREG_TTBR0_EL3 = AARCH64_SYSREG_TTBR0_EL3, |
| 1838 | ARM64_SYSREG_TTBR1_EL1 = AARCH64_SYSREG_TTBR1_EL1, |
| 1839 | ARM64_SYSREG_TTBR1_EL12 = AARCH64_SYSREG_TTBR1_EL12, |
| 1840 | ARM64_SYSREG_TTBR1_EL2 = AARCH64_SYSREG_TTBR1_EL2, |
| 1841 | ARM64_SYSREG_UAO = AARCH64_SYSREG_UAO, |
| 1842 | ARM64_SYSREG_VBAR_EL1 = AARCH64_SYSREG_VBAR_EL1, |
| 1843 | ARM64_SYSREG_VBAR_EL12 = AARCH64_SYSREG_VBAR_EL12, |
| 1844 | ARM64_SYSREG_VBAR_EL2 = AARCH64_SYSREG_VBAR_EL2, |
| 1845 | ARM64_SYSREG_VBAR_EL3 = AARCH64_SYSREG_VBAR_EL3, |
| 1846 | ARM64_SYSREG_VDISR_EL2 = AARCH64_SYSREG_VDISR_EL2, |
| 1847 | ARM64_SYSREG_VDISR_EL3 = AARCH64_SYSREG_VDISR_EL3, |
| 1848 | ARM64_SYSREG_VMECID_A_EL2 = AARCH64_SYSREG_VMECID_A_EL2, |
| 1849 | ARM64_SYSREG_VMECID_P_EL2 = AARCH64_SYSREG_VMECID_P_EL2, |
| 1850 | ARM64_SYSREG_VMPIDR_EL2 = AARCH64_SYSREG_VMPIDR_EL2, |
| 1851 | ARM64_SYSREG_VNCR_EL2 = AARCH64_SYSREG_VNCR_EL2, |
| 1852 | ARM64_SYSREG_VPIDR_EL2 = AARCH64_SYSREG_VPIDR_EL2, |
| 1853 | ARM64_SYSREG_VSESR_EL2 = AARCH64_SYSREG_VSESR_EL2, |
| 1854 | ARM64_SYSREG_VSESR_EL3 = AARCH64_SYSREG_VSESR_EL3, |
| 1855 | ARM64_SYSREG_VSTCR_EL2 = AARCH64_SYSREG_VSTCR_EL2, |
| 1856 | ARM64_SYSREG_VSTTBR_EL2 = AARCH64_SYSREG_VSTTBR_EL2, |
| 1857 | ARM64_SYSREG_VTCR_EL2 = AARCH64_SYSREG_VTCR_EL2, |
| 1858 | ARM64_SYSREG_VTTBR_EL2 = AARCH64_SYSREG_VTTBR_EL2, |
| 1859 | ARM64_SYSREG_ZCR_EL1 = AARCH64_SYSREG_ZCR_EL1, |
| 1860 | ARM64_SYSREG_ZCR_EL12 = AARCH64_SYSREG_ZCR_EL12, |
| 1861 | ARM64_SYSREG_ZCR_EL2 = AARCH64_SYSREG_ZCR_EL2, |
| 1862 | ARM64_SYSREG_ZCR_EL3 = AARCH64_SYSREG_ZCR_EL3, |
| 1863 | |
| 1864 | ARM64_SYSREG_ENDING = AARCH64_SYSREG_ENDING, |
| 1865 | } arm64_sysreg; |
| 1866 | |
| 1867 | typedef enum { |
| 1868 | |
| 1869 | ARM64_TSB_CSYNC = AARCH64_TSB_CSYNC, |
| 1870 | |
| 1871 | ARM64_TSB_ENDING = AARCH64_TSB_ENDING, |
| 1872 | } arm64_tsb; |
| 1873 | |
| 1874 | typedef aarch64_sysop_reg arm64_sysop_reg; |
| 1875 | |
| 1876 | typedef aarch64_sysop_imm arm64_sysop_imm; |
| 1877 | |
| 1878 | typedef aarch64_sysop_alias arm64_sysop_alias; |
| 1879 | |
| 1880 | typedef enum { |
| 1881 | ARM64_OP_INVALID = AARCH64_OP_INVALID, |
| 1882 | ARM64_OP_REG = AARCH64_OP_REG, |
| 1883 | ARM64_OP_IMM = AARCH64_OP_IMM, |
| 1884 | ARM64_OP_MEM_REG = AARCH64_OP_MEM_REG, |
| 1885 | ARM64_OP_MEM_IMM = AARCH64_OP_MEM_IMM, |
| 1886 | ARM64_OP_MEM = AARCH64_OP_MEM, |
| 1887 | ARM64_OP_FP = AARCH64_OP_FP, |
| 1888 | ARM64_OP_CIMM = AARCH64_OP_CIMM, |
| 1889 | ARM64_OP_REG_MRS = AARCH64_OP_REG_MRS, |
| 1890 | ARM64_OP_REG_MSR = AARCH64_OP_REG_MSR, |
| 1891 | ARM64_OP_IMPLICIT_IMM_0 = AARCH64_OP_IMPLICIT_IMM_0, |
| 1892 | ARM64_OP_SVCR = AARCH64_OP_SVCR, |
| 1893 | ARM64_OP_AT = AARCH64_OP_AT, |
| 1894 | ARM64_OP_DB = AARCH64_OP_DB, |
| 1895 | ARM64_OP_DC = AARCH64_OP_DC, |
| 1896 | ARM64_OP_ISB = AARCH64_OP_ISB, |
| 1897 | ARM64_OP_TSB = AARCH64_OP_TSB, |
| 1898 | ARM64_OP_PRFM = AARCH64_OP_PRFM, |
| 1899 | ARM64_OP_SVEPRFM = AARCH64_OP_SVEPRFM, |
| 1900 | ARM64_OP_RPRFM = AARCH64_OP_RPRFM, |
| 1901 | ARM64_OP_PSTATEIMM0_15 = AARCH64_OP_PSTATEIMM0_15, |
| 1902 | ARM64_OP_PSTATEIMM0_1 = AARCH64_OP_PSTATEIMM0_1, |
| 1903 | ARM64_OP_PSB = AARCH64_OP_PSB, |
| 1904 | ARM64_OP_BTI = AARCH64_OP_BTI, |
| 1905 | ARM64_OP_SVEPREDPAT = AARCH64_OP_SVEPREDPAT, |
| 1906 | ARM64_OP_SVEVECLENSPECIFIER = AARCH64_OP_SVEVECLENSPECIFIER, |
| 1907 | ARM64_OP_SME = AARCH64_OP_SME, |
| 1908 | ARM64_OP_IMM_RANGE = AARCH64_OP_IMM_RANGE, |
| 1909 | ARM64_OP_TLBI = AARCH64_OP_TLBI, |
| 1910 | ARM64_OP_IC = AARCH64_OP_IC, |
| 1911 | ARM64_OP_DBNXS = AARCH64_OP_DBNXS, |
| 1912 | ARM64_OP_EXACTFPIMM = AARCH64_OP_EXACTFPIMM, |
| 1913 | ARM64_OP_SYSREG = AARCH64_OP_SYSREG, |
| 1914 | ARM64_OP_SYSIMM = AARCH64_OP_SYSIMM, |
| 1915 | ARM64_OP_SYSALIAS = AARCH64_OP_SYSALIAS, |
| 1916 | ARM64_OP_PRED = AARCH64_OP_PRED, |
| 1917 | } arm64_op_type; |
| 1918 | |
| 1919 | typedef aarch64_sysop arm64_sysop; |
| 1920 | |
| 1921 | typedef enum { |
| 1922 | |
| 1923 | ARM64_REG_INVALID = AARCH64_REG_INVALID, |
| 1924 | ARM64_REG_FFR = AARCH64_REG_FFR, |
| 1925 | ARM64_REG_FP = AARCH64_REG_FP, |
| 1926 | ARM64_REG_FPCR = AARCH64_REG_FPCR, |
| 1927 | ARM64_REG_LR = AARCH64_REG_LR, |
| 1928 | ARM64_REG_NZCV = AARCH64_REG_NZCV, |
| 1929 | ARM64_REG_SP = AARCH64_REG_SP, |
| 1930 | ARM64_REG_VG = AARCH64_REG_VG, |
| 1931 | ARM64_REG_WSP = AARCH64_REG_WSP, |
| 1932 | ARM64_REG_WZR = AARCH64_REG_WZR, |
| 1933 | ARM64_REG_XZR = AARCH64_REG_XZR, |
| 1934 | ARM64_REG_ZA = AARCH64_REG_ZA, |
| 1935 | ARM64_REG_B0 = AARCH64_REG_B0, |
| 1936 | ARM64_REG_B1 = AARCH64_REG_B1, |
| 1937 | ARM64_REG_B2 = AARCH64_REG_B2, |
| 1938 | ARM64_REG_B3 = AARCH64_REG_B3, |
| 1939 | ARM64_REG_B4 = AARCH64_REG_B4, |
| 1940 | ARM64_REG_B5 = AARCH64_REG_B5, |
| 1941 | ARM64_REG_B6 = AARCH64_REG_B6, |
| 1942 | ARM64_REG_B7 = AARCH64_REG_B7, |
| 1943 | ARM64_REG_B8 = AARCH64_REG_B8, |
| 1944 | ARM64_REG_B9 = AARCH64_REG_B9, |
| 1945 | ARM64_REG_B10 = AARCH64_REG_B10, |
| 1946 | ARM64_REG_B11 = AARCH64_REG_B11, |
| 1947 | ARM64_REG_B12 = AARCH64_REG_B12, |
| 1948 | ARM64_REG_B13 = AARCH64_REG_B13, |
| 1949 | ARM64_REG_B14 = AARCH64_REG_B14, |
| 1950 | ARM64_REG_B15 = AARCH64_REG_B15, |
| 1951 | ARM64_REG_B16 = AARCH64_REG_B16, |
| 1952 | ARM64_REG_B17 = AARCH64_REG_B17, |
| 1953 | ARM64_REG_B18 = AARCH64_REG_B18, |
| 1954 | ARM64_REG_B19 = AARCH64_REG_B19, |
| 1955 | ARM64_REG_B20 = AARCH64_REG_B20, |
| 1956 | ARM64_REG_B21 = AARCH64_REG_B21, |
| 1957 | ARM64_REG_B22 = AARCH64_REG_B22, |
| 1958 | ARM64_REG_B23 = AARCH64_REG_B23, |
| 1959 | ARM64_REG_B24 = AARCH64_REG_B24, |
| 1960 | ARM64_REG_B25 = AARCH64_REG_B25, |
| 1961 | ARM64_REG_B26 = AARCH64_REG_B26, |
| 1962 | ARM64_REG_B27 = AARCH64_REG_B27, |
| 1963 | ARM64_REG_B28 = AARCH64_REG_B28, |
| 1964 | ARM64_REG_B29 = AARCH64_REG_B29, |
| 1965 | ARM64_REG_B30 = AARCH64_REG_B30, |
| 1966 | ARM64_REG_B31 = AARCH64_REG_B31, |
| 1967 | ARM64_REG_D0 = AARCH64_REG_D0, |
| 1968 | ARM64_REG_D1 = AARCH64_REG_D1, |
| 1969 | ARM64_REG_D2 = AARCH64_REG_D2, |
| 1970 | ARM64_REG_D3 = AARCH64_REG_D3, |
| 1971 | ARM64_REG_D4 = AARCH64_REG_D4, |
| 1972 | ARM64_REG_D5 = AARCH64_REG_D5, |
| 1973 | ARM64_REG_D6 = AARCH64_REG_D6, |
| 1974 | ARM64_REG_D7 = AARCH64_REG_D7, |
| 1975 | ARM64_REG_D8 = AARCH64_REG_D8, |
| 1976 | ARM64_REG_D9 = AARCH64_REG_D9, |
| 1977 | ARM64_REG_D10 = AARCH64_REG_D10, |
| 1978 | ARM64_REG_D11 = AARCH64_REG_D11, |
| 1979 | ARM64_REG_D12 = AARCH64_REG_D12, |
| 1980 | ARM64_REG_D13 = AARCH64_REG_D13, |
| 1981 | ARM64_REG_D14 = AARCH64_REG_D14, |
| 1982 | ARM64_REG_D15 = AARCH64_REG_D15, |
| 1983 | ARM64_REG_D16 = AARCH64_REG_D16, |
| 1984 | ARM64_REG_D17 = AARCH64_REG_D17, |
| 1985 | ARM64_REG_D18 = AARCH64_REG_D18, |
| 1986 | ARM64_REG_D19 = AARCH64_REG_D19, |
| 1987 | ARM64_REG_D20 = AARCH64_REG_D20, |
| 1988 | ARM64_REG_D21 = AARCH64_REG_D21, |
| 1989 | ARM64_REG_D22 = AARCH64_REG_D22, |
| 1990 | ARM64_REG_D23 = AARCH64_REG_D23, |
| 1991 | ARM64_REG_D24 = AARCH64_REG_D24, |
| 1992 | ARM64_REG_D25 = AARCH64_REG_D25, |
| 1993 | ARM64_REG_D26 = AARCH64_REG_D26, |
| 1994 | ARM64_REG_D27 = AARCH64_REG_D27, |
| 1995 | ARM64_REG_D28 = AARCH64_REG_D28, |
| 1996 | ARM64_REG_D29 = AARCH64_REG_D29, |
| 1997 | ARM64_REG_D30 = AARCH64_REG_D30, |
| 1998 | ARM64_REG_D31 = AARCH64_REG_D31, |
| 1999 | ARM64_REG_H0 = AARCH64_REG_H0, |
| 2000 | ARM64_REG_H1 = AARCH64_REG_H1, |
| 2001 | ARM64_REG_H2 = AARCH64_REG_H2, |
| 2002 | ARM64_REG_H3 = AARCH64_REG_H3, |
| 2003 | ARM64_REG_H4 = AARCH64_REG_H4, |
| 2004 | ARM64_REG_H5 = AARCH64_REG_H5, |
| 2005 | ARM64_REG_H6 = AARCH64_REG_H6, |
| 2006 | ARM64_REG_H7 = AARCH64_REG_H7, |
| 2007 | ARM64_REG_H8 = AARCH64_REG_H8, |
| 2008 | ARM64_REG_H9 = AARCH64_REG_H9, |
| 2009 | ARM64_REG_H10 = AARCH64_REG_H10, |
| 2010 | ARM64_REG_H11 = AARCH64_REG_H11, |
| 2011 | ARM64_REG_H12 = AARCH64_REG_H12, |
| 2012 | ARM64_REG_H13 = AARCH64_REG_H13, |
| 2013 | ARM64_REG_H14 = AARCH64_REG_H14, |
| 2014 | ARM64_REG_H15 = AARCH64_REG_H15, |
| 2015 | ARM64_REG_H16 = AARCH64_REG_H16, |
| 2016 | ARM64_REG_H17 = AARCH64_REG_H17, |
| 2017 | ARM64_REG_H18 = AARCH64_REG_H18, |
| 2018 | ARM64_REG_H19 = AARCH64_REG_H19, |
| 2019 | ARM64_REG_H20 = AARCH64_REG_H20, |
| 2020 | ARM64_REG_H21 = AARCH64_REG_H21, |
| 2021 | ARM64_REG_H22 = AARCH64_REG_H22, |
| 2022 | ARM64_REG_H23 = AARCH64_REG_H23, |
| 2023 | ARM64_REG_H24 = AARCH64_REG_H24, |
| 2024 | ARM64_REG_H25 = AARCH64_REG_H25, |
| 2025 | ARM64_REG_H26 = AARCH64_REG_H26, |
| 2026 | ARM64_REG_H27 = AARCH64_REG_H27, |
| 2027 | ARM64_REG_H28 = AARCH64_REG_H28, |
| 2028 | ARM64_REG_H29 = AARCH64_REG_H29, |
| 2029 | ARM64_REG_H30 = AARCH64_REG_H30, |
| 2030 | ARM64_REG_H31 = AARCH64_REG_H31, |
| 2031 | ARM64_REG_P0 = AARCH64_REG_P0, |
| 2032 | ARM64_REG_P1 = AARCH64_REG_P1, |
| 2033 | ARM64_REG_P2 = AARCH64_REG_P2, |
| 2034 | ARM64_REG_P3 = AARCH64_REG_P3, |
| 2035 | ARM64_REG_P4 = AARCH64_REG_P4, |
| 2036 | ARM64_REG_P5 = AARCH64_REG_P5, |
| 2037 | ARM64_REG_P6 = AARCH64_REG_P6, |
| 2038 | ARM64_REG_P7 = AARCH64_REG_P7, |
| 2039 | ARM64_REG_P8 = AARCH64_REG_P8, |
| 2040 | ARM64_REG_P9 = AARCH64_REG_P9, |
| 2041 | ARM64_REG_P10 = AARCH64_REG_P10, |
| 2042 | ARM64_REG_P11 = AARCH64_REG_P11, |
| 2043 | ARM64_REG_P12 = AARCH64_REG_P12, |
| 2044 | ARM64_REG_P13 = AARCH64_REG_P13, |
| 2045 | ARM64_REG_P14 = AARCH64_REG_P14, |
| 2046 | ARM64_REG_P15 = AARCH64_REG_P15, |
| 2047 | ARM64_REG_PN0 = AARCH64_REG_PN0, |
| 2048 | ARM64_REG_PN1 = AARCH64_REG_PN1, |
| 2049 | ARM64_REG_PN2 = AARCH64_REG_PN2, |
| 2050 | ARM64_REG_PN3 = AARCH64_REG_PN3, |
| 2051 | ARM64_REG_PN4 = AARCH64_REG_PN4, |
| 2052 | ARM64_REG_PN5 = AARCH64_REG_PN5, |
| 2053 | ARM64_REG_PN6 = AARCH64_REG_PN6, |
| 2054 | ARM64_REG_PN7 = AARCH64_REG_PN7, |
| 2055 | ARM64_REG_PN8 = AARCH64_REG_PN8, |
| 2056 | ARM64_REG_PN9 = AARCH64_REG_PN9, |
| 2057 | ARM64_REG_PN10 = AARCH64_REG_PN10, |
| 2058 | ARM64_REG_PN11 = AARCH64_REG_PN11, |
| 2059 | ARM64_REG_PN12 = AARCH64_REG_PN12, |
| 2060 | ARM64_REG_PN13 = AARCH64_REG_PN13, |
| 2061 | ARM64_REG_PN14 = AARCH64_REG_PN14, |
| 2062 | ARM64_REG_PN15 = AARCH64_REG_PN15, |
| 2063 | ARM64_REG_Q0 = AARCH64_REG_Q0, |
| 2064 | ARM64_REG_Q1 = AARCH64_REG_Q1, |
| 2065 | ARM64_REG_Q2 = AARCH64_REG_Q2, |
| 2066 | ARM64_REG_Q3 = AARCH64_REG_Q3, |
| 2067 | ARM64_REG_Q4 = AARCH64_REG_Q4, |
| 2068 | ARM64_REG_Q5 = AARCH64_REG_Q5, |
| 2069 | ARM64_REG_Q6 = AARCH64_REG_Q6, |
| 2070 | ARM64_REG_Q7 = AARCH64_REG_Q7, |
| 2071 | ARM64_REG_Q8 = AARCH64_REG_Q8, |
| 2072 | ARM64_REG_Q9 = AARCH64_REG_Q9, |
| 2073 | ARM64_REG_Q10 = AARCH64_REG_Q10, |
| 2074 | ARM64_REG_Q11 = AARCH64_REG_Q11, |
| 2075 | ARM64_REG_Q12 = AARCH64_REG_Q12, |
| 2076 | ARM64_REG_Q13 = AARCH64_REG_Q13, |
| 2077 | ARM64_REG_Q14 = AARCH64_REG_Q14, |
| 2078 | ARM64_REG_Q15 = AARCH64_REG_Q15, |
| 2079 | ARM64_REG_Q16 = AARCH64_REG_Q16, |
| 2080 | ARM64_REG_Q17 = AARCH64_REG_Q17, |
| 2081 | ARM64_REG_Q18 = AARCH64_REG_Q18, |
| 2082 | ARM64_REG_Q19 = AARCH64_REG_Q19, |
| 2083 | ARM64_REG_Q20 = AARCH64_REG_Q20, |
| 2084 | ARM64_REG_Q21 = AARCH64_REG_Q21, |
| 2085 | ARM64_REG_Q22 = AARCH64_REG_Q22, |
| 2086 | ARM64_REG_Q23 = AARCH64_REG_Q23, |
| 2087 | ARM64_REG_Q24 = AARCH64_REG_Q24, |
| 2088 | ARM64_REG_Q25 = AARCH64_REG_Q25, |
| 2089 | ARM64_REG_Q26 = AARCH64_REG_Q26, |
| 2090 | ARM64_REG_Q27 = AARCH64_REG_Q27, |
| 2091 | ARM64_REG_Q28 = AARCH64_REG_Q28, |
| 2092 | ARM64_REG_Q29 = AARCH64_REG_Q29, |
| 2093 | ARM64_REG_Q30 = AARCH64_REG_Q30, |
| 2094 | ARM64_REG_Q31 = AARCH64_REG_Q31, |
| 2095 | ARM64_REG_S0 = AARCH64_REG_S0, |
| 2096 | ARM64_REG_S1 = AARCH64_REG_S1, |
| 2097 | ARM64_REG_S2 = AARCH64_REG_S2, |
| 2098 | ARM64_REG_S3 = AARCH64_REG_S3, |
| 2099 | ARM64_REG_S4 = AARCH64_REG_S4, |
| 2100 | ARM64_REG_S5 = AARCH64_REG_S5, |
| 2101 | ARM64_REG_S6 = AARCH64_REG_S6, |
| 2102 | ARM64_REG_S7 = AARCH64_REG_S7, |
| 2103 | ARM64_REG_S8 = AARCH64_REG_S8, |
| 2104 | ARM64_REG_S9 = AARCH64_REG_S9, |
| 2105 | ARM64_REG_S10 = AARCH64_REG_S10, |
| 2106 | ARM64_REG_S11 = AARCH64_REG_S11, |
| 2107 | ARM64_REG_S12 = AARCH64_REG_S12, |
| 2108 | ARM64_REG_S13 = AARCH64_REG_S13, |
| 2109 | ARM64_REG_S14 = AARCH64_REG_S14, |
| 2110 | ARM64_REG_S15 = AARCH64_REG_S15, |
| 2111 | ARM64_REG_S16 = AARCH64_REG_S16, |
| 2112 | ARM64_REG_S17 = AARCH64_REG_S17, |
| 2113 | ARM64_REG_S18 = AARCH64_REG_S18, |
| 2114 | ARM64_REG_S19 = AARCH64_REG_S19, |
| 2115 | ARM64_REG_S20 = AARCH64_REG_S20, |
| 2116 | ARM64_REG_S21 = AARCH64_REG_S21, |
| 2117 | ARM64_REG_S22 = AARCH64_REG_S22, |
| 2118 | ARM64_REG_S23 = AARCH64_REG_S23, |
| 2119 | ARM64_REG_S24 = AARCH64_REG_S24, |
| 2120 | ARM64_REG_S25 = AARCH64_REG_S25, |
| 2121 | ARM64_REG_S26 = AARCH64_REG_S26, |
| 2122 | ARM64_REG_S27 = AARCH64_REG_S27, |
| 2123 | ARM64_REG_S28 = AARCH64_REG_S28, |
| 2124 | ARM64_REG_S29 = AARCH64_REG_S29, |
| 2125 | ARM64_REG_S30 = AARCH64_REG_S30, |
| 2126 | ARM64_REG_S31 = AARCH64_REG_S31, |
| 2127 | ARM64_REG_W0 = AARCH64_REG_W0, |
| 2128 | ARM64_REG_W1 = AARCH64_REG_W1, |
| 2129 | ARM64_REG_W2 = AARCH64_REG_W2, |
| 2130 | ARM64_REG_W3 = AARCH64_REG_W3, |
| 2131 | ARM64_REG_W4 = AARCH64_REG_W4, |
| 2132 | ARM64_REG_W5 = AARCH64_REG_W5, |
| 2133 | ARM64_REG_W6 = AARCH64_REG_W6, |
| 2134 | ARM64_REG_W7 = AARCH64_REG_W7, |
| 2135 | ARM64_REG_W8 = AARCH64_REG_W8, |
| 2136 | ARM64_REG_W9 = AARCH64_REG_W9, |
| 2137 | ARM64_REG_W10 = AARCH64_REG_W10, |
| 2138 | ARM64_REG_W11 = AARCH64_REG_W11, |
| 2139 | ARM64_REG_W12 = AARCH64_REG_W12, |
| 2140 | ARM64_REG_W13 = AARCH64_REG_W13, |
| 2141 | ARM64_REG_W14 = AARCH64_REG_W14, |
| 2142 | ARM64_REG_W15 = AARCH64_REG_W15, |
| 2143 | ARM64_REG_W16 = AARCH64_REG_W16, |
| 2144 | ARM64_REG_W17 = AARCH64_REG_W17, |
| 2145 | ARM64_REG_W18 = AARCH64_REG_W18, |
| 2146 | ARM64_REG_W19 = AARCH64_REG_W19, |
| 2147 | ARM64_REG_W20 = AARCH64_REG_W20, |
| 2148 | ARM64_REG_W21 = AARCH64_REG_W21, |
| 2149 | ARM64_REG_W22 = AARCH64_REG_W22, |
| 2150 | ARM64_REG_W23 = AARCH64_REG_W23, |
| 2151 | ARM64_REG_W24 = AARCH64_REG_W24, |
| 2152 | ARM64_REG_W25 = AARCH64_REG_W25, |
| 2153 | ARM64_REG_W26 = AARCH64_REG_W26, |
| 2154 | ARM64_REG_W27 = AARCH64_REG_W27, |
| 2155 | ARM64_REG_W28 = AARCH64_REG_W28, |
| 2156 | ARM64_REG_W29 = AARCH64_REG_W29, |
| 2157 | ARM64_REG_W30 = AARCH64_REG_W30, |
| 2158 | ARM64_REG_X0 = AARCH64_REG_X0, |
| 2159 | ARM64_REG_X1 = AARCH64_REG_X1, |
| 2160 | ARM64_REG_X2 = AARCH64_REG_X2, |
| 2161 | ARM64_REG_X3 = AARCH64_REG_X3, |
| 2162 | ARM64_REG_X4 = AARCH64_REG_X4, |
| 2163 | ARM64_REG_X5 = AARCH64_REG_X5, |
| 2164 | ARM64_REG_X6 = AARCH64_REG_X6, |
| 2165 | ARM64_REG_X7 = AARCH64_REG_X7, |
| 2166 | ARM64_REG_X8 = AARCH64_REG_X8, |
| 2167 | ARM64_REG_X9 = AARCH64_REG_X9, |
| 2168 | ARM64_REG_X10 = AARCH64_REG_X10, |
| 2169 | ARM64_REG_X11 = AARCH64_REG_X11, |
| 2170 | ARM64_REG_X12 = AARCH64_REG_X12, |
| 2171 | ARM64_REG_X13 = AARCH64_REG_X13, |
| 2172 | ARM64_REG_X14 = AARCH64_REG_X14, |
| 2173 | ARM64_REG_X15 = AARCH64_REG_X15, |
| 2174 | ARM64_REG_X16 = AARCH64_REG_X16, |
| 2175 | ARM64_REG_X17 = AARCH64_REG_X17, |
| 2176 | ARM64_REG_X18 = AARCH64_REG_X18, |
| 2177 | ARM64_REG_X19 = AARCH64_REG_X19, |
| 2178 | ARM64_REG_X20 = AARCH64_REG_X20, |
| 2179 | ARM64_REG_X21 = AARCH64_REG_X21, |
| 2180 | ARM64_REG_X22 = AARCH64_REG_X22, |
| 2181 | ARM64_REG_X23 = AARCH64_REG_X23, |
| 2182 | ARM64_REG_X24 = AARCH64_REG_X24, |
| 2183 | ARM64_REG_X25 = AARCH64_REG_X25, |
| 2184 | ARM64_REG_X26 = AARCH64_REG_X26, |
| 2185 | ARM64_REG_X27 = AARCH64_REG_X27, |
| 2186 | ARM64_REG_X28 = AARCH64_REG_X28, |
| 2187 | ARM64_REG_Z0 = AARCH64_REG_Z0, |
| 2188 | ARM64_REG_Z1 = AARCH64_REG_Z1, |
| 2189 | ARM64_REG_Z2 = AARCH64_REG_Z2, |
| 2190 | ARM64_REG_Z3 = AARCH64_REG_Z3, |
| 2191 | ARM64_REG_Z4 = AARCH64_REG_Z4, |
| 2192 | ARM64_REG_Z5 = AARCH64_REG_Z5, |
| 2193 | ARM64_REG_Z6 = AARCH64_REG_Z6, |
| 2194 | ARM64_REG_Z7 = AARCH64_REG_Z7, |
| 2195 | ARM64_REG_Z8 = AARCH64_REG_Z8, |
| 2196 | ARM64_REG_Z9 = AARCH64_REG_Z9, |
| 2197 | ARM64_REG_Z10 = AARCH64_REG_Z10, |
| 2198 | ARM64_REG_Z11 = AARCH64_REG_Z11, |
| 2199 | ARM64_REG_Z12 = AARCH64_REG_Z12, |
| 2200 | ARM64_REG_Z13 = AARCH64_REG_Z13, |
| 2201 | ARM64_REG_Z14 = AARCH64_REG_Z14, |
| 2202 | ARM64_REG_Z15 = AARCH64_REG_Z15, |
| 2203 | ARM64_REG_Z16 = AARCH64_REG_Z16, |
| 2204 | ARM64_REG_Z17 = AARCH64_REG_Z17, |
| 2205 | ARM64_REG_Z18 = AARCH64_REG_Z18, |
| 2206 | ARM64_REG_Z19 = AARCH64_REG_Z19, |
| 2207 | ARM64_REG_Z20 = AARCH64_REG_Z20, |
| 2208 | ARM64_REG_Z21 = AARCH64_REG_Z21, |
| 2209 | ARM64_REG_Z22 = AARCH64_REG_Z22, |
| 2210 | ARM64_REG_Z23 = AARCH64_REG_Z23, |
| 2211 | ARM64_REG_Z24 = AARCH64_REG_Z24, |
| 2212 | ARM64_REG_Z25 = AARCH64_REG_Z25, |
| 2213 | ARM64_REG_Z26 = AARCH64_REG_Z26, |
| 2214 | ARM64_REG_Z27 = AARCH64_REG_Z27, |
| 2215 | ARM64_REG_Z28 = AARCH64_REG_Z28, |
| 2216 | ARM64_REG_Z29 = AARCH64_REG_Z29, |
| 2217 | ARM64_REG_Z30 = AARCH64_REG_Z30, |
| 2218 | ARM64_REG_Z31 = AARCH64_REG_Z31, |
| 2219 | ARM64_REG_ZAB0 = AARCH64_REG_ZAB0, |
| 2220 | ARM64_REG_ZAD0 = AARCH64_REG_ZAD0, |
| 2221 | ARM64_REG_ZAD1 = AARCH64_REG_ZAD1, |
| 2222 | ARM64_REG_ZAD2 = AARCH64_REG_ZAD2, |
| 2223 | ARM64_REG_ZAD3 = AARCH64_REG_ZAD3, |
| 2224 | ARM64_REG_ZAD4 = AARCH64_REG_ZAD4, |
| 2225 | ARM64_REG_ZAD5 = AARCH64_REG_ZAD5, |
| 2226 | ARM64_REG_ZAD6 = AARCH64_REG_ZAD6, |
| 2227 | ARM64_REG_ZAD7 = AARCH64_REG_ZAD7, |
| 2228 | ARM64_REG_ZAH0 = AARCH64_REG_ZAH0, |
| 2229 | ARM64_REG_ZAH1 = AARCH64_REG_ZAH1, |
| 2230 | ARM64_REG_ZAQ0 = AARCH64_REG_ZAQ0, |
| 2231 | ARM64_REG_ZAQ1 = AARCH64_REG_ZAQ1, |
| 2232 | ARM64_REG_ZAQ2 = AARCH64_REG_ZAQ2, |
| 2233 | ARM64_REG_ZAQ3 = AARCH64_REG_ZAQ3, |
| 2234 | ARM64_REG_ZAQ4 = AARCH64_REG_ZAQ4, |
| 2235 | ARM64_REG_ZAQ5 = AARCH64_REG_ZAQ5, |
| 2236 | ARM64_REG_ZAQ6 = AARCH64_REG_ZAQ6, |
| 2237 | ARM64_REG_ZAQ7 = AARCH64_REG_ZAQ7, |
| 2238 | ARM64_REG_ZAQ8 = AARCH64_REG_ZAQ8, |
| 2239 | ARM64_REG_ZAQ9 = AARCH64_REG_ZAQ9, |
| 2240 | ARM64_REG_ZAQ10 = AARCH64_REG_ZAQ10, |
| 2241 | ARM64_REG_ZAQ11 = AARCH64_REG_ZAQ11, |
| 2242 | ARM64_REG_ZAQ12 = AARCH64_REG_ZAQ12, |
| 2243 | ARM64_REG_ZAQ13 = AARCH64_REG_ZAQ13, |
| 2244 | ARM64_REG_ZAQ14 = AARCH64_REG_ZAQ14, |
| 2245 | ARM64_REG_ZAQ15 = AARCH64_REG_ZAQ15, |
| 2246 | ARM64_REG_ZAS0 = AARCH64_REG_ZAS0, |
| 2247 | ARM64_REG_ZAS1 = AARCH64_REG_ZAS1, |
| 2248 | ARM64_REG_ZAS2 = AARCH64_REG_ZAS2, |
| 2249 | ARM64_REG_ZAS3 = AARCH64_REG_ZAS3, |
| 2250 | ARM64_REG_ZT0 = AARCH64_REG_ZT0, |
| 2251 | ARM64_REG_D0_D1 = AARCH64_REG_D0_D1, |
| 2252 | ARM64_REG_D1_D2 = AARCH64_REG_D1_D2, |
| 2253 | ARM64_REG_D2_D3 = AARCH64_REG_D2_D3, |
| 2254 | ARM64_REG_D3_D4 = AARCH64_REG_D3_D4, |
| 2255 | ARM64_REG_D4_D5 = AARCH64_REG_D4_D5, |
| 2256 | ARM64_REG_D5_D6 = AARCH64_REG_D5_D6, |
| 2257 | ARM64_REG_D6_D7 = AARCH64_REG_D6_D7, |
| 2258 | ARM64_REG_D7_D8 = AARCH64_REG_D7_D8, |
| 2259 | ARM64_REG_D8_D9 = AARCH64_REG_D8_D9, |
| 2260 | ARM64_REG_D9_D10 = AARCH64_REG_D9_D10, |
| 2261 | ARM64_REG_D10_D11 = AARCH64_REG_D10_D11, |
| 2262 | ARM64_REG_D11_D12 = AARCH64_REG_D11_D12, |
| 2263 | ARM64_REG_D12_D13 = AARCH64_REG_D12_D13, |
| 2264 | ARM64_REG_D13_D14 = AARCH64_REG_D13_D14, |
| 2265 | ARM64_REG_D14_D15 = AARCH64_REG_D14_D15, |
| 2266 | ARM64_REG_D15_D16 = AARCH64_REG_D15_D16, |
| 2267 | ARM64_REG_D16_D17 = AARCH64_REG_D16_D17, |
| 2268 | ARM64_REG_D17_D18 = AARCH64_REG_D17_D18, |
| 2269 | ARM64_REG_D18_D19 = AARCH64_REG_D18_D19, |
| 2270 | ARM64_REG_D19_D20 = AARCH64_REG_D19_D20, |
| 2271 | ARM64_REG_D20_D21 = AARCH64_REG_D20_D21, |
| 2272 | ARM64_REG_D21_D22 = AARCH64_REG_D21_D22, |
| 2273 | ARM64_REG_D22_D23 = AARCH64_REG_D22_D23, |
| 2274 | ARM64_REG_D23_D24 = AARCH64_REG_D23_D24, |
| 2275 | ARM64_REG_D24_D25 = AARCH64_REG_D24_D25, |
| 2276 | ARM64_REG_D25_D26 = AARCH64_REG_D25_D26, |
| 2277 | ARM64_REG_D26_D27 = AARCH64_REG_D26_D27, |
| 2278 | ARM64_REG_D27_D28 = AARCH64_REG_D27_D28, |
| 2279 | ARM64_REG_D28_D29 = AARCH64_REG_D28_D29, |
| 2280 | ARM64_REG_D29_D30 = AARCH64_REG_D29_D30, |
| 2281 | ARM64_REG_D30_D31 = AARCH64_REG_D30_D31, |
| 2282 | ARM64_REG_D31_D0 = AARCH64_REG_D31_D0, |
| 2283 | ARM64_REG_D0_D1_D2_D3 = AARCH64_REG_D0_D1_D2_D3, |
| 2284 | ARM64_REG_D1_D2_D3_D4 = AARCH64_REG_D1_D2_D3_D4, |
| 2285 | ARM64_REG_D2_D3_D4_D5 = AARCH64_REG_D2_D3_D4_D5, |
| 2286 | ARM64_REG_D3_D4_D5_D6 = AARCH64_REG_D3_D4_D5_D6, |
| 2287 | ARM64_REG_D4_D5_D6_D7 = AARCH64_REG_D4_D5_D6_D7, |
| 2288 | ARM64_REG_D5_D6_D7_D8 = AARCH64_REG_D5_D6_D7_D8, |
| 2289 | ARM64_REG_D6_D7_D8_D9 = AARCH64_REG_D6_D7_D8_D9, |
| 2290 | ARM64_REG_D7_D8_D9_D10 = AARCH64_REG_D7_D8_D9_D10, |
| 2291 | ARM64_REG_D8_D9_D10_D11 = AARCH64_REG_D8_D9_D10_D11, |
| 2292 | ARM64_REG_D9_D10_D11_D12 = AARCH64_REG_D9_D10_D11_D12, |
| 2293 | ARM64_REG_D10_D11_D12_D13 = AARCH64_REG_D10_D11_D12_D13, |
| 2294 | ARM64_REG_D11_D12_D13_D14 = AARCH64_REG_D11_D12_D13_D14, |
| 2295 | ARM64_REG_D12_D13_D14_D15 = AARCH64_REG_D12_D13_D14_D15, |
| 2296 | ARM64_REG_D13_D14_D15_D16 = AARCH64_REG_D13_D14_D15_D16, |
| 2297 | ARM64_REG_D14_D15_D16_D17 = AARCH64_REG_D14_D15_D16_D17, |
| 2298 | ARM64_REG_D15_D16_D17_D18 = AARCH64_REG_D15_D16_D17_D18, |
| 2299 | ARM64_REG_D16_D17_D18_D19 = AARCH64_REG_D16_D17_D18_D19, |
| 2300 | ARM64_REG_D17_D18_D19_D20 = AARCH64_REG_D17_D18_D19_D20, |
| 2301 | ARM64_REG_D18_D19_D20_D21 = AARCH64_REG_D18_D19_D20_D21, |
| 2302 | ARM64_REG_D19_D20_D21_D22 = AARCH64_REG_D19_D20_D21_D22, |
| 2303 | ARM64_REG_D20_D21_D22_D23 = AARCH64_REG_D20_D21_D22_D23, |
| 2304 | ARM64_REG_D21_D22_D23_D24 = AARCH64_REG_D21_D22_D23_D24, |
| 2305 | ARM64_REG_D22_D23_D24_D25 = AARCH64_REG_D22_D23_D24_D25, |
| 2306 | ARM64_REG_D23_D24_D25_D26 = AARCH64_REG_D23_D24_D25_D26, |
| 2307 | ARM64_REG_D24_D25_D26_D27 = AARCH64_REG_D24_D25_D26_D27, |
| 2308 | ARM64_REG_D25_D26_D27_D28 = AARCH64_REG_D25_D26_D27_D28, |
| 2309 | ARM64_REG_D26_D27_D28_D29 = AARCH64_REG_D26_D27_D28_D29, |
| 2310 | ARM64_REG_D27_D28_D29_D30 = AARCH64_REG_D27_D28_D29_D30, |
| 2311 | ARM64_REG_D28_D29_D30_D31 = AARCH64_REG_D28_D29_D30_D31, |
| 2312 | ARM64_REG_D29_D30_D31_D0 = AARCH64_REG_D29_D30_D31_D0, |
| 2313 | ARM64_REG_D30_D31_D0_D1 = AARCH64_REG_D30_D31_D0_D1, |
| 2314 | ARM64_REG_D31_D0_D1_D2 = AARCH64_REG_D31_D0_D1_D2, |
| 2315 | ARM64_REG_D0_D1_D2 = AARCH64_REG_D0_D1_D2, |
| 2316 | ARM64_REG_D1_D2_D3 = AARCH64_REG_D1_D2_D3, |
| 2317 | ARM64_REG_D2_D3_D4 = AARCH64_REG_D2_D3_D4, |
| 2318 | ARM64_REG_D3_D4_D5 = AARCH64_REG_D3_D4_D5, |
| 2319 | ARM64_REG_D4_D5_D6 = AARCH64_REG_D4_D5_D6, |
| 2320 | ARM64_REG_D5_D6_D7 = AARCH64_REG_D5_D6_D7, |
| 2321 | ARM64_REG_D6_D7_D8 = AARCH64_REG_D6_D7_D8, |
| 2322 | ARM64_REG_D7_D8_D9 = AARCH64_REG_D7_D8_D9, |
| 2323 | ARM64_REG_D8_D9_D10 = AARCH64_REG_D8_D9_D10, |
| 2324 | ARM64_REG_D9_D10_D11 = AARCH64_REG_D9_D10_D11, |
| 2325 | ARM64_REG_D10_D11_D12 = AARCH64_REG_D10_D11_D12, |
| 2326 | ARM64_REG_D11_D12_D13 = AARCH64_REG_D11_D12_D13, |
| 2327 | ARM64_REG_D12_D13_D14 = AARCH64_REG_D12_D13_D14, |
| 2328 | ARM64_REG_D13_D14_D15 = AARCH64_REG_D13_D14_D15, |
| 2329 | ARM64_REG_D14_D15_D16 = AARCH64_REG_D14_D15_D16, |
| 2330 | ARM64_REG_D15_D16_D17 = AARCH64_REG_D15_D16_D17, |
| 2331 | ARM64_REG_D16_D17_D18 = AARCH64_REG_D16_D17_D18, |
| 2332 | ARM64_REG_D17_D18_D19 = AARCH64_REG_D17_D18_D19, |
| 2333 | ARM64_REG_D18_D19_D20 = AARCH64_REG_D18_D19_D20, |
| 2334 | ARM64_REG_D19_D20_D21 = AARCH64_REG_D19_D20_D21, |
| 2335 | ARM64_REG_D20_D21_D22 = AARCH64_REG_D20_D21_D22, |
| 2336 | ARM64_REG_D21_D22_D23 = AARCH64_REG_D21_D22_D23, |
| 2337 | ARM64_REG_D22_D23_D24 = AARCH64_REG_D22_D23_D24, |
| 2338 | ARM64_REG_D23_D24_D25 = AARCH64_REG_D23_D24_D25, |
| 2339 | ARM64_REG_D24_D25_D26 = AARCH64_REG_D24_D25_D26, |
| 2340 | ARM64_REG_D25_D26_D27 = AARCH64_REG_D25_D26_D27, |
| 2341 | ARM64_REG_D26_D27_D28 = AARCH64_REG_D26_D27_D28, |
| 2342 | ARM64_REG_D27_D28_D29 = AARCH64_REG_D27_D28_D29, |
| 2343 | ARM64_REG_D28_D29_D30 = AARCH64_REG_D28_D29_D30, |
| 2344 | ARM64_REG_D29_D30_D31 = AARCH64_REG_D29_D30_D31, |
| 2345 | ARM64_REG_D30_D31_D0 = AARCH64_REG_D30_D31_D0, |
| 2346 | ARM64_REG_D31_D0_D1 = AARCH64_REG_D31_D0_D1, |
| 2347 | ARM64_REG_P0_P1 = AARCH64_REG_P0_P1, |
| 2348 | ARM64_REG_P1_P2 = AARCH64_REG_P1_P2, |
| 2349 | ARM64_REG_P2_P3 = AARCH64_REG_P2_P3, |
| 2350 | ARM64_REG_P3_P4 = AARCH64_REG_P3_P4, |
| 2351 | ARM64_REG_P4_P5 = AARCH64_REG_P4_P5, |
| 2352 | ARM64_REG_P5_P6 = AARCH64_REG_P5_P6, |
| 2353 | ARM64_REG_P6_P7 = AARCH64_REG_P6_P7, |
| 2354 | ARM64_REG_P7_P8 = AARCH64_REG_P7_P8, |
| 2355 | ARM64_REG_P8_P9 = AARCH64_REG_P8_P9, |
| 2356 | ARM64_REG_P9_P10 = AARCH64_REG_P9_P10, |
| 2357 | ARM64_REG_P10_P11 = AARCH64_REG_P10_P11, |
| 2358 | ARM64_REG_P11_P12 = AARCH64_REG_P11_P12, |
| 2359 | ARM64_REG_P12_P13 = AARCH64_REG_P12_P13, |
| 2360 | ARM64_REG_P13_P14 = AARCH64_REG_P13_P14, |
| 2361 | ARM64_REG_P14_P15 = AARCH64_REG_P14_P15, |
| 2362 | ARM64_REG_P15_P0 = AARCH64_REG_P15_P0, |
| 2363 | ARM64_REG_Q0_Q1 = AARCH64_REG_Q0_Q1, |
| 2364 | ARM64_REG_Q1_Q2 = AARCH64_REG_Q1_Q2, |
| 2365 | ARM64_REG_Q2_Q3 = AARCH64_REG_Q2_Q3, |
| 2366 | ARM64_REG_Q3_Q4 = AARCH64_REG_Q3_Q4, |
| 2367 | ARM64_REG_Q4_Q5 = AARCH64_REG_Q4_Q5, |
| 2368 | ARM64_REG_Q5_Q6 = AARCH64_REG_Q5_Q6, |
| 2369 | ARM64_REG_Q6_Q7 = AARCH64_REG_Q6_Q7, |
| 2370 | ARM64_REG_Q7_Q8 = AARCH64_REG_Q7_Q8, |
| 2371 | ARM64_REG_Q8_Q9 = AARCH64_REG_Q8_Q9, |
| 2372 | ARM64_REG_Q9_Q10 = AARCH64_REG_Q9_Q10, |
| 2373 | ARM64_REG_Q10_Q11 = AARCH64_REG_Q10_Q11, |
| 2374 | ARM64_REG_Q11_Q12 = AARCH64_REG_Q11_Q12, |
| 2375 | ARM64_REG_Q12_Q13 = AARCH64_REG_Q12_Q13, |
| 2376 | ARM64_REG_Q13_Q14 = AARCH64_REG_Q13_Q14, |
| 2377 | ARM64_REG_Q14_Q15 = AARCH64_REG_Q14_Q15, |
| 2378 | ARM64_REG_Q15_Q16 = AARCH64_REG_Q15_Q16, |
| 2379 | ARM64_REG_Q16_Q17 = AARCH64_REG_Q16_Q17, |
| 2380 | ARM64_REG_Q17_Q18 = AARCH64_REG_Q17_Q18, |
| 2381 | ARM64_REG_Q18_Q19 = AARCH64_REG_Q18_Q19, |
| 2382 | ARM64_REG_Q19_Q20 = AARCH64_REG_Q19_Q20, |
| 2383 | ARM64_REG_Q20_Q21 = AARCH64_REG_Q20_Q21, |
| 2384 | ARM64_REG_Q21_Q22 = AARCH64_REG_Q21_Q22, |
| 2385 | ARM64_REG_Q22_Q23 = AARCH64_REG_Q22_Q23, |
| 2386 | ARM64_REG_Q23_Q24 = AARCH64_REG_Q23_Q24, |
| 2387 | ARM64_REG_Q24_Q25 = AARCH64_REG_Q24_Q25, |
| 2388 | ARM64_REG_Q25_Q26 = AARCH64_REG_Q25_Q26, |
| 2389 | ARM64_REG_Q26_Q27 = AARCH64_REG_Q26_Q27, |
| 2390 | ARM64_REG_Q27_Q28 = AARCH64_REG_Q27_Q28, |
| 2391 | ARM64_REG_Q28_Q29 = AARCH64_REG_Q28_Q29, |
| 2392 | ARM64_REG_Q29_Q30 = AARCH64_REG_Q29_Q30, |
| 2393 | ARM64_REG_Q30_Q31 = AARCH64_REG_Q30_Q31, |
| 2394 | ARM64_REG_Q31_Q0 = AARCH64_REG_Q31_Q0, |
| 2395 | ARM64_REG_Q0_Q1_Q2_Q3 = AARCH64_REG_Q0_Q1_Q2_Q3, |
| 2396 | ARM64_REG_Q1_Q2_Q3_Q4 = AARCH64_REG_Q1_Q2_Q3_Q4, |
| 2397 | ARM64_REG_Q2_Q3_Q4_Q5 = AARCH64_REG_Q2_Q3_Q4_Q5, |
| 2398 | ARM64_REG_Q3_Q4_Q5_Q6 = AARCH64_REG_Q3_Q4_Q5_Q6, |
| 2399 | ARM64_REG_Q4_Q5_Q6_Q7 = AARCH64_REG_Q4_Q5_Q6_Q7, |
| 2400 | ARM64_REG_Q5_Q6_Q7_Q8 = AARCH64_REG_Q5_Q6_Q7_Q8, |
| 2401 | ARM64_REG_Q6_Q7_Q8_Q9 = AARCH64_REG_Q6_Q7_Q8_Q9, |
| 2402 | ARM64_REG_Q7_Q8_Q9_Q10 = AARCH64_REG_Q7_Q8_Q9_Q10, |
| 2403 | ARM64_REG_Q8_Q9_Q10_Q11 = AARCH64_REG_Q8_Q9_Q10_Q11, |
| 2404 | ARM64_REG_Q9_Q10_Q11_Q12 = AARCH64_REG_Q9_Q10_Q11_Q12, |
| 2405 | ARM64_REG_Q10_Q11_Q12_Q13 = AARCH64_REG_Q10_Q11_Q12_Q13, |
| 2406 | ARM64_REG_Q11_Q12_Q13_Q14 = AARCH64_REG_Q11_Q12_Q13_Q14, |
| 2407 | ARM64_REG_Q12_Q13_Q14_Q15 = AARCH64_REG_Q12_Q13_Q14_Q15, |
| 2408 | ARM64_REG_Q13_Q14_Q15_Q16 = AARCH64_REG_Q13_Q14_Q15_Q16, |
| 2409 | ARM64_REG_Q14_Q15_Q16_Q17 = AARCH64_REG_Q14_Q15_Q16_Q17, |
| 2410 | ARM64_REG_Q15_Q16_Q17_Q18 = AARCH64_REG_Q15_Q16_Q17_Q18, |
| 2411 | ARM64_REG_Q16_Q17_Q18_Q19 = AARCH64_REG_Q16_Q17_Q18_Q19, |
| 2412 | ARM64_REG_Q17_Q18_Q19_Q20 = AARCH64_REG_Q17_Q18_Q19_Q20, |
| 2413 | ARM64_REG_Q18_Q19_Q20_Q21 = AARCH64_REG_Q18_Q19_Q20_Q21, |
| 2414 | ARM64_REG_Q19_Q20_Q21_Q22 = AARCH64_REG_Q19_Q20_Q21_Q22, |
| 2415 | ARM64_REG_Q20_Q21_Q22_Q23 = AARCH64_REG_Q20_Q21_Q22_Q23, |
| 2416 | ARM64_REG_Q21_Q22_Q23_Q24 = AARCH64_REG_Q21_Q22_Q23_Q24, |
| 2417 | ARM64_REG_Q22_Q23_Q24_Q25 = AARCH64_REG_Q22_Q23_Q24_Q25, |
| 2418 | ARM64_REG_Q23_Q24_Q25_Q26 = AARCH64_REG_Q23_Q24_Q25_Q26, |
| 2419 | ARM64_REG_Q24_Q25_Q26_Q27 = AARCH64_REG_Q24_Q25_Q26_Q27, |
| 2420 | ARM64_REG_Q25_Q26_Q27_Q28 = AARCH64_REG_Q25_Q26_Q27_Q28, |
| 2421 | ARM64_REG_Q26_Q27_Q28_Q29 = AARCH64_REG_Q26_Q27_Q28_Q29, |
| 2422 | ARM64_REG_Q27_Q28_Q29_Q30 = AARCH64_REG_Q27_Q28_Q29_Q30, |
| 2423 | ARM64_REG_Q28_Q29_Q30_Q31 = AARCH64_REG_Q28_Q29_Q30_Q31, |
| 2424 | ARM64_REG_Q29_Q30_Q31_Q0 = AARCH64_REG_Q29_Q30_Q31_Q0, |
| 2425 | ARM64_REG_Q30_Q31_Q0_Q1 = AARCH64_REG_Q30_Q31_Q0_Q1, |
| 2426 | ARM64_REG_Q31_Q0_Q1_Q2 = AARCH64_REG_Q31_Q0_Q1_Q2, |
| 2427 | ARM64_REG_Q0_Q1_Q2 = AARCH64_REG_Q0_Q1_Q2, |
| 2428 | ARM64_REG_Q1_Q2_Q3 = AARCH64_REG_Q1_Q2_Q3, |
| 2429 | ARM64_REG_Q2_Q3_Q4 = AARCH64_REG_Q2_Q3_Q4, |
| 2430 | ARM64_REG_Q3_Q4_Q5 = AARCH64_REG_Q3_Q4_Q5, |
| 2431 | ARM64_REG_Q4_Q5_Q6 = AARCH64_REG_Q4_Q5_Q6, |
| 2432 | ARM64_REG_Q5_Q6_Q7 = AARCH64_REG_Q5_Q6_Q7, |
| 2433 | ARM64_REG_Q6_Q7_Q8 = AARCH64_REG_Q6_Q7_Q8, |
| 2434 | ARM64_REG_Q7_Q8_Q9 = AARCH64_REG_Q7_Q8_Q9, |
| 2435 | ARM64_REG_Q8_Q9_Q10 = AARCH64_REG_Q8_Q9_Q10, |
| 2436 | ARM64_REG_Q9_Q10_Q11 = AARCH64_REG_Q9_Q10_Q11, |
| 2437 | ARM64_REG_Q10_Q11_Q12 = AARCH64_REG_Q10_Q11_Q12, |
| 2438 | ARM64_REG_Q11_Q12_Q13 = AARCH64_REG_Q11_Q12_Q13, |
| 2439 | ARM64_REG_Q12_Q13_Q14 = AARCH64_REG_Q12_Q13_Q14, |
| 2440 | ARM64_REG_Q13_Q14_Q15 = AARCH64_REG_Q13_Q14_Q15, |
| 2441 | ARM64_REG_Q14_Q15_Q16 = AARCH64_REG_Q14_Q15_Q16, |
| 2442 | ARM64_REG_Q15_Q16_Q17 = AARCH64_REG_Q15_Q16_Q17, |
| 2443 | ARM64_REG_Q16_Q17_Q18 = AARCH64_REG_Q16_Q17_Q18, |
| 2444 | ARM64_REG_Q17_Q18_Q19 = AARCH64_REG_Q17_Q18_Q19, |
| 2445 | ARM64_REG_Q18_Q19_Q20 = AARCH64_REG_Q18_Q19_Q20, |
| 2446 | ARM64_REG_Q19_Q20_Q21 = AARCH64_REG_Q19_Q20_Q21, |
| 2447 | ARM64_REG_Q20_Q21_Q22 = AARCH64_REG_Q20_Q21_Q22, |
| 2448 | ARM64_REG_Q21_Q22_Q23 = AARCH64_REG_Q21_Q22_Q23, |
| 2449 | ARM64_REG_Q22_Q23_Q24 = AARCH64_REG_Q22_Q23_Q24, |
| 2450 | ARM64_REG_Q23_Q24_Q25 = AARCH64_REG_Q23_Q24_Q25, |
| 2451 | ARM64_REG_Q24_Q25_Q26 = AARCH64_REG_Q24_Q25_Q26, |
| 2452 | ARM64_REG_Q25_Q26_Q27 = AARCH64_REG_Q25_Q26_Q27, |
| 2453 | ARM64_REG_Q26_Q27_Q28 = AARCH64_REG_Q26_Q27_Q28, |
| 2454 | ARM64_REG_Q27_Q28_Q29 = AARCH64_REG_Q27_Q28_Q29, |
| 2455 | ARM64_REG_Q28_Q29_Q30 = AARCH64_REG_Q28_Q29_Q30, |
| 2456 | ARM64_REG_Q29_Q30_Q31 = AARCH64_REG_Q29_Q30_Q31, |
| 2457 | ARM64_REG_Q30_Q31_Q0 = AARCH64_REG_Q30_Q31_Q0, |
| 2458 | ARM64_REG_Q31_Q0_Q1 = AARCH64_REG_Q31_Q0_Q1, |
| 2459 | ARM64_REG_X22_X23_X24_X25_X26_X27_X28_FP = AARCH64_REG_X22_X23_X24_X25_X26_X27_X28_FP, |
| 2460 | ARM64_REG_X0_X1_X2_X3_X4_X5_X6_X7 = AARCH64_REG_X0_X1_X2_X3_X4_X5_X6_X7, |
| 2461 | ARM64_REG_X2_X3_X4_X5_X6_X7_X8_X9 = AARCH64_REG_X2_X3_X4_X5_X6_X7_X8_X9, |
| 2462 | ARM64_REG_X4_X5_X6_X7_X8_X9_X10_X11 = AARCH64_REG_X4_X5_X6_X7_X8_X9_X10_X11, |
| 2463 | ARM64_REG_X6_X7_X8_X9_X10_X11_X12_X13 = AARCH64_REG_X6_X7_X8_X9_X10_X11_X12_X13, |
| 2464 | ARM64_REG_X8_X9_X10_X11_X12_X13_X14_X15 = AARCH64_REG_X8_X9_X10_X11_X12_X13_X14_X15, |
| 2465 | ARM64_REG_X10_X11_X12_X13_X14_X15_X16_X17 = AARCH64_REG_X10_X11_X12_X13_X14_X15_X16_X17, |
| 2466 | ARM64_REG_X12_X13_X14_X15_X16_X17_X18_X19 = AARCH64_REG_X12_X13_X14_X15_X16_X17_X18_X19, |
| 2467 | ARM64_REG_X14_X15_X16_X17_X18_X19_X20_X21 = AARCH64_REG_X14_X15_X16_X17_X18_X19_X20_X21, |
| 2468 | ARM64_REG_X16_X17_X18_X19_X20_X21_X22_X23 = AARCH64_REG_X16_X17_X18_X19_X20_X21_X22_X23, |
| 2469 | ARM64_REG_X18_X19_X20_X21_X22_X23_X24_X25 = AARCH64_REG_X18_X19_X20_X21_X22_X23_X24_X25, |
| 2470 | ARM64_REG_X20_X21_X22_X23_X24_X25_X26_X27 = AARCH64_REG_X20_X21_X22_X23_X24_X25_X26_X27, |
| 2471 | ARM64_REG_W30_WZR = AARCH64_REG_W30_WZR, |
| 2472 | ARM64_REG_W0_W1 = AARCH64_REG_W0_W1, |
| 2473 | ARM64_REG_W2_W3 = AARCH64_REG_W2_W3, |
| 2474 | ARM64_REG_W4_W5 = AARCH64_REG_W4_W5, |
| 2475 | ARM64_REG_W6_W7 = AARCH64_REG_W6_W7, |
| 2476 | ARM64_REG_W8_W9 = AARCH64_REG_W8_W9, |
| 2477 | ARM64_REG_W10_W11 = AARCH64_REG_W10_W11, |
| 2478 | ARM64_REG_W12_W13 = AARCH64_REG_W12_W13, |
| 2479 | ARM64_REG_W14_W15 = AARCH64_REG_W14_W15, |
| 2480 | ARM64_REG_W16_W17 = AARCH64_REG_W16_W17, |
| 2481 | ARM64_REG_W18_W19 = AARCH64_REG_W18_W19, |
| 2482 | ARM64_REG_W20_W21 = AARCH64_REG_W20_W21, |
| 2483 | ARM64_REG_W22_W23 = AARCH64_REG_W22_W23, |
| 2484 | ARM64_REG_W24_W25 = AARCH64_REG_W24_W25, |
| 2485 | ARM64_REG_W26_W27 = AARCH64_REG_W26_W27, |
| 2486 | ARM64_REG_W28_W29 = AARCH64_REG_W28_W29, |
| 2487 | ARM64_REG_LR_XZR = AARCH64_REG_LR_XZR, |
| 2488 | ARM64_REG_X28_FP = AARCH64_REG_X28_FP, |
| 2489 | ARM64_REG_X0_X1 = AARCH64_REG_X0_X1, |
| 2490 | ARM64_REG_X2_X3 = AARCH64_REG_X2_X3, |
| 2491 | ARM64_REG_X4_X5 = AARCH64_REG_X4_X5, |
| 2492 | ARM64_REG_X6_X7 = AARCH64_REG_X6_X7, |
| 2493 | ARM64_REG_X8_X9 = AARCH64_REG_X8_X9, |
| 2494 | ARM64_REG_X10_X11 = AARCH64_REG_X10_X11, |
| 2495 | ARM64_REG_X12_X13 = AARCH64_REG_X12_X13, |
| 2496 | ARM64_REG_X14_X15 = AARCH64_REG_X14_X15, |
| 2497 | ARM64_REG_X16_X17 = AARCH64_REG_X16_X17, |
| 2498 | ARM64_REG_X18_X19 = AARCH64_REG_X18_X19, |
| 2499 | ARM64_REG_X20_X21 = AARCH64_REG_X20_X21, |
| 2500 | ARM64_REG_X22_X23 = AARCH64_REG_X22_X23, |
| 2501 | ARM64_REG_X24_X25 = AARCH64_REG_X24_X25, |
| 2502 | ARM64_REG_X26_X27 = AARCH64_REG_X26_X27, |
| 2503 | ARM64_REG_Z0_Z1 = AARCH64_REG_Z0_Z1, |
| 2504 | ARM64_REG_Z1_Z2 = AARCH64_REG_Z1_Z2, |
| 2505 | ARM64_REG_Z2_Z3 = AARCH64_REG_Z2_Z3, |
| 2506 | ARM64_REG_Z3_Z4 = AARCH64_REG_Z3_Z4, |
| 2507 | ARM64_REG_Z4_Z5 = AARCH64_REG_Z4_Z5, |
| 2508 | ARM64_REG_Z5_Z6 = AARCH64_REG_Z5_Z6, |
| 2509 | ARM64_REG_Z6_Z7 = AARCH64_REG_Z6_Z7, |
| 2510 | ARM64_REG_Z7_Z8 = AARCH64_REG_Z7_Z8, |
| 2511 | ARM64_REG_Z8_Z9 = AARCH64_REG_Z8_Z9, |
| 2512 | ARM64_REG_Z9_Z10 = AARCH64_REG_Z9_Z10, |
| 2513 | ARM64_REG_Z10_Z11 = AARCH64_REG_Z10_Z11, |
| 2514 | ARM64_REG_Z11_Z12 = AARCH64_REG_Z11_Z12, |
| 2515 | ARM64_REG_Z12_Z13 = AARCH64_REG_Z12_Z13, |
| 2516 | ARM64_REG_Z13_Z14 = AARCH64_REG_Z13_Z14, |
| 2517 | ARM64_REG_Z14_Z15 = AARCH64_REG_Z14_Z15, |
| 2518 | ARM64_REG_Z15_Z16 = AARCH64_REG_Z15_Z16, |
| 2519 | ARM64_REG_Z16_Z17 = AARCH64_REG_Z16_Z17, |
| 2520 | ARM64_REG_Z17_Z18 = AARCH64_REG_Z17_Z18, |
| 2521 | ARM64_REG_Z18_Z19 = AARCH64_REG_Z18_Z19, |
| 2522 | ARM64_REG_Z19_Z20 = AARCH64_REG_Z19_Z20, |
| 2523 | ARM64_REG_Z20_Z21 = AARCH64_REG_Z20_Z21, |
| 2524 | ARM64_REG_Z21_Z22 = AARCH64_REG_Z21_Z22, |
| 2525 | ARM64_REG_Z22_Z23 = AARCH64_REG_Z22_Z23, |
| 2526 | ARM64_REG_Z23_Z24 = AARCH64_REG_Z23_Z24, |
| 2527 | ARM64_REG_Z24_Z25 = AARCH64_REG_Z24_Z25, |
| 2528 | ARM64_REG_Z25_Z26 = AARCH64_REG_Z25_Z26, |
| 2529 | ARM64_REG_Z26_Z27 = AARCH64_REG_Z26_Z27, |
| 2530 | ARM64_REG_Z27_Z28 = AARCH64_REG_Z27_Z28, |
| 2531 | ARM64_REG_Z28_Z29 = AARCH64_REG_Z28_Z29, |
| 2532 | ARM64_REG_Z29_Z30 = AARCH64_REG_Z29_Z30, |
| 2533 | ARM64_REG_Z30_Z31 = AARCH64_REG_Z30_Z31, |
| 2534 | ARM64_REG_Z31_Z0 = AARCH64_REG_Z31_Z0, |
| 2535 | ARM64_REG_Z0_Z1_Z2_Z3 = AARCH64_REG_Z0_Z1_Z2_Z3, |
| 2536 | ARM64_REG_Z1_Z2_Z3_Z4 = AARCH64_REG_Z1_Z2_Z3_Z4, |
| 2537 | ARM64_REG_Z2_Z3_Z4_Z5 = AARCH64_REG_Z2_Z3_Z4_Z5, |
| 2538 | ARM64_REG_Z3_Z4_Z5_Z6 = AARCH64_REG_Z3_Z4_Z5_Z6, |
| 2539 | ARM64_REG_Z4_Z5_Z6_Z7 = AARCH64_REG_Z4_Z5_Z6_Z7, |
| 2540 | ARM64_REG_Z5_Z6_Z7_Z8 = AARCH64_REG_Z5_Z6_Z7_Z8, |
| 2541 | ARM64_REG_Z6_Z7_Z8_Z9 = AARCH64_REG_Z6_Z7_Z8_Z9, |
| 2542 | ARM64_REG_Z7_Z8_Z9_Z10 = AARCH64_REG_Z7_Z8_Z9_Z10, |
| 2543 | ARM64_REG_Z8_Z9_Z10_Z11 = AARCH64_REG_Z8_Z9_Z10_Z11, |
| 2544 | ARM64_REG_Z9_Z10_Z11_Z12 = AARCH64_REG_Z9_Z10_Z11_Z12, |
| 2545 | ARM64_REG_Z10_Z11_Z12_Z13 = AARCH64_REG_Z10_Z11_Z12_Z13, |
| 2546 | ARM64_REG_Z11_Z12_Z13_Z14 = AARCH64_REG_Z11_Z12_Z13_Z14, |
| 2547 | ARM64_REG_Z12_Z13_Z14_Z15 = AARCH64_REG_Z12_Z13_Z14_Z15, |
| 2548 | ARM64_REG_Z13_Z14_Z15_Z16 = AARCH64_REG_Z13_Z14_Z15_Z16, |
| 2549 | ARM64_REG_Z14_Z15_Z16_Z17 = AARCH64_REG_Z14_Z15_Z16_Z17, |
| 2550 | ARM64_REG_Z15_Z16_Z17_Z18 = AARCH64_REG_Z15_Z16_Z17_Z18, |
| 2551 | ARM64_REG_Z16_Z17_Z18_Z19 = AARCH64_REG_Z16_Z17_Z18_Z19, |
| 2552 | ARM64_REG_Z17_Z18_Z19_Z20 = AARCH64_REG_Z17_Z18_Z19_Z20, |
| 2553 | ARM64_REG_Z18_Z19_Z20_Z21 = AARCH64_REG_Z18_Z19_Z20_Z21, |
| 2554 | ARM64_REG_Z19_Z20_Z21_Z22 = AARCH64_REG_Z19_Z20_Z21_Z22, |
| 2555 | ARM64_REG_Z20_Z21_Z22_Z23 = AARCH64_REG_Z20_Z21_Z22_Z23, |
| 2556 | ARM64_REG_Z21_Z22_Z23_Z24 = AARCH64_REG_Z21_Z22_Z23_Z24, |
| 2557 | ARM64_REG_Z22_Z23_Z24_Z25 = AARCH64_REG_Z22_Z23_Z24_Z25, |
| 2558 | ARM64_REG_Z23_Z24_Z25_Z26 = AARCH64_REG_Z23_Z24_Z25_Z26, |
| 2559 | ARM64_REG_Z24_Z25_Z26_Z27 = AARCH64_REG_Z24_Z25_Z26_Z27, |
| 2560 | ARM64_REG_Z25_Z26_Z27_Z28 = AARCH64_REG_Z25_Z26_Z27_Z28, |
| 2561 | ARM64_REG_Z26_Z27_Z28_Z29 = AARCH64_REG_Z26_Z27_Z28_Z29, |
| 2562 | ARM64_REG_Z27_Z28_Z29_Z30 = AARCH64_REG_Z27_Z28_Z29_Z30, |
| 2563 | ARM64_REG_Z28_Z29_Z30_Z31 = AARCH64_REG_Z28_Z29_Z30_Z31, |
| 2564 | ARM64_REG_Z29_Z30_Z31_Z0 = AARCH64_REG_Z29_Z30_Z31_Z0, |
| 2565 | ARM64_REG_Z30_Z31_Z0_Z1 = AARCH64_REG_Z30_Z31_Z0_Z1, |
| 2566 | ARM64_REG_Z31_Z0_Z1_Z2 = AARCH64_REG_Z31_Z0_Z1_Z2, |
| 2567 | ARM64_REG_Z0_Z1_Z2 = AARCH64_REG_Z0_Z1_Z2, |
| 2568 | ARM64_REG_Z1_Z2_Z3 = AARCH64_REG_Z1_Z2_Z3, |
| 2569 | ARM64_REG_Z2_Z3_Z4 = AARCH64_REG_Z2_Z3_Z4, |
| 2570 | ARM64_REG_Z3_Z4_Z5 = AARCH64_REG_Z3_Z4_Z5, |
| 2571 | ARM64_REG_Z4_Z5_Z6 = AARCH64_REG_Z4_Z5_Z6, |
| 2572 | ARM64_REG_Z5_Z6_Z7 = AARCH64_REG_Z5_Z6_Z7, |
| 2573 | ARM64_REG_Z6_Z7_Z8 = AARCH64_REG_Z6_Z7_Z8, |
| 2574 | ARM64_REG_Z7_Z8_Z9 = AARCH64_REG_Z7_Z8_Z9, |
| 2575 | ARM64_REG_Z8_Z9_Z10 = AARCH64_REG_Z8_Z9_Z10, |
| 2576 | ARM64_REG_Z9_Z10_Z11 = AARCH64_REG_Z9_Z10_Z11, |
| 2577 | ARM64_REG_Z10_Z11_Z12 = AARCH64_REG_Z10_Z11_Z12, |
| 2578 | ARM64_REG_Z11_Z12_Z13 = AARCH64_REG_Z11_Z12_Z13, |
| 2579 | ARM64_REG_Z12_Z13_Z14 = AARCH64_REG_Z12_Z13_Z14, |
| 2580 | ARM64_REG_Z13_Z14_Z15 = AARCH64_REG_Z13_Z14_Z15, |
| 2581 | ARM64_REG_Z14_Z15_Z16 = AARCH64_REG_Z14_Z15_Z16, |
| 2582 | ARM64_REG_Z15_Z16_Z17 = AARCH64_REG_Z15_Z16_Z17, |
| 2583 | ARM64_REG_Z16_Z17_Z18 = AARCH64_REG_Z16_Z17_Z18, |
| 2584 | ARM64_REG_Z17_Z18_Z19 = AARCH64_REG_Z17_Z18_Z19, |
| 2585 | ARM64_REG_Z18_Z19_Z20 = AARCH64_REG_Z18_Z19_Z20, |
| 2586 | ARM64_REG_Z19_Z20_Z21 = AARCH64_REG_Z19_Z20_Z21, |
| 2587 | ARM64_REG_Z20_Z21_Z22 = AARCH64_REG_Z20_Z21_Z22, |
| 2588 | ARM64_REG_Z21_Z22_Z23 = AARCH64_REG_Z21_Z22_Z23, |
| 2589 | ARM64_REG_Z22_Z23_Z24 = AARCH64_REG_Z22_Z23_Z24, |
| 2590 | ARM64_REG_Z23_Z24_Z25 = AARCH64_REG_Z23_Z24_Z25, |
| 2591 | ARM64_REG_Z24_Z25_Z26 = AARCH64_REG_Z24_Z25_Z26, |
| 2592 | ARM64_REG_Z25_Z26_Z27 = AARCH64_REG_Z25_Z26_Z27, |
| 2593 | ARM64_REG_Z26_Z27_Z28 = AARCH64_REG_Z26_Z27_Z28, |
| 2594 | ARM64_REG_Z27_Z28_Z29 = AARCH64_REG_Z27_Z28_Z29, |
| 2595 | ARM64_REG_Z28_Z29_Z30 = AARCH64_REG_Z28_Z29_Z30, |
| 2596 | ARM64_REG_Z29_Z30_Z31 = AARCH64_REG_Z29_Z30_Z31, |
| 2597 | ARM64_REG_Z30_Z31_Z0 = AARCH64_REG_Z30_Z31_Z0, |
| 2598 | ARM64_REG_Z31_Z0_Z1 = AARCH64_REG_Z31_Z0_Z1, |
| 2599 | ARM64_REG_Z16_Z24 = AARCH64_REG_Z16_Z24, |
| 2600 | ARM64_REG_Z17_Z25 = AARCH64_REG_Z17_Z25, |
| 2601 | ARM64_REG_Z18_Z26 = AARCH64_REG_Z18_Z26, |
| 2602 | ARM64_REG_Z19_Z27 = AARCH64_REG_Z19_Z27, |
| 2603 | ARM64_REG_Z20_Z28 = AARCH64_REG_Z20_Z28, |
| 2604 | ARM64_REG_Z21_Z29 = AARCH64_REG_Z21_Z29, |
| 2605 | ARM64_REG_Z22_Z30 = AARCH64_REG_Z22_Z30, |
| 2606 | ARM64_REG_Z23_Z31 = AARCH64_REG_Z23_Z31, |
| 2607 | ARM64_REG_Z0_Z8 = AARCH64_REG_Z0_Z8, |
| 2608 | ARM64_REG_Z1_Z9 = AARCH64_REG_Z1_Z9, |
| 2609 | ARM64_REG_Z2_Z10 = AARCH64_REG_Z2_Z10, |
| 2610 | ARM64_REG_Z3_Z11 = AARCH64_REG_Z3_Z11, |
| 2611 | ARM64_REG_Z4_Z12 = AARCH64_REG_Z4_Z12, |
| 2612 | ARM64_REG_Z5_Z13 = AARCH64_REG_Z5_Z13, |
| 2613 | ARM64_REG_Z6_Z14 = AARCH64_REG_Z6_Z14, |
| 2614 | ARM64_REG_Z7_Z15 = AARCH64_REG_Z7_Z15, |
| 2615 | ARM64_REG_Z16_Z20_Z24_Z28 = AARCH64_REG_Z16_Z20_Z24_Z28, |
| 2616 | ARM64_REG_Z17_Z21_Z25_Z29 = AARCH64_REG_Z17_Z21_Z25_Z29, |
| 2617 | ARM64_REG_Z18_Z22_Z26_Z30 = AARCH64_REG_Z18_Z22_Z26_Z30, |
| 2618 | ARM64_REG_Z19_Z23_Z27_Z31 = AARCH64_REG_Z19_Z23_Z27_Z31, |
| 2619 | ARM64_REG_Z0_Z4_Z8_Z12 = AARCH64_REG_Z0_Z4_Z8_Z12, |
| 2620 | ARM64_REG_Z1_Z5_Z9_Z13 = AARCH64_REG_Z1_Z5_Z9_Z13, |
| 2621 | ARM64_REG_Z2_Z6_Z10_Z14 = AARCH64_REG_Z2_Z6_Z10_Z14, |
| 2622 | ARM64_REG_Z3_Z7_Z11_Z15 = AARCH64_REG_Z3_Z7_Z11_Z15, |
| 2623 | ARM64_REG_ENDING = AARCH64_REG_ENDING, |
| 2624 | |
| 2625 | |
| 2626 | ARM64_REG_IP0 = AARCH64_REG_IP0, |
| 2627 | ARM64_REG_IP1 = AARCH64_REG_IP1, |
| 2628 | ARM64_REG_X29 = AARCH64_REG_X29, |
| 2629 | ARM64_REG_X30 = AARCH64_REG_X30, |
| 2630 | } arm64_reg; |
| 2631 | |
| 2632 | typedef aarch64_op_mem arm64_op_mem; |
| 2633 | |
| 2634 | typedef enum { |
| 2635 | ARM64_SME_OP_INVALID = AARCH64_SME_OP_INVALID, |
| 2636 | ARM64_SME_OP_TILE = AARCH64_SME_OP_TILE, |
| 2637 | ARM64_SME_OP_TILE_VEC = AARCH64_SME_OP_TILE_VEC, |
| 2638 | } arm64_sme_op_type; |
| 2639 | |
| 2640 | #define ARM64_SLICE_IMM_INVALID UINT16_MAX |
| 2641 | #define ARM64_SLICE_IMM_RANGE_INVALID UINT8_MAX |
| 2642 | |
| 2643 | typedef aarch64_imm_range arm64_imm_range; |
| 2644 | |
| 2645 | typedef aarch64_op_sme arm64_op_sme; |
| 2646 | |
| 2647 | typedef aarch64_op_pred arm64_op_pred; |
| 2648 | |
| 2649 | typedef cs_aarch64_op cs_arm64_op; |
| 2650 | |
| 2651 | typedef aarch64_suppl_info arm64_suppl_info; |
| 2652 | |
| 2653 | #define NUM_ARM64_OPS 16 |
| 2654 | |
| 2655 | typedef cs_aarch64 cs_arm64; |
| 2656 | |
| 2657 | typedef enum { |
| 2658 | |
| 2659 | ARM64_INS_INVALID = AARCH64_INS_INVALID, |
| 2660 | ARM64_INS_ABS = AARCH64_INS_ABS, |
| 2661 | ARM64_INS_ADCLB = AARCH64_INS_ADCLB, |
| 2662 | ARM64_INS_ADCLT = AARCH64_INS_ADCLT, |
| 2663 | ARM64_INS_ADCS = AARCH64_INS_ADCS, |
| 2664 | ARM64_INS_ADC = AARCH64_INS_ADC, |
| 2665 | ARM64_INS_ADDG = AARCH64_INS_ADDG, |
| 2666 | ARM64_INS_ADDHA = AARCH64_INS_ADDHA, |
| 2667 | ARM64_INS_ADDHNB = AARCH64_INS_ADDHNB, |
| 2668 | ARM64_INS_ADDHNT = AARCH64_INS_ADDHNT, |
| 2669 | ARM64_INS_ADDHN = AARCH64_INS_ADDHN, |
| 2670 | ARM64_INS_ADDHN2 = AARCH64_INS_ADDHN2, |
| 2671 | ARM64_INS_ADDPL = AARCH64_INS_ADDPL, |
| 2672 | ARM64_INS_ADDPT = AARCH64_INS_ADDPT, |
| 2673 | ARM64_INS_ADDP = AARCH64_INS_ADDP, |
| 2674 | ARM64_INS_ADDQV = AARCH64_INS_ADDQV, |
| 2675 | ARM64_INS_ADDSPL = AARCH64_INS_ADDSPL, |
| 2676 | ARM64_INS_ADDSVL = AARCH64_INS_ADDSVL, |
| 2677 | ARM64_INS_ADDS = AARCH64_INS_ADDS, |
| 2678 | ARM64_INS_ADDVA = AARCH64_INS_ADDVA, |
| 2679 | ARM64_INS_ADDVL = AARCH64_INS_ADDVL, |
| 2680 | ARM64_INS_ADDV = AARCH64_INS_ADDV, |
| 2681 | ARM64_INS_ADD = AARCH64_INS_ADD, |
| 2682 | ARM64_INS_ADR = AARCH64_INS_ADR, |
| 2683 | ARM64_INS_ADRP = AARCH64_INS_ADRP, |
| 2684 | ARM64_INS_AESD = AARCH64_INS_AESD, |
| 2685 | ARM64_INS_AESE = AARCH64_INS_AESE, |
| 2686 | ARM64_INS_AESIMC = AARCH64_INS_AESIMC, |
| 2687 | ARM64_INS_AESMC = AARCH64_INS_AESMC, |
| 2688 | ARM64_INS_ANDQV = AARCH64_INS_ANDQV, |
| 2689 | ARM64_INS_ANDS = AARCH64_INS_ANDS, |
| 2690 | ARM64_INS_ANDV = AARCH64_INS_ANDV, |
| 2691 | ARM64_INS_AND = AARCH64_INS_AND, |
| 2692 | ARM64_INS_ASRD = AARCH64_INS_ASRD, |
| 2693 | ARM64_INS_ASRR = AARCH64_INS_ASRR, |
| 2694 | ARM64_INS_ASR = AARCH64_INS_ASR, |
| 2695 | ARM64_INS_AUTDA = AARCH64_INS_AUTDA, |
| 2696 | ARM64_INS_AUTDB = AARCH64_INS_AUTDB, |
| 2697 | ARM64_INS_AUTDZA = AARCH64_INS_AUTDZA, |
| 2698 | ARM64_INS_AUTDZB = AARCH64_INS_AUTDZB, |
| 2699 | ARM64_INS_AUTIA = AARCH64_INS_AUTIA, |
| 2700 | ARM64_INS_HINT = AARCH64_INS_HINT, |
| 2701 | ARM64_INS_AUTIA171615 = AARCH64_INS_AUTIA171615, |
| 2702 | ARM64_INS_AUTIASPPC = AARCH64_INS_AUTIASPPC, |
| 2703 | ARM64_INS_AUTIB = AARCH64_INS_AUTIB, |
| 2704 | ARM64_INS_AUTIB171615 = AARCH64_INS_AUTIB171615, |
| 2705 | ARM64_INS_AUTIBSPPC = AARCH64_INS_AUTIBSPPC, |
| 2706 | ARM64_INS_AUTIZA = AARCH64_INS_AUTIZA, |
| 2707 | ARM64_INS_AUTIZB = AARCH64_INS_AUTIZB, |
| 2708 | ARM64_INS_AXFLAG = AARCH64_INS_AXFLAG, |
| 2709 | ARM64_INS_B = AARCH64_INS_B, |
| 2710 | ARM64_INS_BCAX = AARCH64_INS_BCAX, |
| 2711 | ARM64_INS_BC = AARCH64_INS_BC, |
| 2712 | ARM64_INS_BDEP = AARCH64_INS_BDEP, |
| 2713 | ARM64_INS_BEXT = AARCH64_INS_BEXT, |
| 2714 | ARM64_INS_BFDOT = AARCH64_INS_BFDOT, |
| 2715 | ARM64_INS_BF1CVTL2 = AARCH64_INS_BF1CVTL2, |
| 2716 | ARM64_INS_BF1CVTLT = AARCH64_INS_BF1CVTLT, |
| 2717 | ARM64_INS_BF1CVTL = AARCH64_INS_BF1CVTL, |
| 2718 | ARM64_INS_BF1CVT = AARCH64_INS_BF1CVT, |
| 2719 | ARM64_INS_BF2CVTL2 = AARCH64_INS_BF2CVTL2, |
| 2720 | ARM64_INS_BF2CVTLT = AARCH64_INS_BF2CVTLT, |
| 2721 | ARM64_INS_BF2CVTL = AARCH64_INS_BF2CVTL, |
| 2722 | ARM64_INS_BF2CVT = AARCH64_INS_BF2CVT, |
| 2723 | ARM64_INS_BFADD = AARCH64_INS_BFADD, |
| 2724 | ARM64_INS_BFCLAMP = AARCH64_INS_BFCLAMP, |
| 2725 | ARM64_INS_BFCVT = AARCH64_INS_BFCVT, |
| 2726 | ARM64_INS_BFCVTN = AARCH64_INS_BFCVTN, |
| 2727 | ARM64_INS_BFCVTN2 = AARCH64_INS_BFCVTN2, |
| 2728 | ARM64_INS_BFCVTNT = AARCH64_INS_BFCVTNT, |
| 2729 | ARM64_INS_BFMAXNM = AARCH64_INS_BFMAXNM, |
| 2730 | ARM64_INS_BFMAX = AARCH64_INS_BFMAX, |
| 2731 | ARM64_INS_BFMINNM = AARCH64_INS_BFMINNM, |
| 2732 | ARM64_INS_BFMIN = AARCH64_INS_BFMIN, |
| 2733 | ARM64_INS_BFMLALB = AARCH64_INS_BFMLALB, |
| 2734 | ARM64_INS_BFMLALT = AARCH64_INS_BFMLALT, |
| 2735 | ARM64_INS_BFMLAL = AARCH64_INS_BFMLAL, |
| 2736 | ARM64_INS_BFMLA = AARCH64_INS_BFMLA, |
| 2737 | ARM64_INS_BFMLSLB = AARCH64_INS_BFMLSLB, |
| 2738 | ARM64_INS_BFMLSLT = AARCH64_INS_BFMLSLT, |
| 2739 | ARM64_INS_BFMLSL = AARCH64_INS_BFMLSL, |
| 2740 | ARM64_INS_BFMLS = AARCH64_INS_BFMLS, |
| 2741 | ARM64_INS_BFMMLA = AARCH64_INS_BFMMLA, |
| 2742 | ARM64_INS_BFMOPA = AARCH64_INS_BFMOPA, |
| 2743 | ARM64_INS_BFMOPS = AARCH64_INS_BFMOPS, |
| 2744 | ARM64_INS_BFMUL = AARCH64_INS_BFMUL, |
| 2745 | ARM64_INS_BFM = AARCH64_INS_BFM, |
| 2746 | ARM64_INS_BFSUB = AARCH64_INS_BFSUB, |
| 2747 | ARM64_INS_BFVDOT = AARCH64_INS_BFVDOT, |
| 2748 | ARM64_INS_BGRP = AARCH64_INS_BGRP, |
| 2749 | ARM64_INS_BICS = AARCH64_INS_BICS, |
| 2750 | ARM64_INS_BIC = AARCH64_INS_BIC, |
| 2751 | ARM64_INS_BIF = AARCH64_INS_BIF, |
| 2752 | ARM64_INS_BIT = AARCH64_INS_BIT, |
| 2753 | ARM64_INS_BL = AARCH64_INS_BL, |
| 2754 | ARM64_INS_BLR = AARCH64_INS_BLR, |
| 2755 | ARM64_INS_BLRAA = AARCH64_INS_BLRAA, |
| 2756 | ARM64_INS_BLRAAZ = AARCH64_INS_BLRAAZ, |
| 2757 | ARM64_INS_BLRAB = AARCH64_INS_BLRAB, |
| 2758 | ARM64_INS_BLRABZ = AARCH64_INS_BLRABZ, |
| 2759 | ARM64_INS_BMOPA = AARCH64_INS_BMOPA, |
| 2760 | ARM64_INS_BMOPS = AARCH64_INS_BMOPS, |
| 2761 | ARM64_INS_BR = AARCH64_INS_BR, |
| 2762 | ARM64_INS_BRAA = AARCH64_INS_BRAA, |
| 2763 | ARM64_INS_BRAAZ = AARCH64_INS_BRAAZ, |
| 2764 | ARM64_INS_BRAB = AARCH64_INS_BRAB, |
| 2765 | ARM64_INS_BRABZ = AARCH64_INS_BRABZ, |
| 2766 | ARM64_INS_BRB = AARCH64_INS_BRB, |
| 2767 | ARM64_INS_BRK = AARCH64_INS_BRK, |
| 2768 | ARM64_INS_BRKAS = AARCH64_INS_BRKAS, |
| 2769 | ARM64_INS_BRKA = AARCH64_INS_BRKA, |
| 2770 | ARM64_INS_BRKBS = AARCH64_INS_BRKBS, |
| 2771 | ARM64_INS_BRKB = AARCH64_INS_BRKB, |
| 2772 | ARM64_INS_BRKNS = AARCH64_INS_BRKNS, |
| 2773 | ARM64_INS_BRKN = AARCH64_INS_BRKN, |
| 2774 | ARM64_INS_BRKPAS = AARCH64_INS_BRKPAS, |
| 2775 | ARM64_INS_BRKPA = AARCH64_INS_BRKPA, |
| 2776 | ARM64_INS_BRKPBS = AARCH64_INS_BRKPBS, |
| 2777 | ARM64_INS_BRKPB = AARCH64_INS_BRKPB, |
| 2778 | ARM64_INS_BSL1N = AARCH64_INS_BSL1N, |
| 2779 | ARM64_INS_BSL2N = AARCH64_INS_BSL2N, |
| 2780 | ARM64_INS_BSL = AARCH64_INS_BSL, |
| 2781 | ARM64_INS_CADD = AARCH64_INS_CADD, |
| 2782 | ARM64_INS_CASAB = AARCH64_INS_CASAB, |
| 2783 | ARM64_INS_CASAH = AARCH64_INS_CASAH, |
| 2784 | ARM64_INS_CASALB = AARCH64_INS_CASALB, |
| 2785 | ARM64_INS_CASALH = AARCH64_INS_CASALH, |
| 2786 | ARM64_INS_CASAL = AARCH64_INS_CASAL, |
| 2787 | ARM64_INS_CASA = AARCH64_INS_CASA, |
| 2788 | ARM64_INS_CASB = AARCH64_INS_CASB, |
| 2789 | ARM64_INS_CASH = AARCH64_INS_CASH, |
| 2790 | ARM64_INS_CASLB = AARCH64_INS_CASLB, |
| 2791 | ARM64_INS_CASLH = AARCH64_INS_CASLH, |
| 2792 | ARM64_INS_CASL = AARCH64_INS_CASL, |
| 2793 | ARM64_INS_CASPAL = AARCH64_INS_CASPAL, |
| 2794 | ARM64_INS_CASPA = AARCH64_INS_CASPA, |
| 2795 | ARM64_INS_CASPL = AARCH64_INS_CASPL, |
| 2796 | ARM64_INS_CASP = AARCH64_INS_CASP, |
| 2797 | ARM64_INS_CAS = AARCH64_INS_CAS, |
| 2798 | ARM64_INS_CBNZ = AARCH64_INS_CBNZ, |
| 2799 | ARM64_INS_CBZ = AARCH64_INS_CBZ, |
| 2800 | ARM64_INS_CCMN = AARCH64_INS_CCMN, |
| 2801 | ARM64_INS_CCMP = AARCH64_INS_CCMP, |
| 2802 | ARM64_INS_CDOT = AARCH64_INS_CDOT, |
| 2803 | ARM64_INS_CFINV = AARCH64_INS_CFINV, |
| 2804 | ARM64_INS_CLASTA = AARCH64_INS_CLASTA, |
| 2805 | ARM64_INS_CLASTB = AARCH64_INS_CLASTB, |
| 2806 | ARM64_INS_CLREX = AARCH64_INS_CLREX, |
| 2807 | ARM64_INS_CLS = AARCH64_INS_CLS, |
| 2808 | ARM64_INS_CLZ = AARCH64_INS_CLZ, |
| 2809 | ARM64_INS_CMEQ = AARCH64_INS_CMEQ, |
| 2810 | ARM64_INS_CMGE = AARCH64_INS_CMGE, |
| 2811 | ARM64_INS_CMGT = AARCH64_INS_CMGT, |
| 2812 | ARM64_INS_CMHI = AARCH64_INS_CMHI, |
| 2813 | ARM64_INS_CMHS = AARCH64_INS_CMHS, |
| 2814 | ARM64_INS_CMLA = AARCH64_INS_CMLA, |
| 2815 | ARM64_INS_CMLE = AARCH64_INS_CMLE, |
| 2816 | ARM64_INS_CMLT = AARCH64_INS_CMLT, |
| 2817 | ARM64_INS_CMPEQ = AARCH64_INS_CMPEQ, |
| 2818 | ARM64_INS_CMPGE = AARCH64_INS_CMPGE, |
| 2819 | ARM64_INS_CMPGT = AARCH64_INS_CMPGT, |
| 2820 | ARM64_INS_CMPHI = AARCH64_INS_CMPHI, |
| 2821 | ARM64_INS_CMPHS = AARCH64_INS_CMPHS, |
| 2822 | ARM64_INS_CMPLE = AARCH64_INS_CMPLE, |
| 2823 | ARM64_INS_CMPLO = AARCH64_INS_CMPLO, |
| 2824 | ARM64_INS_CMPLS = AARCH64_INS_CMPLS, |
| 2825 | ARM64_INS_CMPLT = AARCH64_INS_CMPLT, |
| 2826 | ARM64_INS_CMPNE = AARCH64_INS_CMPNE, |
| 2827 | ARM64_INS_CMTST = AARCH64_INS_CMTST, |
| 2828 | ARM64_INS_CNOT = AARCH64_INS_CNOT, |
| 2829 | ARM64_INS_CNTB = AARCH64_INS_CNTB, |
| 2830 | ARM64_INS_CNTD = AARCH64_INS_CNTD, |
| 2831 | ARM64_INS_CNTH = AARCH64_INS_CNTH, |
| 2832 | ARM64_INS_CNTP = AARCH64_INS_CNTP, |
| 2833 | ARM64_INS_CNTW = AARCH64_INS_CNTW, |
| 2834 | ARM64_INS_CNT = AARCH64_INS_CNT, |
| 2835 | ARM64_INS_COMPACT = AARCH64_INS_COMPACT, |
| 2836 | ARM64_INS_CPYE = AARCH64_INS_CPYE, |
| 2837 | ARM64_INS_CPYEN = AARCH64_INS_CPYEN, |
| 2838 | ARM64_INS_CPYERN = AARCH64_INS_CPYERN, |
| 2839 | ARM64_INS_CPYERT = AARCH64_INS_CPYERT, |
| 2840 | ARM64_INS_CPYERTN = AARCH64_INS_CPYERTN, |
| 2841 | ARM64_INS_CPYERTRN = AARCH64_INS_CPYERTRN, |
| 2842 | ARM64_INS_CPYERTWN = AARCH64_INS_CPYERTWN, |
| 2843 | ARM64_INS_CPYET = AARCH64_INS_CPYET, |
| 2844 | ARM64_INS_CPYETN = AARCH64_INS_CPYETN, |
| 2845 | ARM64_INS_CPYETRN = AARCH64_INS_CPYETRN, |
| 2846 | ARM64_INS_CPYETWN = AARCH64_INS_CPYETWN, |
| 2847 | ARM64_INS_CPYEWN = AARCH64_INS_CPYEWN, |
| 2848 | ARM64_INS_CPYEWT = AARCH64_INS_CPYEWT, |
| 2849 | ARM64_INS_CPYEWTN = AARCH64_INS_CPYEWTN, |
| 2850 | ARM64_INS_CPYEWTRN = AARCH64_INS_CPYEWTRN, |
| 2851 | ARM64_INS_CPYEWTWN = AARCH64_INS_CPYEWTWN, |
| 2852 | ARM64_INS_CPYFE = AARCH64_INS_CPYFE, |
| 2853 | ARM64_INS_CPYFEN = AARCH64_INS_CPYFEN, |
| 2854 | ARM64_INS_CPYFERN = AARCH64_INS_CPYFERN, |
| 2855 | ARM64_INS_CPYFERT = AARCH64_INS_CPYFERT, |
| 2856 | ARM64_INS_CPYFERTN = AARCH64_INS_CPYFERTN, |
| 2857 | ARM64_INS_CPYFERTRN = AARCH64_INS_CPYFERTRN, |
| 2858 | ARM64_INS_CPYFERTWN = AARCH64_INS_CPYFERTWN, |
| 2859 | ARM64_INS_CPYFET = AARCH64_INS_CPYFET, |
| 2860 | ARM64_INS_CPYFETN = AARCH64_INS_CPYFETN, |
| 2861 | ARM64_INS_CPYFETRN = AARCH64_INS_CPYFETRN, |
| 2862 | ARM64_INS_CPYFETWN = AARCH64_INS_CPYFETWN, |
| 2863 | ARM64_INS_CPYFEWN = AARCH64_INS_CPYFEWN, |
| 2864 | ARM64_INS_CPYFEWT = AARCH64_INS_CPYFEWT, |
| 2865 | ARM64_INS_CPYFEWTN = AARCH64_INS_CPYFEWTN, |
| 2866 | ARM64_INS_CPYFEWTRN = AARCH64_INS_CPYFEWTRN, |
| 2867 | ARM64_INS_CPYFEWTWN = AARCH64_INS_CPYFEWTWN, |
| 2868 | ARM64_INS_CPYFM = AARCH64_INS_CPYFM, |
| 2869 | ARM64_INS_CPYFMN = AARCH64_INS_CPYFMN, |
| 2870 | ARM64_INS_CPYFMRN = AARCH64_INS_CPYFMRN, |
| 2871 | ARM64_INS_CPYFMRT = AARCH64_INS_CPYFMRT, |
| 2872 | ARM64_INS_CPYFMRTN = AARCH64_INS_CPYFMRTN, |
| 2873 | ARM64_INS_CPYFMRTRN = AARCH64_INS_CPYFMRTRN, |
| 2874 | ARM64_INS_CPYFMRTWN = AARCH64_INS_CPYFMRTWN, |
| 2875 | ARM64_INS_CPYFMT = AARCH64_INS_CPYFMT, |
| 2876 | ARM64_INS_CPYFMTN = AARCH64_INS_CPYFMTN, |
| 2877 | ARM64_INS_CPYFMTRN = AARCH64_INS_CPYFMTRN, |
| 2878 | ARM64_INS_CPYFMTWN = AARCH64_INS_CPYFMTWN, |
| 2879 | ARM64_INS_CPYFMWN = AARCH64_INS_CPYFMWN, |
| 2880 | ARM64_INS_CPYFMWT = AARCH64_INS_CPYFMWT, |
| 2881 | ARM64_INS_CPYFMWTN = AARCH64_INS_CPYFMWTN, |
| 2882 | ARM64_INS_CPYFMWTRN = AARCH64_INS_CPYFMWTRN, |
| 2883 | ARM64_INS_CPYFMWTWN = AARCH64_INS_CPYFMWTWN, |
| 2884 | ARM64_INS_CPYFP = AARCH64_INS_CPYFP, |
| 2885 | ARM64_INS_CPYFPN = AARCH64_INS_CPYFPN, |
| 2886 | ARM64_INS_CPYFPRN = AARCH64_INS_CPYFPRN, |
| 2887 | ARM64_INS_CPYFPRT = AARCH64_INS_CPYFPRT, |
| 2888 | ARM64_INS_CPYFPRTN = AARCH64_INS_CPYFPRTN, |
| 2889 | ARM64_INS_CPYFPRTRN = AARCH64_INS_CPYFPRTRN, |
| 2890 | ARM64_INS_CPYFPRTWN = AARCH64_INS_CPYFPRTWN, |
| 2891 | ARM64_INS_CPYFPT = AARCH64_INS_CPYFPT, |
| 2892 | ARM64_INS_CPYFPTN = AARCH64_INS_CPYFPTN, |
| 2893 | ARM64_INS_CPYFPTRN = AARCH64_INS_CPYFPTRN, |
| 2894 | ARM64_INS_CPYFPTWN = AARCH64_INS_CPYFPTWN, |
| 2895 | ARM64_INS_CPYFPWN = AARCH64_INS_CPYFPWN, |
| 2896 | ARM64_INS_CPYFPWT = AARCH64_INS_CPYFPWT, |
| 2897 | ARM64_INS_CPYFPWTN = AARCH64_INS_CPYFPWTN, |
| 2898 | ARM64_INS_CPYFPWTRN = AARCH64_INS_CPYFPWTRN, |
| 2899 | ARM64_INS_CPYFPWTWN = AARCH64_INS_CPYFPWTWN, |
| 2900 | ARM64_INS_CPYM = AARCH64_INS_CPYM, |
| 2901 | ARM64_INS_CPYMN = AARCH64_INS_CPYMN, |
| 2902 | ARM64_INS_CPYMRN = AARCH64_INS_CPYMRN, |
| 2903 | ARM64_INS_CPYMRT = AARCH64_INS_CPYMRT, |
| 2904 | ARM64_INS_CPYMRTN = AARCH64_INS_CPYMRTN, |
| 2905 | ARM64_INS_CPYMRTRN = AARCH64_INS_CPYMRTRN, |
| 2906 | ARM64_INS_CPYMRTWN = AARCH64_INS_CPYMRTWN, |
| 2907 | ARM64_INS_CPYMT = AARCH64_INS_CPYMT, |
| 2908 | ARM64_INS_CPYMTN = AARCH64_INS_CPYMTN, |
| 2909 | ARM64_INS_CPYMTRN = AARCH64_INS_CPYMTRN, |
| 2910 | ARM64_INS_CPYMTWN = AARCH64_INS_CPYMTWN, |
| 2911 | ARM64_INS_CPYMWN = AARCH64_INS_CPYMWN, |
| 2912 | ARM64_INS_CPYMWT = AARCH64_INS_CPYMWT, |
| 2913 | ARM64_INS_CPYMWTN = AARCH64_INS_CPYMWTN, |
| 2914 | ARM64_INS_CPYMWTRN = AARCH64_INS_CPYMWTRN, |
| 2915 | ARM64_INS_CPYMWTWN = AARCH64_INS_CPYMWTWN, |
| 2916 | ARM64_INS_CPYP = AARCH64_INS_CPYP, |
| 2917 | ARM64_INS_CPYPN = AARCH64_INS_CPYPN, |
| 2918 | ARM64_INS_CPYPRN = AARCH64_INS_CPYPRN, |
| 2919 | ARM64_INS_CPYPRT = AARCH64_INS_CPYPRT, |
| 2920 | ARM64_INS_CPYPRTN = AARCH64_INS_CPYPRTN, |
| 2921 | ARM64_INS_CPYPRTRN = AARCH64_INS_CPYPRTRN, |
| 2922 | ARM64_INS_CPYPRTWN = AARCH64_INS_CPYPRTWN, |
| 2923 | ARM64_INS_CPYPT = AARCH64_INS_CPYPT, |
| 2924 | ARM64_INS_CPYPTN = AARCH64_INS_CPYPTN, |
| 2925 | ARM64_INS_CPYPTRN = AARCH64_INS_CPYPTRN, |
| 2926 | ARM64_INS_CPYPTWN = AARCH64_INS_CPYPTWN, |
| 2927 | ARM64_INS_CPYPWN = AARCH64_INS_CPYPWN, |
| 2928 | ARM64_INS_CPYPWT = AARCH64_INS_CPYPWT, |
| 2929 | ARM64_INS_CPYPWTN = AARCH64_INS_CPYPWTN, |
| 2930 | ARM64_INS_CPYPWTRN = AARCH64_INS_CPYPWTRN, |
| 2931 | ARM64_INS_CPYPWTWN = AARCH64_INS_CPYPWTWN, |
| 2932 | ARM64_INS_CPY = AARCH64_INS_CPY, |
| 2933 | ARM64_INS_CRC32B = AARCH64_INS_CRC32B, |
| 2934 | ARM64_INS_CRC32CB = AARCH64_INS_CRC32CB, |
| 2935 | ARM64_INS_CRC32CH = AARCH64_INS_CRC32CH, |
| 2936 | ARM64_INS_CRC32CW = AARCH64_INS_CRC32CW, |
| 2937 | ARM64_INS_CRC32CX = AARCH64_INS_CRC32CX, |
| 2938 | ARM64_INS_CRC32H = AARCH64_INS_CRC32H, |
| 2939 | ARM64_INS_CRC32W = AARCH64_INS_CRC32W, |
| 2940 | ARM64_INS_CRC32X = AARCH64_INS_CRC32X, |
| 2941 | ARM64_INS_CSEL = AARCH64_INS_CSEL, |
| 2942 | ARM64_INS_CSINC = AARCH64_INS_CSINC, |
| 2943 | ARM64_INS_CSINV = AARCH64_INS_CSINV, |
| 2944 | ARM64_INS_CSNEG = AARCH64_INS_CSNEG, |
| 2945 | ARM64_INS_CTERMEQ = AARCH64_INS_CTERMEQ, |
| 2946 | ARM64_INS_CTERMNE = AARCH64_INS_CTERMNE, |
| 2947 | ARM64_INS_CTZ = AARCH64_INS_CTZ, |
| 2948 | ARM64_INS_DCPS1 = AARCH64_INS_DCPS1, |
| 2949 | ARM64_INS_DCPS2 = AARCH64_INS_DCPS2, |
| 2950 | ARM64_INS_DCPS3 = AARCH64_INS_DCPS3, |
| 2951 | ARM64_INS_DECB = AARCH64_INS_DECB, |
| 2952 | ARM64_INS_DECD = AARCH64_INS_DECD, |
| 2953 | ARM64_INS_DECH = AARCH64_INS_DECH, |
| 2954 | ARM64_INS_DECP = AARCH64_INS_DECP, |
| 2955 | ARM64_INS_DECW = AARCH64_INS_DECW, |
| 2956 | ARM64_INS_DMB = AARCH64_INS_DMB, |
| 2957 | ARM64_INS_DRPS = AARCH64_INS_DRPS, |
| 2958 | ARM64_INS_DSB = AARCH64_INS_DSB, |
| 2959 | ARM64_INS_DUPM = AARCH64_INS_DUPM, |
| 2960 | ARM64_INS_DUPQ = AARCH64_INS_DUPQ, |
| 2961 | ARM64_INS_DUP = AARCH64_INS_DUP, |
| 2962 | ARM64_INS_MOV = AARCH64_INS_MOV, |
| 2963 | ARM64_INS_EON = AARCH64_INS_EON, |
| 2964 | ARM64_INS_EOR3 = AARCH64_INS_EOR3, |
| 2965 | ARM64_INS_EORBT = AARCH64_INS_EORBT, |
| 2966 | ARM64_INS_EORQV = AARCH64_INS_EORQV, |
| 2967 | ARM64_INS_EORS = AARCH64_INS_EORS, |
| 2968 | ARM64_INS_EORTB = AARCH64_INS_EORTB, |
| 2969 | ARM64_INS_EORV = AARCH64_INS_EORV, |
| 2970 | ARM64_INS_EOR = AARCH64_INS_EOR, |
| 2971 | ARM64_INS_ERET = AARCH64_INS_ERET, |
| 2972 | ARM64_INS_ERETAA = AARCH64_INS_ERETAA, |
| 2973 | ARM64_INS_ERETAB = AARCH64_INS_ERETAB, |
| 2974 | ARM64_INS_EXTQ = AARCH64_INS_EXTQ, |
| 2975 | ARM64_INS_MOVA = AARCH64_INS_MOVA, |
| 2976 | ARM64_INS_EXTR = AARCH64_INS_EXTR, |
| 2977 | ARM64_INS_EXT = AARCH64_INS_EXT, |
| 2978 | ARM64_INS_F1CVTL2 = AARCH64_INS_F1CVTL2, |
| 2979 | ARM64_INS_F1CVTLT = AARCH64_INS_F1CVTLT, |
| 2980 | ARM64_INS_F1CVTL = AARCH64_INS_F1CVTL, |
| 2981 | ARM64_INS_F1CVT = AARCH64_INS_F1CVT, |
| 2982 | ARM64_INS_F2CVTL2 = AARCH64_INS_F2CVTL2, |
| 2983 | ARM64_INS_F2CVTLT = AARCH64_INS_F2CVTLT, |
| 2984 | ARM64_INS_F2CVTL = AARCH64_INS_F2CVTL, |
| 2985 | ARM64_INS_F2CVT = AARCH64_INS_F2CVT, |
| 2986 | ARM64_INS_FABD = AARCH64_INS_FABD, |
| 2987 | ARM64_INS_FABS = AARCH64_INS_FABS, |
| 2988 | ARM64_INS_FACGE = AARCH64_INS_FACGE, |
| 2989 | ARM64_INS_FACGT = AARCH64_INS_FACGT, |
| 2990 | ARM64_INS_FADDA = AARCH64_INS_FADDA, |
| 2991 | ARM64_INS_FADD = AARCH64_INS_FADD, |
| 2992 | ARM64_INS_FADDP = AARCH64_INS_FADDP, |
| 2993 | ARM64_INS_FADDQV = AARCH64_INS_FADDQV, |
| 2994 | ARM64_INS_FADDV = AARCH64_INS_FADDV, |
| 2995 | ARM64_INS_FAMAX = AARCH64_INS_FAMAX, |
| 2996 | ARM64_INS_FAMIN = AARCH64_INS_FAMIN, |
| 2997 | ARM64_INS_FCADD = AARCH64_INS_FCADD, |
| 2998 | ARM64_INS_FCCMP = AARCH64_INS_FCCMP, |
| 2999 | ARM64_INS_FCCMPE = AARCH64_INS_FCCMPE, |
| 3000 | ARM64_INS_FCLAMP = AARCH64_INS_FCLAMP, |
| 3001 | ARM64_INS_FCMEQ = AARCH64_INS_FCMEQ, |
| 3002 | ARM64_INS_FCMGE = AARCH64_INS_FCMGE, |
| 3003 | ARM64_INS_FCMGT = AARCH64_INS_FCMGT, |
| 3004 | ARM64_INS_FCMLA = AARCH64_INS_FCMLA, |
| 3005 | ARM64_INS_FCMLE = AARCH64_INS_FCMLE, |
| 3006 | ARM64_INS_FCMLT = AARCH64_INS_FCMLT, |
| 3007 | ARM64_INS_FCMNE = AARCH64_INS_FCMNE, |
| 3008 | ARM64_INS_FCMP = AARCH64_INS_FCMP, |
| 3009 | ARM64_INS_FCMPE = AARCH64_INS_FCMPE, |
| 3010 | ARM64_INS_FCMUO = AARCH64_INS_FCMUO, |
| 3011 | ARM64_INS_FCPY = AARCH64_INS_FCPY, |
| 3012 | ARM64_INS_FCSEL = AARCH64_INS_FCSEL, |
| 3013 | ARM64_INS_FCVTAS = AARCH64_INS_FCVTAS, |
| 3014 | ARM64_INS_FCVTAU = AARCH64_INS_FCVTAU, |
| 3015 | ARM64_INS_FCVT = AARCH64_INS_FCVT, |
| 3016 | ARM64_INS_FCVTLT = AARCH64_INS_FCVTLT, |
| 3017 | ARM64_INS_FCVTL = AARCH64_INS_FCVTL, |
| 3018 | ARM64_INS_FCVTL2 = AARCH64_INS_FCVTL2, |
| 3019 | ARM64_INS_FCVTMS = AARCH64_INS_FCVTMS, |
| 3020 | ARM64_INS_FCVTMU = AARCH64_INS_FCVTMU, |
| 3021 | ARM64_INS_FCVTNB = AARCH64_INS_FCVTNB, |
| 3022 | ARM64_INS_FCVTNS = AARCH64_INS_FCVTNS, |
| 3023 | ARM64_INS_FCVTNT = AARCH64_INS_FCVTNT, |
| 3024 | ARM64_INS_FCVTNU = AARCH64_INS_FCVTNU, |
| 3025 | ARM64_INS_FCVTN = AARCH64_INS_FCVTN, |
| 3026 | ARM64_INS_FCVTN2 = AARCH64_INS_FCVTN2, |
| 3027 | ARM64_INS_FCVTPS = AARCH64_INS_FCVTPS, |
| 3028 | ARM64_INS_FCVTPU = AARCH64_INS_FCVTPU, |
| 3029 | ARM64_INS_FCVTXNT = AARCH64_INS_FCVTXNT, |
| 3030 | ARM64_INS_FCVTXN = AARCH64_INS_FCVTXN, |
| 3031 | ARM64_INS_FCVTXN2 = AARCH64_INS_FCVTXN2, |
| 3032 | ARM64_INS_FCVTX = AARCH64_INS_FCVTX, |
| 3033 | ARM64_INS_FCVTZS = AARCH64_INS_FCVTZS, |
| 3034 | ARM64_INS_FCVTZU = AARCH64_INS_FCVTZU, |
| 3035 | ARM64_INS_FDIV = AARCH64_INS_FDIV, |
| 3036 | ARM64_INS_FDIVR = AARCH64_INS_FDIVR, |
| 3037 | ARM64_INS_FDOT = AARCH64_INS_FDOT, |
| 3038 | ARM64_INS_FDUP = AARCH64_INS_FDUP, |
| 3039 | ARM64_INS_FEXPA = AARCH64_INS_FEXPA, |
| 3040 | ARM64_INS_FJCVTZS = AARCH64_INS_FJCVTZS, |
| 3041 | ARM64_INS_FLOGB = AARCH64_INS_FLOGB, |
| 3042 | ARM64_INS_FMADD = AARCH64_INS_FMADD, |
| 3043 | ARM64_INS_FMAD = AARCH64_INS_FMAD, |
| 3044 | ARM64_INS_FMAX = AARCH64_INS_FMAX, |
| 3045 | ARM64_INS_FMAXNM = AARCH64_INS_FMAXNM, |
| 3046 | ARM64_INS_FMAXNMP = AARCH64_INS_FMAXNMP, |
| 3047 | ARM64_INS_FMAXNMQV = AARCH64_INS_FMAXNMQV, |
| 3048 | ARM64_INS_FMAXNMV = AARCH64_INS_FMAXNMV, |
| 3049 | ARM64_INS_FMAXP = AARCH64_INS_FMAXP, |
| 3050 | ARM64_INS_FMAXQV = AARCH64_INS_FMAXQV, |
| 3051 | ARM64_INS_FMAXV = AARCH64_INS_FMAXV, |
| 3052 | ARM64_INS_FMIN = AARCH64_INS_FMIN, |
| 3053 | ARM64_INS_FMINNM = AARCH64_INS_FMINNM, |
| 3054 | ARM64_INS_FMINNMP = AARCH64_INS_FMINNMP, |
| 3055 | ARM64_INS_FMINNMQV = AARCH64_INS_FMINNMQV, |
| 3056 | ARM64_INS_FMINNMV = AARCH64_INS_FMINNMV, |
| 3057 | ARM64_INS_FMINP = AARCH64_INS_FMINP, |
| 3058 | ARM64_INS_FMINQV = AARCH64_INS_FMINQV, |
| 3059 | ARM64_INS_FMINV = AARCH64_INS_FMINV, |
| 3060 | ARM64_INS_FMLAL2 = AARCH64_INS_FMLAL2, |
| 3061 | ARM64_INS_FMLALB = AARCH64_INS_FMLALB, |
| 3062 | ARM64_INS_FMLALLBB = AARCH64_INS_FMLALLBB, |
| 3063 | ARM64_INS_FMLALLBT = AARCH64_INS_FMLALLBT, |
| 3064 | ARM64_INS_FMLALLTB = AARCH64_INS_FMLALLTB, |
| 3065 | ARM64_INS_FMLALLTT = AARCH64_INS_FMLALLTT, |
| 3066 | ARM64_INS_FMLALL = AARCH64_INS_FMLALL, |
| 3067 | ARM64_INS_FMLALT = AARCH64_INS_FMLALT, |
| 3068 | ARM64_INS_FMLAL = AARCH64_INS_FMLAL, |
| 3069 | ARM64_INS_FMLA = AARCH64_INS_FMLA, |
| 3070 | ARM64_INS_FMLSL2 = AARCH64_INS_FMLSL2, |
| 3071 | ARM64_INS_FMLSLB = AARCH64_INS_FMLSLB, |
| 3072 | ARM64_INS_FMLSLT = AARCH64_INS_FMLSLT, |
| 3073 | ARM64_INS_FMLSL = AARCH64_INS_FMLSL, |
| 3074 | ARM64_INS_FMLS = AARCH64_INS_FMLS, |
| 3075 | ARM64_INS_FMMLA = AARCH64_INS_FMMLA, |
| 3076 | ARM64_INS_FMOPA = AARCH64_INS_FMOPA, |
| 3077 | ARM64_INS_FMOPS = AARCH64_INS_FMOPS, |
| 3078 | ARM64_INS_FMOV = AARCH64_INS_FMOV, |
| 3079 | ARM64_INS_FMSB = AARCH64_INS_FMSB, |
| 3080 | ARM64_INS_FMSUB = AARCH64_INS_FMSUB, |
| 3081 | ARM64_INS_FMUL = AARCH64_INS_FMUL, |
| 3082 | ARM64_INS_FMULX = AARCH64_INS_FMULX, |
| 3083 | ARM64_INS_FNEG = AARCH64_INS_FNEG, |
| 3084 | ARM64_INS_FNMADD = AARCH64_INS_FNMADD, |
| 3085 | ARM64_INS_FNMAD = AARCH64_INS_FNMAD, |
| 3086 | ARM64_INS_FNMLA = AARCH64_INS_FNMLA, |
| 3087 | ARM64_INS_FNMLS = AARCH64_INS_FNMLS, |
| 3088 | ARM64_INS_FNMSB = AARCH64_INS_FNMSB, |
| 3089 | ARM64_INS_FNMSUB = AARCH64_INS_FNMSUB, |
| 3090 | ARM64_INS_FNMUL = AARCH64_INS_FNMUL, |
| 3091 | ARM64_INS_FRECPE = AARCH64_INS_FRECPE, |
| 3092 | ARM64_INS_FRECPS = AARCH64_INS_FRECPS, |
| 3093 | ARM64_INS_FRECPX = AARCH64_INS_FRECPX, |
| 3094 | ARM64_INS_FRINT32X = AARCH64_INS_FRINT32X, |
| 3095 | ARM64_INS_FRINT32Z = AARCH64_INS_FRINT32Z, |
| 3096 | ARM64_INS_FRINT64X = AARCH64_INS_FRINT64X, |
| 3097 | ARM64_INS_FRINT64Z = AARCH64_INS_FRINT64Z, |
| 3098 | ARM64_INS_FRINTA = AARCH64_INS_FRINTA, |
| 3099 | ARM64_INS_FRINTI = AARCH64_INS_FRINTI, |
| 3100 | ARM64_INS_FRINTM = AARCH64_INS_FRINTM, |
| 3101 | ARM64_INS_FRINTN = AARCH64_INS_FRINTN, |
| 3102 | ARM64_INS_FRINTP = AARCH64_INS_FRINTP, |
| 3103 | ARM64_INS_FRINTX = AARCH64_INS_FRINTX, |
| 3104 | ARM64_INS_FRINTZ = AARCH64_INS_FRINTZ, |
| 3105 | ARM64_INS_FRSQRTE = AARCH64_INS_FRSQRTE, |
| 3106 | ARM64_INS_FRSQRTS = AARCH64_INS_FRSQRTS, |
| 3107 | ARM64_INS_FSCALE = AARCH64_INS_FSCALE, |
| 3108 | ARM64_INS_FSQRT = AARCH64_INS_FSQRT, |
| 3109 | ARM64_INS_FSUB = AARCH64_INS_FSUB, |
| 3110 | ARM64_INS_FSUBR = AARCH64_INS_FSUBR, |
| 3111 | ARM64_INS_FTMAD = AARCH64_INS_FTMAD, |
| 3112 | ARM64_INS_FTSMUL = AARCH64_INS_FTSMUL, |
| 3113 | ARM64_INS_FTSSEL = AARCH64_INS_FTSSEL, |
| 3114 | ARM64_INS_FVDOTB = AARCH64_INS_FVDOTB, |
| 3115 | ARM64_INS_FVDOTT = AARCH64_INS_FVDOTT, |
| 3116 | ARM64_INS_FVDOT = AARCH64_INS_FVDOT, |
| 3117 | ARM64_INS_GCSPOPCX = AARCH64_INS_GCSPOPCX, |
| 3118 | ARM64_INS_GCSPOPM = AARCH64_INS_GCSPOPM, |
| 3119 | ARM64_INS_GCSPOPX = AARCH64_INS_GCSPOPX, |
| 3120 | ARM64_INS_GCSPUSHM = AARCH64_INS_GCSPUSHM, |
| 3121 | ARM64_INS_GCSPUSHX = AARCH64_INS_GCSPUSHX, |
| 3122 | ARM64_INS_GCSSS1 = AARCH64_INS_GCSSS1, |
| 3123 | ARM64_INS_GCSSS2 = AARCH64_INS_GCSSS2, |
| 3124 | ARM64_INS_GCSSTR = AARCH64_INS_GCSSTR, |
| 3125 | ARM64_INS_GCSSTTR = AARCH64_INS_GCSSTTR, |
| 3126 | ARM64_INS_LD1B = AARCH64_INS_LD1B, |
| 3127 | ARM64_INS_LD1D = AARCH64_INS_LD1D, |
| 3128 | ARM64_INS_LD1H = AARCH64_INS_LD1H, |
| 3129 | ARM64_INS_LD1Q = AARCH64_INS_LD1Q, |
| 3130 | ARM64_INS_LD1SB = AARCH64_INS_LD1SB, |
| 3131 | ARM64_INS_LD1SH = AARCH64_INS_LD1SH, |
| 3132 | ARM64_INS_LD1SW = AARCH64_INS_LD1SW, |
| 3133 | ARM64_INS_LD1W = AARCH64_INS_LD1W, |
| 3134 | ARM64_INS_LDFF1B = AARCH64_INS_LDFF1B, |
| 3135 | ARM64_INS_LDFF1D = AARCH64_INS_LDFF1D, |
| 3136 | ARM64_INS_LDFF1H = AARCH64_INS_LDFF1H, |
| 3137 | ARM64_INS_LDFF1SB = AARCH64_INS_LDFF1SB, |
| 3138 | ARM64_INS_LDFF1SH = AARCH64_INS_LDFF1SH, |
| 3139 | ARM64_INS_LDFF1SW = AARCH64_INS_LDFF1SW, |
| 3140 | ARM64_INS_LDFF1W = AARCH64_INS_LDFF1W, |
| 3141 | ARM64_INS_GMI = AARCH64_INS_GMI, |
| 3142 | ARM64_INS_HISTCNT = AARCH64_INS_HISTCNT, |
| 3143 | ARM64_INS_HISTSEG = AARCH64_INS_HISTSEG, |
| 3144 | ARM64_INS_HLT = AARCH64_INS_HLT, |
| 3145 | ARM64_INS_HVC = AARCH64_INS_HVC, |
| 3146 | ARM64_INS_INCB = AARCH64_INS_INCB, |
| 3147 | ARM64_INS_INCD = AARCH64_INS_INCD, |
| 3148 | ARM64_INS_INCH = AARCH64_INS_INCH, |
| 3149 | ARM64_INS_INCP = AARCH64_INS_INCP, |
| 3150 | ARM64_INS_INCW = AARCH64_INS_INCW, |
| 3151 | ARM64_INS_INDEX = AARCH64_INS_INDEX, |
| 3152 | ARM64_INS_INSR = AARCH64_INS_INSR, |
| 3153 | ARM64_INS_INS = AARCH64_INS_INS, |
| 3154 | ARM64_INS_IRG = AARCH64_INS_IRG, |
| 3155 | ARM64_INS_ISB = AARCH64_INS_ISB, |
| 3156 | ARM64_INS_LASTA = AARCH64_INS_LASTA, |
| 3157 | ARM64_INS_LASTB = AARCH64_INS_LASTB, |
| 3158 | ARM64_INS_LD1 = AARCH64_INS_LD1, |
| 3159 | ARM64_INS_LD1RB = AARCH64_INS_LD1RB, |
| 3160 | ARM64_INS_LD1RD = AARCH64_INS_LD1RD, |
| 3161 | ARM64_INS_LD1RH = AARCH64_INS_LD1RH, |
| 3162 | ARM64_INS_LD1ROB = AARCH64_INS_LD1ROB, |
| 3163 | ARM64_INS_LD1ROD = AARCH64_INS_LD1ROD, |
| 3164 | ARM64_INS_LD1ROH = AARCH64_INS_LD1ROH, |
| 3165 | ARM64_INS_LD1ROW = AARCH64_INS_LD1ROW, |
| 3166 | ARM64_INS_LD1RQB = AARCH64_INS_LD1RQB, |
| 3167 | ARM64_INS_LD1RQD = AARCH64_INS_LD1RQD, |
| 3168 | ARM64_INS_LD1RQH = AARCH64_INS_LD1RQH, |
| 3169 | ARM64_INS_LD1RQW = AARCH64_INS_LD1RQW, |
| 3170 | ARM64_INS_LD1RSB = AARCH64_INS_LD1RSB, |
| 3171 | ARM64_INS_LD1RSH = AARCH64_INS_LD1RSH, |
| 3172 | ARM64_INS_LD1RSW = AARCH64_INS_LD1RSW, |
| 3173 | ARM64_INS_LD1RW = AARCH64_INS_LD1RW, |
| 3174 | ARM64_INS_LD1R = AARCH64_INS_LD1R, |
| 3175 | ARM64_INS_LD2B = AARCH64_INS_LD2B, |
| 3176 | ARM64_INS_LD2D = AARCH64_INS_LD2D, |
| 3177 | ARM64_INS_LD2H = AARCH64_INS_LD2H, |
| 3178 | ARM64_INS_LD2Q = AARCH64_INS_LD2Q, |
| 3179 | ARM64_INS_LD2R = AARCH64_INS_LD2R, |
| 3180 | ARM64_INS_LD2 = AARCH64_INS_LD2, |
| 3181 | ARM64_INS_LD2W = AARCH64_INS_LD2W, |
| 3182 | ARM64_INS_LD3B = AARCH64_INS_LD3B, |
| 3183 | ARM64_INS_LD3D = AARCH64_INS_LD3D, |
| 3184 | ARM64_INS_LD3H = AARCH64_INS_LD3H, |
| 3185 | ARM64_INS_LD3Q = AARCH64_INS_LD3Q, |
| 3186 | ARM64_INS_LD3R = AARCH64_INS_LD3R, |
| 3187 | ARM64_INS_LD3 = AARCH64_INS_LD3, |
| 3188 | ARM64_INS_LD3W = AARCH64_INS_LD3W, |
| 3189 | ARM64_INS_LD4B = AARCH64_INS_LD4B, |
| 3190 | ARM64_INS_LD4D = AARCH64_INS_LD4D, |
| 3191 | ARM64_INS_LD4 = AARCH64_INS_LD4, |
| 3192 | ARM64_INS_LD4H = AARCH64_INS_LD4H, |
| 3193 | ARM64_INS_LD4Q = AARCH64_INS_LD4Q, |
| 3194 | ARM64_INS_LD4R = AARCH64_INS_LD4R, |
| 3195 | ARM64_INS_LD4W = AARCH64_INS_LD4W, |
| 3196 | ARM64_INS_LD64B = AARCH64_INS_LD64B, |
| 3197 | ARM64_INS_LDADDAB = AARCH64_INS_LDADDAB, |
| 3198 | ARM64_INS_LDADDAH = AARCH64_INS_LDADDAH, |
| 3199 | ARM64_INS_LDADDALB = AARCH64_INS_LDADDALB, |
| 3200 | ARM64_INS_LDADDALH = AARCH64_INS_LDADDALH, |
| 3201 | ARM64_INS_LDADDAL = AARCH64_INS_LDADDAL, |
| 3202 | ARM64_INS_LDADDA = AARCH64_INS_LDADDA, |
| 3203 | ARM64_INS_LDADDB = AARCH64_INS_LDADDB, |
| 3204 | ARM64_INS_LDADDH = AARCH64_INS_LDADDH, |
| 3205 | ARM64_INS_LDADDLB = AARCH64_INS_LDADDLB, |
| 3206 | ARM64_INS_LDADDLH = AARCH64_INS_LDADDLH, |
| 3207 | ARM64_INS_LDADDL = AARCH64_INS_LDADDL, |
| 3208 | ARM64_INS_LDADD = AARCH64_INS_LDADD, |
| 3209 | ARM64_INS_LDAP1 = AARCH64_INS_LDAP1, |
| 3210 | ARM64_INS_LDAPRB = AARCH64_INS_LDAPRB, |
| 3211 | ARM64_INS_LDAPRH = AARCH64_INS_LDAPRH, |
| 3212 | ARM64_INS_LDAPR = AARCH64_INS_LDAPR, |
| 3213 | ARM64_INS_LDAPURB = AARCH64_INS_LDAPURB, |
| 3214 | ARM64_INS_LDAPURH = AARCH64_INS_LDAPURH, |
| 3215 | ARM64_INS_LDAPURSB = AARCH64_INS_LDAPURSB, |
| 3216 | ARM64_INS_LDAPURSH = AARCH64_INS_LDAPURSH, |
| 3217 | ARM64_INS_LDAPURSW = AARCH64_INS_LDAPURSW, |
| 3218 | ARM64_INS_LDAPUR = AARCH64_INS_LDAPUR, |
| 3219 | ARM64_INS_LDARB = AARCH64_INS_LDARB, |
| 3220 | ARM64_INS_LDARH = AARCH64_INS_LDARH, |
| 3221 | ARM64_INS_LDAR = AARCH64_INS_LDAR, |
| 3222 | ARM64_INS_LDAXP = AARCH64_INS_LDAXP, |
| 3223 | ARM64_INS_LDAXRB = AARCH64_INS_LDAXRB, |
| 3224 | ARM64_INS_LDAXRH = AARCH64_INS_LDAXRH, |
| 3225 | ARM64_INS_LDAXR = AARCH64_INS_LDAXR, |
| 3226 | ARM64_INS_LDCLRAB = AARCH64_INS_LDCLRAB, |
| 3227 | ARM64_INS_LDCLRAH = AARCH64_INS_LDCLRAH, |
| 3228 | ARM64_INS_LDCLRALB = AARCH64_INS_LDCLRALB, |
| 3229 | ARM64_INS_LDCLRALH = AARCH64_INS_LDCLRALH, |
| 3230 | ARM64_INS_LDCLRAL = AARCH64_INS_LDCLRAL, |
| 3231 | ARM64_INS_LDCLRA = AARCH64_INS_LDCLRA, |
| 3232 | ARM64_INS_LDCLRB = AARCH64_INS_LDCLRB, |
| 3233 | ARM64_INS_LDCLRH = AARCH64_INS_LDCLRH, |
| 3234 | ARM64_INS_LDCLRLB = AARCH64_INS_LDCLRLB, |
| 3235 | ARM64_INS_LDCLRLH = AARCH64_INS_LDCLRLH, |
| 3236 | ARM64_INS_LDCLRL = AARCH64_INS_LDCLRL, |
| 3237 | ARM64_INS_LDCLRP = AARCH64_INS_LDCLRP, |
| 3238 | ARM64_INS_LDCLRPA = AARCH64_INS_LDCLRPA, |
| 3239 | ARM64_INS_LDCLRPAL = AARCH64_INS_LDCLRPAL, |
| 3240 | ARM64_INS_LDCLRPL = AARCH64_INS_LDCLRPL, |
| 3241 | ARM64_INS_LDCLR = AARCH64_INS_LDCLR, |
| 3242 | ARM64_INS_LDEORAB = AARCH64_INS_LDEORAB, |
| 3243 | ARM64_INS_LDEORAH = AARCH64_INS_LDEORAH, |
| 3244 | ARM64_INS_LDEORALB = AARCH64_INS_LDEORALB, |
| 3245 | ARM64_INS_LDEORALH = AARCH64_INS_LDEORALH, |
| 3246 | ARM64_INS_LDEORAL = AARCH64_INS_LDEORAL, |
| 3247 | ARM64_INS_LDEORA = AARCH64_INS_LDEORA, |
| 3248 | ARM64_INS_LDEORB = AARCH64_INS_LDEORB, |
| 3249 | ARM64_INS_LDEORH = AARCH64_INS_LDEORH, |
| 3250 | ARM64_INS_LDEORLB = AARCH64_INS_LDEORLB, |
| 3251 | ARM64_INS_LDEORLH = AARCH64_INS_LDEORLH, |
| 3252 | ARM64_INS_LDEORL = AARCH64_INS_LDEORL, |
| 3253 | ARM64_INS_LDEOR = AARCH64_INS_LDEOR, |
| 3254 | ARM64_INS_LDG = AARCH64_INS_LDG, |
| 3255 | ARM64_INS_LDGM = AARCH64_INS_LDGM, |
| 3256 | ARM64_INS_LDIAPP = AARCH64_INS_LDIAPP, |
| 3257 | ARM64_INS_LDLARB = AARCH64_INS_LDLARB, |
| 3258 | ARM64_INS_LDLARH = AARCH64_INS_LDLARH, |
| 3259 | ARM64_INS_LDLAR = AARCH64_INS_LDLAR, |
| 3260 | ARM64_INS_LDNF1B = AARCH64_INS_LDNF1B, |
| 3261 | ARM64_INS_LDNF1D = AARCH64_INS_LDNF1D, |
| 3262 | ARM64_INS_LDNF1H = AARCH64_INS_LDNF1H, |
| 3263 | ARM64_INS_LDNF1SB = AARCH64_INS_LDNF1SB, |
| 3264 | ARM64_INS_LDNF1SH = AARCH64_INS_LDNF1SH, |
| 3265 | ARM64_INS_LDNF1SW = AARCH64_INS_LDNF1SW, |
| 3266 | ARM64_INS_LDNF1W = AARCH64_INS_LDNF1W, |
| 3267 | ARM64_INS_LDNP = AARCH64_INS_LDNP, |
| 3268 | ARM64_INS_LDNT1B = AARCH64_INS_LDNT1B, |
| 3269 | ARM64_INS_LDNT1D = AARCH64_INS_LDNT1D, |
| 3270 | ARM64_INS_LDNT1H = AARCH64_INS_LDNT1H, |
| 3271 | ARM64_INS_LDNT1SB = AARCH64_INS_LDNT1SB, |
| 3272 | ARM64_INS_LDNT1SH = AARCH64_INS_LDNT1SH, |
| 3273 | ARM64_INS_LDNT1SW = AARCH64_INS_LDNT1SW, |
| 3274 | ARM64_INS_LDNT1W = AARCH64_INS_LDNT1W, |
| 3275 | ARM64_INS_LDP = AARCH64_INS_LDP, |
| 3276 | ARM64_INS_LDPSW = AARCH64_INS_LDPSW, |
| 3277 | ARM64_INS_LDRAA = AARCH64_INS_LDRAA, |
| 3278 | ARM64_INS_LDRAB = AARCH64_INS_LDRAB, |
| 3279 | ARM64_INS_LDRB = AARCH64_INS_LDRB, |
| 3280 | ARM64_INS_LDR = AARCH64_INS_LDR, |
| 3281 | ARM64_INS_LDRH = AARCH64_INS_LDRH, |
| 3282 | ARM64_INS_LDRSB = AARCH64_INS_LDRSB, |
| 3283 | ARM64_INS_LDRSH = AARCH64_INS_LDRSH, |
| 3284 | ARM64_INS_LDRSW = AARCH64_INS_LDRSW, |
| 3285 | ARM64_INS_LDSETAB = AARCH64_INS_LDSETAB, |
| 3286 | ARM64_INS_LDSETAH = AARCH64_INS_LDSETAH, |
| 3287 | ARM64_INS_LDSETALB = AARCH64_INS_LDSETALB, |
| 3288 | ARM64_INS_LDSETALH = AARCH64_INS_LDSETALH, |
| 3289 | ARM64_INS_LDSETAL = AARCH64_INS_LDSETAL, |
| 3290 | ARM64_INS_LDSETA = AARCH64_INS_LDSETA, |
| 3291 | ARM64_INS_LDSETB = AARCH64_INS_LDSETB, |
| 3292 | ARM64_INS_LDSETH = AARCH64_INS_LDSETH, |
| 3293 | ARM64_INS_LDSETLB = AARCH64_INS_LDSETLB, |
| 3294 | ARM64_INS_LDSETLH = AARCH64_INS_LDSETLH, |
| 3295 | ARM64_INS_LDSETL = AARCH64_INS_LDSETL, |
| 3296 | ARM64_INS_LDSETP = AARCH64_INS_LDSETP, |
| 3297 | ARM64_INS_LDSETPA = AARCH64_INS_LDSETPA, |
| 3298 | ARM64_INS_LDSETPAL = AARCH64_INS_LDSETPAL, |
| 3299 | ARM64_INS_LDSETPL = AARCH64_INS_LDSETPL, |
| 3300 | ARM64_INS_LDSET = AARCH64_INS_LDSET, |
| 3301 | ARM64_INS_LDSMAXAB = AARCH64_INS_LDSMAXAB, |
| 3302 | ARM64_INS_LDSMAXAH = AARCH64_INS_LDSMAXAH, |
| 3303 | ARM64_INS_LDSMAXALB = AARCH64_INS_LDSMAXALB, |
| 3304 | ARM64_INS_LDSMAXALH = AARCH64_INS_LDSMAXALH, |
| 3305 | ARM64_INS_LDSMAXAL = AARCH64_INS_LDSMAXAL, |
| 3306 | ARM64_INS_LDSMAXA = AARCH64_INS_LDSMAXA, |
| 3307 | ARM64_INS_LDSMAXB = AARCH64_INS_LDSMAXB, |
| 3308 | ARM64_INS_LDSMAXH = AARCH64_INS_LDSMAXH, |
| 3309 | ARM64_INS_LDSMAXLB = AARCH64_INS_LDSMAXLB, |
| 3310 | ARM64_INS_LDSMAXLH = AARCH64_INS_LDSMAXLH, |
| 3311 | ARM64_INS_LDSMAXL = AARCH64_INS_LDSMAXL, |
| 3312 | ARM64_INS_LDSMAX = AARCH64_INS_LDSMAX, |
| 3313 | ARM64_INS_LDSMINAB = AARCH64_INS_LDSMINAB, |
| 3314 | ARM64_INS_LDSMINAH = AARCH64_INS_LDSMINAH, |
| 3315 | ARM64_INS_LDSMINALB = AARCH64_INS_LDSMINALB, |
| 3316 | ARM64_INS_LDSMINALH = AARCH64_INS_LDSMINALH, |
| 3317 | ARM64_INS_LDSMINAL = AARCH64_INS_LDSMINAL, |
| 3318 | ARM64_INS_LDSMINA = AARCH64_INS_LDSMINA, |
| 3319 | ARM64_INS_LDSMINB = AARCH64_INS_LDSMINB, |
| 3320 | ARM64_INS_LDSMINH = AARCH64_INS_LDSMINH, |
| 3321 | ARM64_INS_LDSMINLB = AARCH64_INS_LDSMINLB, |
| 3322 | ARM64_INS_LDSMINLH = AARCH64_INS_LDSMINLH, |
| 3323 | ARM64_INS_LDSMINL = AARCH64_INS_LDSMINL, |
| 3324 | ARM64_INS_LDSMIN = AARCH64_INS_LDSMIN, |
| 3325 | ARM64_INS_LDTRB = AARCH64_INS_LDTRB, |
| 3326 | ARM64_INS_LDTRH = AARCH64_INS_LDTRH, |
| 3327 | ARM64_INS_LDTRSB = AARCH64_INS_LDTRSB, |
| 3328 | ARM64_INS_LDTRSH = AARCH64_INS_LDTRSH, |
| 3329 | ARM64_INS_LDTRSW = AARCH64_INS_LDTRSW, |
| 3330 | ARM64_INS_LDTR = AARCH64_INS_LDTR, |
| 3331 | ARM64_INS_LDUMAXAB = AARCH64_INS_LDUMAXAB, |
| 3332 | ARM64_INS_LDUMAXAH = AARCH64_INS_LDUMAXAH, |
| 3333 | ARM64_INS_LDUMAXALB = AARCH64_INS_LDUMAXALB, |
| 3334 | ARM64_INS_LDUMAXALH = AARCH64_INS_LDUMAXALH, |
| 3335 | ARM64_INS_LDUMAXAL = AARCH64_INS_LDUMAXAL, |
| 3336 | ARM64_INS_LDUMAXA = AARCH64_INS_LDUMAXA, |
| 3337 | ARM64_INS_LDUMAXB = AARCH64_INS_LDUMAXB, |
| 3338 | ARM64_INS_LDUMAXH = AARCH64_INS_LDUMAXH, |
| 3339 | ARM64_INS_LDUMAXLB = AARCH64_INS_LDUMAXLB, |
| 3340 | ARM64_INS_LDUMAXLH = AARCH64_INS_LDUMAXLH, |
| 3341 | ARM64_INS_LDUMAXL = AARCH64_INS_LDUMAXL, |
| 3342 | ARM64_INS_LDUMAX = AARCH64_INS_LDUMAX, |
| 3343 | ARM64_INS_LDUMINAB = AARCH64_INS_LDUMINAB, |
| 3344 | ARM64_INS_LDUMINAH = AARCH64_INS_LDUMINAH, |
| 3345 | ARM64_INS_LDUMINALB = AARCH64_INS_LDUMINALB, |
| 3346 | ARM64_INS_LDUMINALH = AARCH64_INS_LDUMINALH, |
| 3347 | ARM64_INS_LDUMINAL = AARCH64_INS_LDUMINAL, |
| 3348 | ARM64_INS_LDUMINA = AARCH64_INS_LDUMINA, |
| 3349 | ARM64_INS_LDUMINB = AARCH64_INS_LDUMINB, |
| 3350 | ARM64_INS_LDUMINH = AARCH64_INS_LDUMINH, |
| 3351 | ARM64_INS_LDUMINLB = AARCH64_INS_LDUMINLB, |
| 3352 | ARM64_INS_LDUMINLH = AARCH64_INS_LDUMINLH, |
| 3353 | ARM64_INS_LDUMINL = AARCH64_INS_LDUMINL, |
| 3354 | ARM64_INS_LDUMIN = AARCH64_INS_LDUMIN, |
| 3355 | ARM64_INS_LDURB = AARCH64_INS_LDURB, |
| 3356 | ARM64_INS_LDUR = AARCH64_INS_LDUR, |
| 3357 | ARM64_INS_LDURH = AARCH64_INS_LDURH, |
| 3358 | ARM64_INS_LDURSB = AARCH64_INS_LDURSB, |
| 3359 | ARM64_INS_LDURSH = AARCH64_INS_LDURSH, |
| 3360 | ARM64_INS_LDURSW = AARCH64_INS_LDURSW, |
| 3361 | ARM64_INS_LDXP = AARCH64_INS_LDXP, |
| 3362 | ARM64_INS_LDXRB = AARCH64_INS_LDXRB, |
| 3363 | ARM64_INS_LDXRH = AARCH64_INS_LDXRH, |
| 3364 | ARM64_INS_LDXR = AARCH64_INS_LDXR, |
| 3365 | ARM64_INS_LSLR = AARCH64_INS_LSLR, |
| 3366 | ARM64_INS_LSL = AARCH64_INS_LSL, |
| 3367 | ARM64_INS_LSRR = AARCH64_INS_LSRR, |
| 3368 | ARM64_INS_LSR = AARCH64_INS_LSR, |
| 3369 | ARM64_INS_LUTI2 = AARCH64_INS_LUTI2, |
| 3370 | ARM64_INS_LUTI4 = AARCH64_INS_LUTI4, |
| 3371 | ARM64_INS_MADDPT = AARCH64_INS_MADDPT, |
| 3372 | ARM64_INS_MADD = AARCH64_INS_MADD, |
| 3373 | ARM64_INS_MADPT = AARCH64_INS_MADPT, |
| 3374 | ARM64_INS_MAD = AARCH64_INS_MAD, |
| 3375 | ARM64_INS_MATCH = AARCH64_INS_MATCH, |
| 3376 | ARM64_INS_MLAPT = AARCH64_INS_MLAPT, |
| 3377 | ARM64_INS_MLA = AARCH64_INS_MLA, |
| 3378 | ARM64_INS_MLS = AARCH64_INS_MLS, |
| 3379 | ARM64_INS_SETGE = AARCH64_INS_SETGE, |
| 3380 | ARM64_INS_SETGEN = AARCH64_INS_SETGEN, |
| 3381 | ARM64_INS_SETGET = AARCH64_INS_SETGET, |
| 3382 | ARM64_INS_SETGETN = AARCH64_INS_SETGETN, |
| 3383 | ARM64_INS_MOVAZ = AARCH64_INS_MOVAZ, |
| 3384 | ARM64_INS_MOVI = AARCH64_INS_MOVI, |
| 3385 | ARM64_INS_MOVK = AARCH64_INS_MOVK, |
| 3386 | ARM64_INS_MOVN = AARCH64_INS_MOVN, |
| 3387 | ARM64_INS_MOVPRFX = AARCH64_INS_MOVPRFX, |
| 3388 | ARM64_INS_MOVT = AARCH64_INS_MOVT, |
| 3389 | ARM64_INS_MOVZ = AARCH64_INS_MOVZ, |
| 3390 | ARM64_INS_MRRS = AARCH64_INS_MRRS, |
| 3391 | ARM64_INS_MRS = AARCH64_INS_MRS, |
| 3392 | ARM64_INS_MSB = AARCH64_INS_MSB, |
| 3393 | ARM64_INS_MSR = AARCH64_INS_MSR, |
| 3394 | ARM64_INS_MSRR = AARCH64_INS_MSRR, |
| 3395 | ARM64_INS_MSUBPT = AARCH64_INS_MSUBPT, |
| 3396 | ARM64_INS_MSUB = AARCH64_INS_MSUB, |
| 3397 | ARM64_INS_MUL = AARCH64_INS_MUL, |
| 3398 | ARM64_INS_MVNI = AARCH64_INS_MVNI, |
| 3399 | ARM64_INS_NANDS = AARCH64_INS_NANDS, |
| 3400 | ARM64_INS_NAND = AARCH64_INS_NAND, |
| 3401 | ARM64_INS_NBSL = AARCH64_INS_NBSL, |
| 3402 | ARM64_INS_NEG = AARCH64_INS_NEG, |
| 3403 | ARM64_INS_NMATCH = AARCH64_INS_NMATCH, |
| 3404 | ARM64_INS_NORS = AARCH64_INS_NORS, |
| 3405 | ARM64_INS_NOR = AARCH64_INS_NOR, |
| 3406 | ARM64_INS_NOT = AARCH64_INS_NOT, |
| 3407 | ARM64_INS_ORNS = AARCH64_INS_ORNS, |
| 3408 | ARM64_INS_ORN = AARCH64_INS_ORN, |
| 3409 | ARM64_INS_ORQV = AARCH64_INS_ORQV, |
| 3410 | ARM64_INS_ORRS = AARCH64_INS_ORRS, |
| 3411 | ARM64_INS_ORR = AARCH64_INS_ORR, |
| 3412 | ARM64_INS_ORV = AARCH64_INS_ORV, |
| 3413 | ARM64_INS_PACDA = AARCH64_INS_PACDA, |
| 3414 | ARM64_INS_PACDB = AARCH64_INS_PACDB, |
| 3415 | ARM64_INS_PACDZA = AARCH64_INS_PACDZA, |
| 3416 | ARM64_INS_PACDZB = AARCH64_INS_PACDZB, |
| 3417 | ARM64_INS_PACGA = AARCH64_INS_PACGA, |
| 3418 | ARM64_INS_PACIA = AARCH64_INS_PACIA, |
| 3419 | ARM64_INS_PACIA171615 = AARCH64_INS_PACIA171615, |
| 3420 | ARM64_INS_PACIASPPC = AARCH64_INS_PACIASPPC, |
| 3421 | ARM64_INS_PACIB = AARCH64_INS_PACIB, |
| 3422 | ARM64_INS_PACIB171615 = AARCH64_INS_PACIB171615, |
| 3423 | ARM64_INS_PACIBSPPC = AARCH64_INS_PACIBSPPC, |
| 3424 | ARM64_INS_PACIZA = AARCH64_INS_PACIZA, |
| 3425 | ARM64_INS_PACIZB = AARCH64_INS_PACIZB, |
| 3426 | ARM64_INS_PACNBIASPPC = AARCH64_INS_PACNBIASPPC, |
| 3427 | ARM64_INS_PACNBIBSPPC = AARCH64_INS_PACNBIBSPPC, |
| 3428 | ARM64_INS_PEXT = AARCH64_INS_PEXT, |
| 3429 | ARM64_INS_PFALSE = AARCH64_INS_PFALSE, |
| 3430 | ARM64_INS_PFIRST = AARCH64_INS_PFIRST, |
| 3431 | ARM64_INS_PMOV = AARCH64_INS_PMOV, |
| 3432 | ARM64_INS_PMULLB = AARCH64_INS_PMULLB, |
| 3433 | ARM64_INS_PMULLT = AARCH64_INS_PMULLT, |
| 3434 | ARM64_INS_PMULL2 = AARCH64_INS_PMULL2, |
| 3435 | ARM64_INS_PMULL = AARCH64_INS_PMULL, |
| 3436 | ARM64_INS_PMUL = AARCH64_INS_PMUL, |
| 3437 | ARM64_INS_PNEXT = AARCH64_INS_PNEXT, |
| 3438 | ARM64_INS_PRFB = AARCH64_INS_PRFB, |
| 3439 | ARM64_INS_PRFD = AARCH64_INS_PRFD, |
| 3440 | ARM64_INS_PRFH = AARCH64_INS_PRFH, |
| 3441 | ARM64_INS_PRFM = AARCH64_INS_PRFM, |
| 3442 | ARM64_INS_PRFUM = AARCH64_INS_PRFUM, |
| 3443 | ARM64_INS_PRFW = AARCH64_INS_PRFW, |
| 3444 | ARM64_INS_PSEL = AARCH64_INS_PSEL, |
| 3445 | ARM64_INS_PTEST = AARCH64_INS_PTEST, |
| 3446 | ARM64_INS_PTRUES = AARCH64_INS_PTRUES, |
| 3447 | ARM64_INS_PTRUE = AARCH64_INS_PTRUE, |
| 3448 | ARM64_INS_PUNPKHI = AARCH64_INS_PUNPKHI, |
| 3449 | ARM64_INS_PUNPKLO = AARCH64_INS_PUNPKLO, |
| 3450 | ARM64_INS_RADDHNB = AARCH64_INS_RADDHNB, |
| 3451 | ARM64_INS_RADDHNT = AARCH64_INS_RADDHNT, |
| 3452 | ARM64_INS_RADDHN = AARCH64_INS_RADDHN, |
| 3453 | ARM64_INS_RADDHN2 = AARCH64_INS_RADDHN2, |
| 3454 | ARM64_INS_RAX1 = AARCH64_INS_RAX1, |
| 3455 | ARM64_INS_RBIT = AARCH64_INS_RBIT, |
| 3456 | ARM64_INS_RCWCAS = AARCH64_INS_RCWCAS, |
| 3457 | ARM64_INS_RCWCASA = AARCH64_INS_RCWCASA, |
| 3458 | ARM64_INS_RCWCASAL = AARCH64_INS_RCWCASAL, |
| 3459 | ARM64_INS_RCWCASL = AARCH64_INS_RCWCASL, |
| 3460 | ARM64_INS_RCWCASP = AARCH64_INS_RCWCASP, |
| 3461 | ARM64_INS_RCWCASPA = AARCH64_INS_RCWCASPA, |
| 3462 | ARM64_INS_RCWCASPAL = AARCH64_INS_RCWCASPAL, |
| 3463 | ARM64_INS_RCWCASPL = AARCH64_INS_RCWCASPL, |
| 3464 | ARM64_INS_RCWCLR = AARCH64_INS_RCWCLR, |
| 3465 | ARM64_INS_RCWCLRA = AARCH64_INS_RCWCLRA, |
| 3466 | ARM64_INS_RCWCLRAL = AARCH64_INS_RCWCLRAL, |
| 3467 | ARM64_INS_RCWCLRL = AARCH64_INS_RCWCLRL, |
| 3468 | ARM64_INS_RCWCLRP = AARCH64_INS_RCWCLRP, |
| 3469 | ARM64_INS_RCWCLRPA = AARCH64_INS_RCWCLRPA, |
| 3470 | ARM64_INS_RCWCLRPAL = AARCH64_INS_RCWCLRPAL, |
| 3471 | ARM64_INS_RCWCLRPL = AARCH64_INS_RCWCLRPL, |
| 3472 | ARM64_INS_RCWSCLR = AARCH64_INS_RCWSCLR, |
| 3473 | ARM64_INS_RCWSCLRA = AARCH64_INS_RCWSCLRA, |
| 3474 | ARM64_INS_RCWSCLRAL = AARCH64_INS_RCWSCLRAL, |
| 3475 | ARM64_INS_RCWSCLRL = AARCH64_INS_RCWSCLRL, |
| 3476 | ARM64_INS_RCWSCLRP = AARCH64_INS_RCWSCLRP, |
| 3477 | ARM64_INS_RCWSCLRPA = AARCH64_INS_RCWSCLRPA, |
| 3478 | ARM64_INS_RCWSCLRPAL = AARCH64_INS_RCWSCLRPAL, |
| 3479 | ARM64_INS_RCWSCLRPL = AARCH64_INS_RCWSCLRPL, |
| 3480 | ARM64_INS_RCWSCAS = AARCH64_INS_RCWSCAS, |
| 3481 | ARM64_INS_RCWSCASA = AARCH64_INS_RCWSCASA, |
| 3482 | ARM64_INS_RCWSCASAL = AARCH64_INS_RCWSCASAL, |
| 3483 | ARM64_INS_RCWSCASL = AARCH64_INS_RCWSCASL, |
| 3484 | ARM64_INS_RCWSCASP = AARCH64_INS_RCWSCASP, |
| 3485 | ARM64_INS_RCWSCASPA = AARCH64_INS_RCWSCASPA, |
| 3486 | ARM64_INS_RCWSCASPAL = AARCH64_INS_RCWSCASPAL, |
| 3487 | ARM64_INS_RCWSCASPL = AARCH64_INS_RCWSCASPL, |
| 3488 | ARM64_INS_RCWSET = AARCH64_INS_RCWSET, |
| 3489 | ARM64_INS_RCWSETA = AARCH64_INS_RCWSETA, |
| 3490 | ARM64_INS_RCWSETAL = AARCH64_INS_RCWSETAL, |
| 3491 | ARM64_INS_RCWSETL = AARCH64_INS_RCWSETL, |
| 3492 | ARM64_INS_RCWSETP = AARCH64_INS_RCWSETP, |
| 3493 | ARM64_INS_RCWSETPA = AARCH64_INS_RCWSETPA, |
| 3494 | ARM64_INS_RCWSETPAL = AARCH64_INS_RCWSETPAL, |
| 3495 | ARM64_INS_RCWSETPL = AARCH64_INS_RCWSETPL, |
| 3496 | ARM64_INS_RCWSSET = AARCH64_INS_RCWSSET, |
| 3497 | ARM64_INS_RCWSSETA = AARCH64_INS_RCWSSETA, |
| 3498 | ARM64_INS_RCWSSETAL = AARCH64_INS_RCWSSETAL, |
| 3499 | ARM64_INS_RCWSSETL = AARCH64_INS_RCWSSETL, |
| 3500 | ARM64_INS_RCWSSETP = AARCH64_INS_RCWSSETP, |
| 3501 | ARM64_INS_RCWSSETPA = AARCH64_INS_RCWSSETPA, |
| 3502 | ARM64_INS_RCWSSETPAL = AARCH64_INS_RCWSSETPAL, |
| 3503 | ARM64_INS_RCWSSETPL = AARCH64_INS_RCWSSETPL, |
| 3504 | ARM64_INS_RCWSWP = AARCH64_INS_RCWSWP, |
| 3505 | ARM64_INS_RCWSWPA = AARCH64_INS_RCWSWPA, |
| 3506 | ARM64_INS_RCWSWPAL = AARCH64_INS_RCWSWPAL, |
| 3507 | ARM64_INS_RCWSWPL = AARCH64_INS_RCWSWPL, |
| 3508 | ARM64_INS_RCWSWPP = AARCH64_INS_RCWSWPP, |
| 3509 | ARM64_INS_RCWSWPPA = AARCH64_INS_RCWSWPPA, |
| 3510 | ARM64_INS_RCWSWPPAL = AARCH64_INS_RCWSWPPAL, |
| 3511 | ARM64_INS_RCWSWPPL = AARCH64_INS_RCWSWPPL, |
| 3512 | ARM64_INS_RCWSSWP = AARCH64_INS_RCWSSWP, |
| 3513 | ARM64_INS_RCWSSWPA = AARCH64_INS_RCWSSWPA, |
| 3514 | ARM64_INS_RCWSSWPAL = AARCH64_INS_RCWSSWPAL, |
| 3515 | ARM64_INS_RCWSSWPL = AARCH64_INS_RCWSSWPL, |
| 3516 | ARM64_INS_RCWSSWPP = AARCH64_INS_RCWSSWPP, |
| 3517 | ARM64_INS_RCWSSWPPA = AARCH64_INS_RCWSSWPPA, |
| 3518 | ARM64_INS_RCWSSWPPAL = AARCH64_INS_RCWSSWPPAL, |
| 3519 | ARM64_INS_RCWSSWPPL = AARCH64_INS_RCWSSWPPL, |
| 3520 | ARM64_INS_RDFFRS = AARCH64_INS_RDFFRS, |
| 3521 | ARM64_INS_RDFFR = AARCH64_INS_RDFFR, |
| 3522 | ARM64_INS_RDSVL = AARCH64_INS_RDSVL, |
| 3523 | ARM64_INS_RDVL = AARCH64_INS_RDVL, |
| 3524 | ARM64_INS_RET = AARCH64_INS_RET, |
| 3525 | ARM64_INS_RETAA = AARCH64_INS_RETAA, |
| 3526 | ARM64_INS_RETAASPPC = AARCH64_INS_RETAASPPC, |
| 3527 | ARM64_INS_RETAB = AARCH64_INS_RETAB, |
| 3528 | ARM64_INS_RETABSPPC = AARCH64_INS_RETABSPPC, |
| 3529 | ARM64_INS_REV16 = AARCH64_INS_REV16, |
| 3530 | ARM64_INS_REV32 = AARCH64_INS_REV32, |
| 3531 | ARM64_INS_REV64 = AARCH64_INS_REV64, |
| 3532 | ARM64_INS_REVB = AARCH64_INS_REVB, |
| 3533 | ARM64_INS_REVD = AARCH64_INS_REVD, |
| 3534 | ARM64_INS_REVH = AARCH64_INS_REVH, |
| 3535 | ARM64_INS_REVW = AARCH64_INS_REVW, |
| 3536 | ARM64_INS_REV = AARCH64_INS_REV, |
| 3537 | ARM64_INS_RMIF = AARCH64_INS_RMIF, |
| 3538 | ARM64_INS_ROR = AARCH64_INS_ROR, |
| 3539 | ARM64_INS_RPRFM = AARCH64_INS_RPRFM, |
| 3540 | ARM64_INS_RSHRNB = AARCH64_INS_RSHRNB, |
| 3541 | ARM64_INS_RSHRNT = AARCH64_INS_RSHRNT, |
| 3542 | ARM64_INS_RSHRN2 = AARCH64_INS_RSHRN2, |
| 3543 | ARM64_INS_RSHRN = AARCH64_INS_RSHRN, |
| 3544 | ARM64_INS_RSUBHNB = AARCH64_INS_RSUBHNB, |
| 3545 | ARM64_INS_RSUBHNT = AARCH64_INS_RSUBHNT, |
| 3546 | ARM64_INS_RSUBHN = AARCH64_INS_RSUBHN, |
| 3547 | ARM64_INS_RSUBHN2 = AARCH64_INS_RSUBHN2, |
| 3548 | ARM64_INS_SABALB = AARCH64_INS_SABALB, |
| 3549 | ARM64_INS_SABALT = AARCH64_INS_SABALT, |
| 3550 | ARM64_INS_SABAL2 = AARCH64_INS_SABAL2, |
| 3551 | ARM64_INS_SABAL = AARCH64_INS_SABAL, |
| 3552 | ARM64_INS_SABA = AARCH64_INS_SABA, |
| 3553 | ARM64_INS_SABDLB = AARCH64_INS_SABDLB, |
| 3554 | ARM64_INS_SABDLT = AARCH64_INS_SABDLT, |
| 3555 | ARM64_INS_SABDL2 = AARCH64_INS_SABDL2, |
| 3556 | ARM64_INS_SABDL = AARCH64_INS_SABDL, |
| 3557 | ARM64_INS_SABD = AARCH64_INS_SABD, |
| 3558 | ARM64_INS_SADALP = AARCH64_INS_SADALP, |
| 3559 | ARM64_INS_SADDLBT = AARCH64_INS_SADDLBT, |
| 3560 | ARM64_INS_SADDLB = AARCH64_INS_SADDLB, |
| 3561 | ARM64_INS_SADDLP = AARCH64_INS_SADDLP, |
| 3562 | ARM64_INS_SADDLT = AARCH64_INS_SADDLT, |
| 3563 | ARM64_INS_SADDLV = AARCH64_INS_SADDLV, |
| 3564 | ARM64_INS_SADDL2 = AARCH64_INS_SADDL2, |
| 3565 | ARM64_INS_SADDL = AARCH64_INS_SADDL, |
| 3566 | ARM64_INS_SADDV = AARCH64_INS_SADDV, |
| 3567 | ARM64_INS_SADDWB = AARCH64_INS_SADDWB, |
| 3568 | ARM64_INS_SADDWT = AARCH64_INS_SADDWT, |
| 3569 | ARM64_INS_SADDW2 = AARCH64_INS_SADDW2, |
| 3570 | ARM64_INS_SADDW = AARCH64_INS_SADDW, |
| 3571 | ARM64_INS_SB = AARCH64_INS_SB, |
| 3572 | ARM64_INS_SBCLB = AARCH64_INS_SBCLB, |
| 3573 | ARM64_INS_SBCLT = AARCH64_INS_SBCLT, |
| 3574 | ARM64_INS_SBCS = AARCH64_INS_SBCS, |
| 3575 | ARM64_INS_SBC = AARCH64_INS_SBC, |
| 3576 | ARM64_INS_SBFM = AARCH64_INS_SBFM, |
| 3577 | ARM64_INS_SCLAMP = AARCH64_INS_SCLAMP, |
| 3578 | ARM64_INS_SCVTF = AARCH64_INS_SCVTF, |
| 3579 | ARM64_INS_SDIVR = AARCH64_INS_SDIVR, |
| 3580 | ARM64_INS_SDIV = AARCH64_INS_SDIV, |
| 3581 | ARM64_INS_SDOT = AARCH64_INS_SDOT, |
| 3582 | ARM64_INS_SEL = AARCH64_INS_SEL, |
| 3583 | ARM64_INS_SETE = AARCH64_INS_SETE, |
| 3584 | ARM64_INS_SETEN = AARCH64_INS_SETEN, |
| 3585 | ARM64_INS_SETET = AARCH64_INS_SETET, |
| 3586 | ARM64_INS_SETETN = AARCH64_INS_SETETN, |
| 3587 | ARM64_INS_SETF16 = AARCH64_INS_SETF16, |
| 3588 | ARM64_INS_SETF8 = AARCH64_INS_SETF8, |
| 3589 | ARM64_INS_SETFFR = AARCH64_INS_SETFFR, |
| 3590 | ARM64_INS_SETGM = AARCH64_INS_SETGM, |
| 3591 | ARM64_INS_SETGMN = AARCH64_INS_SETGMN, |
| 3592 | ARM64_INS_SETGMT = AARCH64_INS_SETGMT, |
| 3593 | ARM64_INS_SETGMTN = AARCH64_INS_SETGMTN, |
| 3594 | ARM64_INS_SETGP = AARCH64_INS_SETGP, |
| 3595 | ARM64_INS_SETGPN = AARCH64_INS_SETGPN, |
| 3596 | ARM64_INS_SETGPT = AARCH64_INS_SETGPT, |
| 3597 | ARM64_INS_SETGPTN = AARCH64_INS_SETGPTN, |
| 3598 | ARM64_INS_SETM = AARCH64_INS_SETM, |
| 3599 | ARM64_INS_SETMN = AARCH64_INS_SETMN, |
| 3600 | ARM64_INS_SETMT = AARCH64_INS_SETMT, |
| 3601 | ARM64_INS_SETMTN = AARCH64_INS_SETMTN, |
| 3602 | ARM64_INS_SETP = AARCH64_INS_SETP, |
| 3603 | ARM64_INS_SETPN = AARCH64_INS_SETPN, |
| 3604 | ARM64_INS_SETPT = AARCH64_INS_SETPT, |
| 3605 | ARM64_INS_SETPTN = AARCH64_INS_SETPTN, |
| 3606 | ARM64_INS_SHA1C = AARCH64_INS_SHA1C, |
| 3607 | ARM64_INS_SHA1H = AARCH64_INS_SHA1H, |
| 3608 | ARM64_INS_SHA1M = AARCH64_INS_SHA1M, |
| 3609 | ARM64_INS_SHA1P = AARCH64_INS_SHA1P, |
| 3610 | ARM64_INS_SHA1SU0 = AARCH64_INS_SHA1SU0, |
| 3611 | ARM64_INS_SHA1SU1 = AARCH64_INS_SHA1SU1, |
| 3612 | ARM64_INS_SHA256H2 = AARCH64_INS_SHA256H2, |
| 3613 | ARM64_INS_SHA256H = AARCH64_INS_SHA256H, |
| 3614 | ARM64_INS_SHA256SU0 = AARCH64_INS_SHA256SU0, |
| 3615 | ARM64_INS_SHA256SU1 = AARCH64_INS_SHA256SU1, |
| 3616 | ARM64_INS_SHA512H = AARCH64_INS_SHA512H, |
| 3617 | ARM64_INS_SHA512H2 = AARCH64_INS_SHA512H2, |
| 3618 | ARM64_INS_SHA512SU0 = AARCH64_INS_SHA512SU0, |
| 3619 | ARM64_INS_SHA512SU1 = AARCH64_INS_SHA512SU1, |
| 3620 | ARM64_INS_SHADD = AARCH64_INS_SHADD, |
| 3621 | ARM64_INS_SHLL2 = AARCH64_INS_SHLL2, |
| 3622 | ARM64_INS_SHLL = AARCH64_INS_SHLL, |
| 3623 | ARM64_INS_SHL = AARCH64_INS_SHL, |
| 3624 | ARM64_INS_SHRNB = AARCH64_INS_SHRNB, |
| 3625 | ARM64_INS_SHRNT = AARCH64_INS_SHRNT, |
| 3626 | ARM64_INS_SHRN2 = AARCH64_INS_SHRN2, |
| 3627 | ARM64_INS_SHRN = AARCH64_INS_SHRN, |
| 3628 | ARM64_INS_SHSUBR = AARCH64_INS_SHSUBR, |
| 3629 | ARM64_INS_SHSUB = AARCH64_INS_SHSUB, |
| 3630 | ARM64_INS_SLI = AARCH64_INS_SLI, |
| 3631 | ARM64_INS_SM3PARTW1 = AARCH64_INS_SM3PARTW1, |
| 3632 | ARM64_INS_SM3PARTW2 = AARCH64_INS_SM3PARTW2, |
| 3633 | ARM64_INS_SM3SS1 = AARCH64_INS_SM3SS1, |
| 3634 | ARM64_INS_SM3TT1A = AARCH64_INS_SM3TT1A, |
| 3635 | ARM64_INS_SM3TT1B = AARCH64_INS_SM3TT1B, |
| 3636 | ARM64_INS_SM3TT2A = AARCH64_INS_SM3TT2A, |
| 3637 | ARM64_INS_SM3TT2B = AARCH64_INS_SM3TT2B, |
| 3638 | ARM64_INS_SM4E = AARCH64_INS_SM4E, |
| 3639 | ARM64_INS_SM4EKEY = AARCH64_INS_SM4EKEY, |
| 3640 | ARM64_INS_SMADDL = AARCH64_INS_SMADDL, |
| 3641 | ARM64_INS_SMAXP = AARCH64_INS_SMAXP, |
| 3642 | ARM64_INS_SMAXQV = AARCH64_INS_SMAXQV, |
| 3643 | ARM64_INS_SMAXV = AARCH64_INS_SMAXV, |
| 3644 | ARM64_INS_SMAX = AARCH64_INS_SMAX, |
| 3645 | ARM64_INS_SMC = AARCH64_INS_SMC, |
| 3646 | ARM64_INS_SMINP = AARCH64_INS_SMINP, |
| 3647 | ARM64_INS_SMINQV = AARCH64_INS_SMINQV, |
| 3648 | ARM64_INS_SMINV = AARCH64_INS_SMINV, |
| 3649 | ARM64_INS_SMIN = AARCH64_INS_SMIN, |
| 3650 | ARM64_INS_SMLALB = AARCH64_INS_SMLALB, |
| 3651 | ARM64_INS_SMLALL = AARCH64_INS_SMLALL, |
| 3652 | ARM64_INS_SMLALT = AARCH64_INS_SMLALT, |
| 3653 | ARM64_INS_SMLAL = AARCH64_INS_SMLAL, |
| 3654 | ARM64_INS_SMLAL2 = AARCH64_INS_SMLAL2, |
| 3655 | ARM64_INS_SMLSLB = AARCH64_INS_SMLSLB, |
| 3656 | ARM64_INS_SMLSLL = AARCH64_INS_SMLSLL, |
| 3657 | ARM64_INS_SMLSLT = AARCH64_INS_SMLSLT, |
| 3658 | ARM64_INS_SMLSL = AARCH64_INS_SMLSL, |
| 3659 | ARM64_INS_SMLSL2 = AARCH64_INS_SMLSL2, |
| 3660 | ARM64_INS_SMMLA = AARCH64_INS_SMMLA, |
| 3661 | ARM64_INS_SMOPA = AARCH64_INS_SMOPA, |
| 3662 | ARM64_INS_SMOPS = AARCH64_INS_SMOPS, |
| 3663 | ARM64_INS_SMOV = AARCH64_INS_SMOV, |
| 3664 | ARM64_INS_SMSUBL = AARCH64_INS_SMSUBL, |
| 3665 | ARM64_INS_SMULH = AARCH64_INS_SMULH, |
| 3666 | ARM64_INS_SMULLB = AARCH64_INS_SMULLB, |
| 3667 | ARM64_INS_SMULLT = AARCH64_INS_SMULLT, |
| 3668 | ARM64_INS_SMULL2 = AARCH64_INS_SMULL2, |
| 3669 | ARM64_INS_SMULL = AARCH64_INS_SMULL, |
| 3670 | ARM64_INS_SPLICE = AARCH64_INS_SPLICE, |
| 3671 | ARM64_INS_SQABS = AARCH64_INS_SQABS, |
| 3672 | ARM64_INS_SQADD = AARCH64_INS_SQADD, |
| 3673 | ARM64_INS_SQCADD = AARCH64_INS_SQCADD, |
| 3674 | ARM64_INS_SQCVTN = AARCH64_INS_SQCVTN, |
| 3675 | ARM64_INS_SQCVTUN = AARCH64_INS_SQCVTUN, |
| 3676 | ARM64_INS_SQCVTU = AARCH64_INS_SQCVTU, |
| 3677 | ARM64_INS_SQCVT = AARCH64_INS_SQCVT, |
| 3678 | ARM64_INS_SQDECB = AARCH64_INS_SQDECB, |
| 3679 | ARM64_INS_SQDECD = AARCH64_INS_SQDECD, |
| 3680 | ARM64_INS_SQDECH = AARCH64_INS_SQDECH, |
| 3681 | ARM64_INS_SQDECP = AARCH64_INS_SQDECP, |
| 3682 | ARM64_INS_SQDECW = AARCH64_INS_SQDECW, |
| 3683 | ARM64_INS_SQDMLALBT = AARCH64_INS_SQDMLALBT, |
| 3684 | ARM64_INS_SQDMLALB = AARCH64_INS_SQDMLALB, |
| 3685 | ARM64_INS_SQDMLALT = AARCH64_INS_SQDMLALT, |
| 3686 | ARM64_INS_SQDMLAL = AARCH64_INS_SQDMLAL, |
| 3687 | ARM64_INS_SQDMLAL2 = AARCH64_INS_SQDMLAL2, |
| 3688 | ARM64_INS_SQDMLSLBT = AARCH64_INS_SQDMLSLBT, |
| 3689 | ARM64_INS_SQDMLSLB = AARCH64_INS_SQDMLSLB, |
| 3690 | ARM64_INS_SQDMLSLT = AARCH64_INS_SQDMLSLT, |
| 3691 | ARM64_INS_SQDMLSL = AARCH64_INS_SQDMLSL, |
| 3692 | ARM64_INS_SQDMLSL2 = AARCH64_INS_SQDMLSL2, |
| 3693 | ARM64_INS_SQDMULH = AARCH64_INS_SQDMULH, |
| 3694 | ARM64_INS_SQDMULLB = AARCH64_INS_SQDMULLB, |
| 3695 | ARM64_INS_SQDMULLT = AARCH64_INS_SQDMULLT, |
| 3696 | ARM64_INS_SQDMULL = AARCH64_INS_SQDMULL, |
| 3697 | ARM64_INS_SQDMULL2 = AARCH64_INS_SQDMULL2, |
| 3698 | ARM64_INS_SQINCB = AARCH64_INS_SQINCB, |
| 3699 | ARM64_INS_SQINCD = AARCH64_INS_SQINCD, |
| 3700 | ARM64_INS_SQINCH = AARCH64_INS_SQINCH, |
| 3701 | ARM64_INS_SQINCP = AARCH64_INS_SQINCP, |
| 3702 | ARM64_INS_SQINCW = AARCH64_INS_SQINCW, |
| 3703 | ARM64_INS_SQNEG = AARCH64_INS_SQNEG, |
| 3704 | ARM64_INS_SQRDCMLAH = AARCH64_INS_SQRDCMLAH, |
| 3705 | ARM64_INS_SQRDMLAH = AARCH64_INS_SQRDMLAH, |
| 3706 | ARM64_INS_SQRDMLSH = AARCH64_INS_SQRDMLSH, |
| 3707 | ARM64_INS_SQRDMULH = AARCH64_INS_SQRDMULH, |
| 3708 | ARM64_INS_SQRSHLR = AARCH64_INS_SQRSHLR, |
| 3709 | ARM64_INS_SQRSHL = AARCH64_INS_SQRSHL, |
| 3710 | ARM64_INS_SQRSHRNB = AARCH64_INS_SQRSHRNB, |
| 3711 | ARM64_INS_SQRSHRNT = AARCH64_INS_SQRSHRNT, |
| 3712 | ARM64_INS_SQRSHRN = AARCH64_INS_SQRSHRN, |
| 3713 | ARM64_INS_SQRSHRN2 = AARCH64_INS_SQRSHRN2, |
| 3714 | ARM64_INS_SQRSHRUNB = AARCH64_INS_SQRSHRUNB, |
| 3715 | ARM64_INS_SQRSHRUNT = AARCH64_INS_SQRSHRUNT, |
| 3716 | ARM64_INS_SQRSHRUN = AARCH64_INS_SQRSHRUN, |
| 3717 | ARM64_INS_SQRSHRUN2 = AARCH64_INS_SQRSHRUN2, |
| 3718 | ARM64_INS_SQRSHRU = AARCH64_INS_SQRSHRU, |
| 3719 | ARM64_INS_SQRSHR = AARCH64_INS_SQRSHR, |
| 3720 | ARM64_INS_SQSHLR = AARCH64_INS_SQSHLR, |
| 3721 | ARM64_INS_SQSHLU = AARCH64_INS_SQSHLU, |
| 3722 | ARM64_INS_SQSHL = AARCH64_INS_SQSHL, |
| 3723 | ARM64_INS_SQSHRNB = AARCH64_INS_SQSHRNB, |
| 3724 | ARM64_INS_SQSHRNT = AARCH64_INS_SQSHRNT, |
| 3725 | ARM64_INS_SQSHRN = AARCH64_INS_SQSHRN, |
| 3726 | ARM64_INS_SQSHRN2 = AARCH64_INS_SQSHRN2, |
| 3727 | ARM64_INS_SQSHRUNB = AARCH64_INS_SQSHRUNB, |
| 3728 | ARM64_INS_SQSHRUNT = AARCH64_INS_SQSHRUNT, |
| 3729 | ARM64_INS_SQSHRUN = AARCH64_INS_SQSHRUN, |
| 3730 | ARM64_INS_SQSHRUN2 = AARCH64_INS_SQSHRUN2, |
| 3731 | ARM64_INS_SQSUBR = AARCH64_INS_SQSUBR, |
| 3732 | ARM64_INS_SQSUB = AARCH64_INS_SQSUB, |
| 3733 | ARM64_INS_SQXTNB = AARCH64_INS_SQXTNB, |
| 3734 | ARM64_INS_SQXTNT = AARCH64_INS_SQXTNT, |
| 3735 | ARM64_INS_SQXTN2 = AARCH64_INS_SQXTN2, |
| 3736 | ARM64_INS_SQXTN = AARCH64_INS_SQXTN, |
| 3737 | ARM64_INS_SQXTUNB = AARCH64_INS_SQXTUNB, |
| 3738 | ARM64_INS_SQXTUNT = AARCH64_INS_SQXTUNT, |
| 3739 | ARM64_INS_SQXTUN2 = AARCH64_INS_SQXTUN2, |
| 3740 | ARM64_INS_SQXTUN = AARCH64_INS_SQXTUN, |
| 3741 | ARM64_INS_SRHADD = AARCH64_INS_SRHADD, |
| 3742 | ARM64_INS_SRI = AARCH64_INS_SRI, |
| 3743 | ARM64_INS_SRSHLR = AARCH64_INS_SRSHLR, |
| 3744 | ARM64_INS_SRSHL = AARCH64_INS_SRSHL, |
| 3745 | ARM64_INS_SRSHR = AARCH64_INS_SRSHR, |
| 3746 | ARM64_INS_SRSRA = AARCH64_INS_SRSRA, |
| 3747 | ARM64_INS_SSHLLB = AARCH64_INS_SSHLLB, |
| 3748 | ARM64_INS_SSHLLT = AARCH64_INS_SSHLLT, |
| 3749 | ARM64_INS_SSHLL2 = AARCH64_INS_SSHLL2, |
| 3750 | ARM64_INS_SSHLL = AARCH64_INS_SSHLL, |
| 3751 | ARM64_INS_SSHL = AARCH64_INS_SSHL, |
| 3752 | ARM64_INS_SSHR = AARCH64_INS_SSHR, |
| 3753 | ARM64_INS_SSRA = AARCH64_INS_SSRA, |
| 3754 | ARM64_INS_ST1B = AARCH64_INS_ST1B, |
| 3755 | ARM64_INS_ST1D = AARCH64_INS_ST1D, |
| 3756 | ARM64_INS_ST1H = AARCH64_INS_ST1H, |
| 3757 | ARM64_INS_ST1Q = AARCH64_INS_ST1Q, |
| 3758 | ARM64_INS_ST1W = AARCH64_INS_ST1W, |
| 3759 | ARM64_INS_SSUBLBT = AARCH64_INS_SSUBLBT, |
| 3760 | ARM64_INS_SSUBLB = AARCH64_INS_SSUBLB, |
| 3761 | ARM64_INS_SSUBLTB = AARCH64_INS_SSUBLTB, |
| 3762 | ARM64_INS_SSUBLT = AARCH64_INS_SSUBLT, |
| 3763 | ARM64_INS_SSUBL2 = AARCH64_INS_SSUBL2, |
| 3764 | ARM64_INS_SSUBL = AARCH64_INS_SSUBL, |
| 3765 | ARM64_INS_SSUBWB = AARCH64_INS_SSUBWB, |
| 3766 | ARM64_INS_SSUBWT = AARCH64_INS_SSUBWT, |
| 3767 | ARM64_INS_SSUBW2 = AARCH64_INS_SSUBW2, |
| 3768 | ARM64_INS_SSUBW = AARCH64_INS_SSUBW, |
| 3769 | ARM64_INS_ST1 = AARCH64_INS_ST1, |
| 3770 | ARM64_INS_ST2B = AARCH64_INS_ST2B, |
| 3771 | ARM64_INS_ST2D = AARCH64_INS_ST2D, |
| 3772 | ARM64_INS_ST2G = AARCH64_INS_ST2G, |
| 3773 | ARM64_INS_ST2H = AARCH64_INS_ST2H, |
| 3774 | ARM64_INS_ST2Q = AARCH64_INS_ST2Q, |
| 3775 | ARM64_INS_ST2 = AARCH64_INS_ST2, |
| 3776 | ARM64_INS_ST2W = AARCH64_INS_ST2W, |
| 3777 | ARM64_INS_ST3B = AARCH64_INS_ST3B, |
| 3778 | ARM64_INS_ST3D = AARCH64_INS_ST3D, |
| 3779 | ARM64_INS_ST3H = AARCH64_INS_ST3H, |
| 3780 | ARM64_INS_ST3Q = AARCH64_INS_ST3Q, |
| 3781 | ARM64_INS_ST3 = AARCH64_INS_ST3, |
| 3782 | ARM64_INS_ST3W = AARCH64_INS_ST3W, |
| 3783 | ARM64_INS_ST4B = AARCH64_INS_ST4B, |
| 3784 | ARM64_INS_ST4D = AARCH64_INS_ST4D, |
| 3785 | ARM64_INS_ST4 = AARCH64_INS_ST4, |
| 3786 | ARM64_INS_ST4H = AARCH64_INS_ST4H, |
| 3787 | ARM64_INS_ST4Q = AARCH64_INS_ST4Q, |
| 3788 | ARM64_INS_ST4W = AARCH64_INS_ST4W, |
| 3789 | ARM64_INS_ST64B = AARCH64_INS_ST64B, |
| 3790 | ARM64_INS_ST64BV = AARCH64_INS_ST64BV, |
| 3791 | ARM64_INS_ST64BV0 = AARCH64_INS_ST64BV0, |
| 3792 | ARM64_INS_STGM = AARCH64_INS_STGM, |
| 3793 | ARM64_INS_STGP = AARCH64_INS_STGP, |
| 3794 | ARM64_INS_STG = AARCH64_INS_STG, |
| 3795 | ARM64_INS_STILP = AARCH64_INS_STILP, |
| 3796 | ARM64_INS_STL1 = AARCH64_INS_STL1, |
| 3797 | ARM64_INS_STLLRB = AARCH64_INS_STLLRB, |
| 3798 | ARM64_INS_STLLRH = AARCH64_INS_STLLRH, |
| 3799 | ARM64_INS_STLLR = AARCH64_INS_STLLR, |
| 3800 | ARM64_INS_STLRB = AARCH64_INS_STLRB, |
| 3801 | ARM64_INS_STLRH = AARCH64_INS_STLRH, |
| 3802 | ARM64_INS_STLR = AARCH64_INS_STLR, |
| 3803 | ARM64_INS_STLURB = AARCH64_INS_STLURB, |
| 3804 | ARM64_INS_STLURH = AARCH64_INS_STLURH, |
| 3805 | ARM64_INS_STLUR = AARCH64_INS_STLUR, |
| 3806 | ARM64_INS_STLXP = AARCH64_INS_STLXP, |
| 3807 | ARM64_INS_STLXRB = AARCH64_INS_STLXRB, |
| 3808 | ARM64_INS_STLXRH = AARCH64_INS_STLXRH, |
| 3809 | ARM64_INS_STLXR = AARCH64_INS_STLXR, |
| 3810 | ARM64_INS_STNP = AARCH64_INS_STNP, |
| 3811 | ARM64_INS_STNT1B = AARCH64_INS_STNT1B, |
| 3812 | ARM64_INS_STNT1D = AARCH64_INS_STNT1D, |
| 3813 | ARM64_INS_STNT1H = AARCH64_INS_STNT1H, |
| 3814 | ARM64_INS_STNT1W = AARCH64_INS_STNT1W, |
| 3815 | ARM64_INS_STP = AARCH64_INS_STP, |
| 3816 | ARM64_INS_STRB = AARCH64_INS_STRB, |
| 3817 | ARM64_INS_STR = AARCH64_INS_STR, |
| 3818 | ARM64_INS_STRH = AARCH64_INS_STRH, |
| 3819 | ARM64_INS_STTRB = AARCH64_INS_STTRB, |
| 3820 | ARM64_INS_STTRH = AARCH64_INS_STTRH, |
| 3821 | ARM64_INS_STTR = AARCH64_INS_STTR, |
| 3822 | ARM64_INS_STURB = AARCH64_INS_STURB, |
| 3823 | ARM64_INS_STUR = AARCH64_INS_STUR, |
| 3824 | ARM64_INS_STURH = AARCH64_INS_STURH, |
| 3825 | ARM64_INS_STXP = AARCH64_INS_STXP, |
| 3826 | ARM64_INS_STXRB = AARCH64_INS_STXRB, |
| 3827 | ARM64_INS_STXRH = AARCH64_INS_STXRH, |
| 3828 | ARM64_INS_STXR = AARCH64_INS_STXR, |
| 3829 | ARM64_INS_STZ2G = AARCH64_INS_STZ2G, |
| 3830 | ARM64_INS_STZGM = AARCH64_INS_STZGM, |
| 3831 | ARM64_INS_STZG = AARCH64_INS_STZG, |
| 3832 | ARM64_INS_SUBG = AARCH64_INS_SUBG, |
| 3833 | ARM64_INS_SUBHNB = AARCH64_INS_SUBHNB, |
| 3834 | ARM64_INS_SUBHNT = AARCH64_INS_SUBHNT, |
| 3835 | ARM64_INS_SUBHN = AARCH64_INS_SUBHN, |
| 3836 | ARM64_INS_SUBHN2 = AARCH64_INS_SUBHN2, |
| 3837 | ARM64_INS_SUBP = AARCH64_INS_SUBP, |
| 3838 | ARM64_INS_SUBPS = AARCH64_INS_SUBPS, |
| 3839 | ARM64_INS_SUBPT = AARCH64_INS_SUBPT, |
| 3840 | ARM64_INS_SUBR = AARCH64_INS_SUBR, |
| 3841 | ARM64_INS_SUBS = AARCH64_INS_SUBS, |
| 3842 | ARM64_INS_SUB = AARCH64_INS_SUB, |
| 3843 | ARM64_INS_SUDOT = AARCH64_INS_SUDOT, |
| 3844 | ARM64_INS_SUMLALL = AARCH64_INS_SUMLALL, |
| 3845 | ARM64_INS_SUMOPA = AARCH64_INS_SUMOPA, |
| 3846 | ARM64_INS_SUMOPS = AARCH64_INS_SUMOPS, |
| 3847 | ARM64_INS_SUNPKHI = AARCH64_INS_SUNPKHI, |
| 3848 | ARM64_INS_SUNPKLO = AARCH64_INS_SUNPKLO, |
| 3849 | ARM64_INS_SUNPK = AARCH64_INS_SUNPK, |
| 3850 | ARM64_INS_SUQADD = AARCH64_INS_SUQADD, |
| 3851 | ARM64_INS_SUVDOT = AARCH64_INS_SUVDOT, |
| 3852 | ARM64_INS_SVC = AARCH64_INS_SVC, |
| 3853 | ARM64_INS_SVDOT = AARCH64_INS_SVDOT, |
| 3854 | ARM64_INS_SWPAB = AARCH64_INS_SWPAB, |
| 3855 | ARM64_INS_SWPAH = AARCH64_INS_SWPAH, |
| 3856 | ARM64_INS_SWPALB = AARCH64_INS_SWPALB, |
| 3857 | ARM64_INS_SWPALH = AARCH64_INS_SWPALH, |
| 3858 | ARM64_INS_SWPAL = AARCH64_INS_SWPAL, |
| 3859 | ARM64_INS_SWPA = AARCH64_INS_SWPA, |
| 3860 | ARM64_INS_SWPB = AARCH64_INS_SWPB, |
| 3861 | ARM64_INS_SWPH = AARCH64_INS_SWPH, |
| 3862 | ARM64_INS_SWPLB = AARCH64_INS_SWPLB, |
| 3863 | ARM64_INS_SWPLH = AARCH64_INS_SWPLH, |
| 3864 | ARM64_INS_SWPL = AARCH64_INS_SWPL, |
| 3865 | ARM64_INS_SWPP = AARCH64_INS_SWPP, |
| 3866 | ARM64_INS_SWPPA = AARCH64_INS_SWPPA, |
| 3867 | ARM64_INS_SWPPAL = AARCH64_INS_SWPPAL, |
| 3868 | ARM64_INS_SWPPL = AARCH64_INS_SWPPL, |
| 3869 | ARM64_INS_SWP = AARCH64_INS_SWP, |
| 3870 | ARM64_INS_SXTB = AARCH64_INS_SXTB, |
| 3871 | ARM64_INS_SXTH = AARCH64_INS_SXTH, |
| 3872 | ARM64_INS_SXTW = AARCH64_INS_SXTW, |
| 3873 | ARM64_INS_SYSL = AARCH64_INS_SYSL, |
| 3874 | ARM64_INS_SYSP = AARCH64_INS_SYSP, |
| 3875 | ARM64_INS_SYS = AARCH64_INS_SYS, |
| 3876 | ARM64_INS_TBLQ = AARCH64_INS_TBLQ, |
| 3877 | ARM64_INS_TBL = AARCH64_INS_TBL, |
| 3878 | ARM64_INS_TBNZ = AARCH64_INS_TBNZ, |
| 3879 | ARM64_INS_TBXQ = AARCH64_INS_TBXQ, |
| 3880 | ARM64_INS_TBX = AARCH64_INS_TBX, |
| 3881 | ARM64_INS_TBZ = AARCH64_INS_TBZ, |
| 3882 | ARM64_INS_TCANCEL = AARCH64_INS_TCANCEL, |
| 3883 | ARM64_INS_TCOMMIT = AARCH64_INS_TCOMMIT, |
| 3884 | ARM64_INS_TRCIT = AARCH64_INS_TRCIT, |
| 3885 | ARM64_INS_TRN1 = AARCH64_INS_TRN1, |
| 3886 | ARM64_INS_TRN2 = AARCH64_INS_TRN2, |
| 3887 | ARM64_INS_TSB = AARCH64_INS_TSB, |
| 3888 | ARM64_INS_TSTART = AARCH64_INS_TSTART, |
| 3889 | ARM64_INS_TTEST = AARCH64_INS_TTEST, |
| 3890 | ARM64_INS_UABALB = AARCH64_INS_UABALB, |
| 3891 | ARM64_INS_UABALT = AARCH64_INS_UABALT, |
| 3892 | ARM64_INS_UABAL2 = AARCH64_INS_UABAL2, |
| 3893 | ARM64_INS_UABAL = AARCH64_INS_UABAL, |
| 3894 | ARM64_INS_UABA = AARCH64_INS_UABA, |
| 3895 | ARM64_INS_UABDLB = AARCH64_INS_UABDLB, |
| 3896 | ARM64_INS_UABDLT = AARCH64_INS_UABDLT, |
| 3897 | ARM64_INS_UABDL2 = AARCH64_INS_UABDL2, |
| 3898 | ARM64_INS_UABDL = AARCH64_INS_UABDL, |
| 3899 | ARM64_INS_UABD = AARCH64_INS_UABD, |
| 3900 | ARM64_INS_UADALP = AARCH64_INS_UADALP, |
| 3901 | ARM64_INS_UADDLB = AARCH64_INS_UADDLB, |
| 3902 | ARM64_INS_UADDLP = AARCH64_INS_UADDLP, |
| 3903 | ARM64_INS_UADDLT = AARCH64_INS_UADDLT, |
| 3904 | ARM64_INS_UADDLV = AARCH64_INS_UADDLV, |
| 3905 | ARM64_INS_UADDL2 = AARCH64_INS_UADDL2, |
| 3906 | ARM64_INS_UADDL = AARCH64_INS_UADDL, |
| 3907 | ARM64_INS_UADDV = AARCH64_INS_UADDV, |
| 3908 | ARM64_INS_UADDWB = AARCH64_INS_UADDWB, |
| 3909 | ARM64_INS_UADDWT = AARCH64_INS_UADDWT, |
| 3910 | ARM64_INS_UADDW2 = AARCH64_INS_UADDW2, |
| 3911 | ARM64_INS_UADDW = AARCH64_INS_UADDW, |
| 3912 | ARM64_INS_UBFM = AARCH64_INS_UBFM, |
| 3913 | ARM64_INS_UCLAMP = AARCH64_INS_UCLAMP, |
| 3914 | ARM64_INS_UCVTF = AARCH64_INS_UCVTF, |
| 3915 | ARM64_INS_UDF = AARCH64_INS_UDF, |
| 3916 | ARM64_INS_UDIVR = AARCH64_INS_UDIVR, |
| 3917 | ARM64_INS_UDIV = AARCH64_INS_UDIV, |
| 3918 | ARM64_INS_UDOT = AARCH64_INS_UDOT, |
| 3919 | ARM64_INS_UHADD = AARCH64_INS_UHADD, |
| 3920 | ARM64_INS_UHSUBR = AARCH64_INS_UHSUBR, |
| 3921 | ARM64_INS_UHSUB = AARCH64_INS_UHSUB, |
| 3922 | ARM64_INS_UMADDL = AARCH64_INS_UMADDL, |
| 3923 | ARM64_INS_UMAXP = AARCH64_INS_UMAXP, |
| 3924 | ARM64_INS_UMAXQV = AARCH64_INS_UMAXQV, |
| 3925 | ARM64_INS_UMAXV = AARCH64_INS_UMAXV, |
| 3926 | ARM64_INS_UMAX = AARCH64_INS_UMAX, |
| 3927 | ARM64_INS_UMINP = AARCH64_INS_UMINP, |
| 3928 | ARM64_INS_UMINQV = AARCH64_INS_UMINQV, |
| 3929 | ARM64_INS_UMINV = AARCH64_INS_UMINV, |
| 3930 | ARM64_INS_UMIN = AARCH64_INS_UMIN, |
| 3931 | ARM64_INS_UMLALB = AARCH64_INS_UMLALB, |
| 3932 | ARM64_INS_UMLALL = AARCH64_INS_UMLALL, |
| 3933 | ARM64_INS_UMLALT = AARCH64_INS_UMLALT, |
| 3934 | ARM64_INS_UMLAL = AARCH64_INS_UMLAL, |
| 3935 | ARM64_INS_UMLAL2 = AARCH64_INS_UMLAL2, |
| 3936 | ARM64_INS_UMLSLB = AARCH64_INS_UMLSLB, |
| 3937 | ARM64_INS_UMLSLL = AARCH64_INS_UMLSLL, |
| 3938 | ARM64_INS_UMLSLT = AARCH64_INS_UMLSLT, |
| 3939 | ARM64_INS_UMLSL = AARCH64_INS_UMLSL, |
| 3940 | ARM64_INS_UMLSL2 = AARCH64_INS_UMLSL2, |
| 3941 | ARM64_INS_UMMLA = AARCH64_INS_UMMLA, |
| 3942 | ARM64_INS_UMOPA = AARCH64_INS_UMOPA, |
| 3943 | ARM64_INS_UMOPS = AARCH64_INS_UMOPS, |
| 3944 | ARM64_INS_UMOV = AARCH64_INS_UMOV, |
| 3945 | ARM64_INS_UMSUBL = AARCH64_INS_UMSUBL, |
| 3946 | ARM64_INS_UMULH = AARCH64_INS_UMULH, |
| 3947 | ARM64_INS_UMULLB = AARCH64_INS_UMULLB, |
| 3948 | ARM64_INS_UMULLT = AARCH64_INS_UMULLT, |
| 3949 | ARM64_INS_UMULL2 = AARCH64_INS_UMULL2, |
| 3950 | ARM64_INS_UMULL = AARCH64_INS_UMULL, |
| 3951 | ARM64_INS_UQADD = AARCH64_INS_UQADD, |
| 3952 | ARM64_INS_UQCVTN = AARCH64_INS_UQCVTN, |
| 3953 | ARM64_INS_UQCVT = AARCH64_INS_UQCVT, |
| 3954 | ARM64_INS_UQDECB = AARCH64_INS_UQDECB, |
| 3955 | ARM64_INS_UQDECD = AARCH64_INS_UQDECD, |
| 3956 | ARM64_INS_UQDECH = AARCH64_INS_UQDECH, |
| 3957 | ARM64_INS_UQDECP = AARCH64_INS_UQDECP, |
| 3958 | ARM64_INS_UQDECW = AARCH64_INS_UQDECW, |
| 3959 | ARM64_INS_UQINCB = AARCH64_INS_UQINCB, |
| 3960 | ARM64_INS_UQINCD = AARCH64_INS_UQINCD, |
| 3961 | ARM64_INS_UQINCH = AARCH64_INS_UQINCH, |
| 3962 | ARM64_INS_UQINCP = AARCH64_INS_UQINCP, |
| 3963 | ARM64_INS_UQINCW = AARCH64_INS_UQINCW, |
| 3964 | ARM64_INS_UQRSHLR = AARCH64_INS_UQRSHLR, |
| 3965 | ARM64_INS_UQRSHL = AARCH64_INS_UQRSHL, |
| 3966 | ARM64_INS_UQRSHRNB = AARCH64_INS_UQRSHRNB, |
| 3967 | ARM64_INS_UQRSHRNT = AARCH64_INS_UQRSHRNT, |
| 3968 | ARM64_INS_UQRSHRN = AARCH64_INS_UQRSHRN, |
| 3969 | ARM64_INS_UQRSHRN2 = AARCH64_INS_UQRSHRN2, |
| 3970 | ARM64_INS_UQRSHR = AARCH64_INS_UQRSHR, |
| 3971 | ARM64_INS_UQSHLR = AARCH64_INS_UQSHLR, |
| 3972 | ARM64_INS_UQSHL = AARCH64_INS_UQSHL, |
| 3973 | ARM64_INS_UQSHRNB = AARCH64_INS_UQSHRNB, |
| 3974 | ARM64_INS_UQSHRNT = AARCH64_INS_UQSHRNT, |
| 3975 | ARM64_INS_UQSHRN = AARCH64_INS_UQSHRN, |
| 3976 | ARM64_INS_UQSHRN2 = AARCH64_INS_UQSHRN2, |
| 3977 | ARM64_INS_UQSUBR = AARCH64_INS_UQSUBR, |
| 3978 | ARM64_INS_UQSUB = AARCH64_INS_UQSUB, |
| 3979 | ARM64_INS_UQXTNB = AARCH64_INS_UQXTNB, |
| 3980 | ARM64_INS_UQXTNT = AARCH64_INS_UQXTNT, |
| 3981 | ARM64_INS_UQXTN2 = AARCH64_INS_UQXTN2, |
| 3982 | ARM64_INS_UQXTN = AARCH64_INS_UQXTN, |
| 3983 | ARM64_INS_URECPE = AARCH64_INS_URECPE, |
| 3984 | ARM64_INS_URHADD = AARCH64_INS_URHADD, |
| 3985 | ARM64_INS_URSHLR = AARCH64_INS_URSHLR, |
| 3986 | ARM64_INS_URSHL = AARCH64_INS_URSHL, |
| 3987 | ARM64_INS_URSHR = AARCH64_INS_URSHR, |
| 3988 | ARM64_INS_URSQRTE = AARCH64_INS_URSQRTE, |
| 3989 | ARM64_INS_URSRA = AARCH64_INS_URSRA, |
| 3990 | ARM64_INS_USDOT = AARCH64_INS_USDOT, |
| 3991 | ARM64_INS_USHLLB = AARCH64_INS_USHLLB, |
| 3992 | ARM64_INS_USHLLT = AARCH64_INS_USHLLT, |
| 3993 | ARM64_INS_USHLL2 = AARCH64_INS_USHLL2, |
| 3994 | ARM64_INS_USHLL = AARCH64_INS_USHLL, |
| 3995 | ARM64_INS_USHL = AARCH64_INS_USHL, |
| 3996 | ARM64_INS_USHR = AARCH64_INS_USHR, |
| 3997 | ARM64_INS_USMLALL = AARCH64_INS_USMLALL, |
| 3998 | ARM64_INS_USMMLA = AARCH64_INS_USMMLA, |
| 3999 | ARM64_INS_USMOPA = AARCH64_INS_USMOPA, |
| 4000 | ARM64_INS_USMOPS = AARCH64_INS_USMOPS, |
| 4001 | ARM64_INS_USQADD = AARCH64_INS_USQADD, |
| 4002 | ARM64_INS_USRA = AARCH64_INS_USRA, |
| 4003 | ARM64_INS_USUBLB = AARCH64_INS_USUBLB, |
| 4004 | ARM64_INS_USUBLT = AARCH64_INS_USUBLT, |
| 4005 | ARM64_INS_USUBL2 = AARCH64_INS_USUBL2, |
| 4006 | ARM64_INS_USUBL = AARCH64_INS_USUBL, |
| 4007 | ARM64_INS_USUBWB = AARCH64_INS_USUBWB, |
| 4008 | ARM64_INS_USUBWT = AARCH64_INS_USUBWT, |
| 4009 | ARM64_INS_USUBW2 = AARCH64_INS_USUBW2, |
| 4010 | ARM64_INS_USUBW = AARCH64_INS_USUBW, |
| 4011 | ARM64_INS_USVDOT = AARCH64_INS_USVDOT, |
| 4012 | ARM64_INS_UUNPKHI = AARCH64_INS_UUNPKHI, |
| 4013 | ARM64_INS_UUNPKLO = AARCH64_INS_UUNPKLO, |
| 4014 | ARM64_INS_UUNPK = AARCH64_INS_UUNPK, |
| 4015 | ARM64_INS_UVDOT = AARCH64_INS_UVDOT, |
| 4016 | ARM64_INS_UXTB = AARCH64_INS_UXTB, |
| 4017 | ARM64_INS_UXTH = AARCH64_INS_UXTH, |
| 4018 | ARM64_INS_UXTW = AARCH64_INS_UXTW, |
| 4019 | ARM64_INS_UZP1 = AARCH64_INS_UZP1, |
| 4020 | ARM64_INS_UZP2 = AARCH64_INS_UZP2, |
| 4021 | ARM64_INS_UZPQ1 = AARCH64_INS_UZPQ1, |
| 4022 | ARM64_INS_UZPQ2 = AARCH64_INS_UZPQ2, |
| 4023 | ARM64_INS_UZP = AARCH64_INS_UZP, |
| 4024 | ARM64_INS_WFET = AARCH64_INS_WFET, |
| 4025 | ARM64_INS_WFIT = AARCH64_INS_WFIT, |
| 4026 | ARM64_INS_WHILEGE = AARCH64_INS_WHILEGE, |
| 4027 | ARM64_INS_WHILEGT = AARCH64_INS_WHILEGT, |
| 4028 | ARM64_INS_WHILEHI = AARCH64_INS_WHILEHI, |
| 4029 | ARM64_INS_WHILEHS = AARCH64_INS_WHILEHS, |
| 4030 | ARM64_INS_WHILELE = AARCH64_INS_WHILELE, |
| 4031 | ARM64_INS_WHILELO = AARCH64_INS_WHILELO, |
| 4032 | ARM64_INS_WHILELS = AARCH64_INS_WHILELS, |
| 4033 | ARM64_INS_WHILELT = AARCH64_INS_WHILELT, |
| 4034 | ARM64_INS_WHILERW = AARCH64_INS_WHILERW, |
| 4035 | ARM64_INS_WHILEWR = AARCH64_INS_WHILEWR, |
| 4036 | ARM64_INS_WRFFR = AARCH64_INS_WRFFR, |
| 4037 | ARM64_INS_XAFLAG = AARCH64_INS_XAFLAG, |
| 4038 | ARM64_INS_XAR = AARCH64_INS_XAR, |
| 4039 | ARM64_INS_XPACD = AARCH64_INS_XPACD, |
| 4040 | ARM64_INS_XPACI = AARCH64_INS_XPACI, |
| 4041 | ARM64_INS_XTN2 = AARCH64_INS_XTN2, |
| 4042 | ARM64_INS_XTN = AARCH64_INS_XTN, |
| 4043 | ARM64_INS_ZERO = AARCH64_INS_ZERO, |
| 4044 | ARM64_INS_ZIP1 = AARCH64_INS_ZIP1, |
| 4045 | ARM64_INS_ZIP2 = AARCH64_INS_ZIP2, |
| 4046 | ARM64_INS_ZIPQ1 = AARCH64_INS_ZIPQ1, |
| 4047 | ARM64_INS_ZIPQ2 = AARCH64_INS_ZIPQ2, |
| 4048 | ARM64_INS_ZIP = AARCH64_INS_ZIP, |
| 4049 | |
| 4050 | |
| 4051 | ARM64_INS_ENDING = AARCH64_INS_ENDING, |
| 4052 | |
| 4053 | ARM64_INS_ALIAS_BEGIN = AARCH64_INS_ALIAS_BEGIN, |
| 4054 | |
| 4055 | ARM64_INS_ALIAS_ADDPT = AARCH64_INS_ALIAS_ADDPT, |
| 4056 | ARM64_INS_ALIAS_GCSB = AARCH64_INS_ALIAS_GCSB, |
| 4057 | ARM64_INS_ALIAS_GCSPOPM = AARCH64_INS_ALIAS_GCSPOPM, |
| 4058 | ARM64_INS_ALIAS_LDAPUR = AARCH64_INS_ALIAS_LDAPUR, |
| 4059 | ARM64_INS_ALIAS_STLLRB = AARCH64_INS_ALIAS_STLLRB, |
| 4060 | ARM64_INS_ALIAS_STLLRH = AARCH64_INS_ALIAS_STLLRH, |
| 4061 | ARM64_INS_ALIAS_STLLR = AARCH64_INS_ALIAS_STLLR, |
| 4062 | ARM64_INS_ALIAS_STLRB = AARCH64_INS_ALIAS_STLRB, |
| 4063 | ARM64_INS_ALIAS_STLRH = AARCH64_INS_ALIAS_STLRH, |
| 4064 | ARM64_INS_ALIAS_STLR = AARCH64_INS_ALIAS_STLR, |
| 4065 | ARM64_INS_ALIAS_STLUR = AARCH64_INS_ALIAS_STLUR, |
| 4066 | ARM64_INS_ALIAS_SUBPT = AARCH64_INS_ALIAS_SUBPT, |
| 4067 | ARM64_INS_ALIAS_LDRAA = AARCH64_INS_ALIAS_LDRAA, |
| 4068 | ARM64_INS_ALIAS_ADD = AARCH64_INS_ALIAS_ADD, |
| 4069 | ARM64_INS_ALIAS_CMN = AARCH64_INS_ALIAS_CMN, |
| 4070 | ARM64_INS_ALIAS_ADDS = AARCH64_INS_ALIAS_ADDS, |
| 4071 | ARM64_INS_ALIAS_AND = AARCH64_INS_ALIAS_AND, |
| 4072 | ARM64_INS_ALIAS_ANDS = AARCH64_INS_ALIAS_ANDS, |
| 4073 | ARM64_INS_ALIAS_LDR = AARCH64_INS_ALIAS_LDR, |
| 4074 | ARM64_INS_ALIAS_STR = AARCH64_INS_ALIAS_STR, |
| 4075 | ARM64_INS_ALIAS_LDRB = AARCH64_INS_ALIAS_LDRB, |
| 4076 | ARM64_INS_ALIAS_STRB = AARCH64_INS_ALIAS_STRB, |
| 4077 | ARM64_INS_ALIAS_LDRH = AARCH64_INS_ALIAS_LDRH, |
| 4078 | ARM64_INS_ALIAS_STRH = AARCH64_INS_ALIAS_STRH, |
| 4079 | ARM64_INS_ALIAS_PRFM = AARCH64_INS_ALIAS_PRFM, |
| 4080 | ARM64_INS_ALIAS_LDAPURB = AARCH64_INS_ALIAS_LDAPURB, |
| 4081 | ARM64_INS_ALIAS_STLURB = AARCH64_INS_ALIAS_STLURB, |
| 4082 | ARM64_INS_ALIAS_LDUR = AARCH64_INS_ALIAS_LDUR, |
| 4083 | ARM64_INS_ALIAS_STUR = AARCH64_INS_ALIAS_STUR, |
| 4084 | ARM64_INS_ALIAS_PRFUM = AARCH64_INS_ALIAS_PRFUM, |
| 4085 | ARM64_INS_ALIAS_LDTR = AARCH64_INS_ALIAS_LDTR, |
| 4086 | ARM64_INS_ALIAS_STTR = AARCH64_INS_ALIAS_STTR, |
| 4087 | ARM64_INS_ALIAS_LDP = AARCH64_INS_ALIAS_LDP, |
| 4088 | ARM64_INS_ALIAS_STGP = AARCH64_INS_ALIAS_STGP, |
| 4089 | ARM64_INS_ALIAS_LDNP = AARCH64_INS_ALIAS_LDNP, |
| 4090 | ARM64_INS_ALIAS_STNP = AARCH64_INS_ALIAS_STNP, |
| 4091 | ARM64_INS_ALIAS_STG = AARCH64_INS_ALIAS_STG, |
| 4092 | ARM64_INS_ALIAS_MOV = AARCH64_INS_ALIAS_MOV, |
| 4093 | ARM64_INS_ALIAS_LD1 = AARCH64_INS_ALIAS_LD1, |
| 4094 | ARM64_INS_ALIAS_LD1R = AARCH64_INS_ALIAS_LD1R, |
| 4095 | ARM64_INS_ALIAS_STADDLB = AARCH64_INS_ALIAS_STADDLB, |
| 4096 | ARM64_INS_ALIAS_STADDLH = AARCH64_INS_ALIAS_STADDLH, |
| 4097 | ARM64_INS_ALIAS_STADDL = AARCH64_INS_ALIAS_STADDL, |
| 4098 | ARM64_INS_ALIAS_STADDB = AARCH64_INS_ALIAS_STADDB, |
| 4099 | ARM64_INS_ALIAS_STADDH = AARCH64_INS_ALIAS_STADDH, |
| 4100 | ARM64_INS_ALIAS_STADD = AARCH64_INS_ALIAS_STADD, |
| 4101 | ARM64_INS_ALIAS_PTRUE = AARCH64_INS_ALIAS_PTRUE, |
| 4102 | ARM64_INS_ALIAS_PTRUES = AARCH64_INS_ALIAS_PTRUES, |
| 4103 | ARM64_INS_ALIAS_CNTB = AARCH64_INS_ALIAS_CNTB, |
| 4104 | ARM64_INS_ALIAS_SQINCH = AARCH64_INS_ALIAS_SQINCH, |
| 4105 | ARM64_INS_ALIAS_INCB = AARCH64_INS_ALIAS_INCB, |
| 4106 | ARM64_INS_ALIAS_SQINCB = AARCH64_INS_ALIAS_SQINCB, |
| 4107 | ARM64_INS_ALIAS_UQINCB = AARCH64_INS_ALIAS_UQINCB, |
| 4108 | ARM64_INS_ALIAS_ORR = AARCH64_INS_ALIAS_ORR, |
| 4109 | ARM64_INS_ALIAS_DUPM = AARCH64_INS_ALIAS_DUPM, |
| 4110 | ARM64_INS_ALIAS_FMOV = AARCH64_INS_ALIAS_FMOV, |
| 4111 | ARM64_INS_ALIAS_EOR3 = AARCH64_INS_ALIAS_EOR3, |
| 4112 | ARM64_INS_ALIAS_ST1B = AARCH64_INS_ALIAS_ST1B, |
| 4113 | ARM64_INS_ALIAS_ST2B = AARCH64_INS_ALIAS_ST2B, |
| 4114 | ARM64_INS_ALIAS_ST2Q = AARCH64_INS_ALIAS_ST2Q, |
| 4115 | ARM64_INS_ALIAS_STNT1B = AARCH64_INS_ALIAS_STNT1B, |
| 4116 | ARM64_INS_ALIAS_LD1B = AARCH64_INS_ALIAS_LD1B, |
| 4117 | ARM64_INS_ALIAS_LDNT1B = AARCH64_INS_ALIAS_LDNT1B, |
| 4118 | ARM64_INS_ALIAS_LD1RQB = AARCH64_INS_ALIAS_LD1RQB, |
| 4119 | ARM64_INS_ALIAS_LD1RB = AARCH64_INS_ALIAS_LD1RB, |
| 4120 | ARM64_INS_ALIAS_LDFF1B = AARCH64_INS_ALIAS_LDFF1B, |
| 4121 | ARM64_INS_ALIAS_LDNF1B = AARCH64_INS_ALIAS_LDNF1B, |
| 4122 | ARM64_INS_ALIAS_LD2B = AARCH64_INS_ALIAS_LD2B, |
| 4123 | ARM64_INS_ALIAS_LD1SB = AARCH64_INS_ALIAS_LD1SB, |
| 4124 | ARM64_INS_ALIAS_PRFB = AARCH64_INS_ALIAS_PRFB, |
| 4125 | ARM64_INS_ALIAS_LDNT1SB = AARCH64_INS_ALIAS_LDNT1SB, |
| 4126 | ARM64_INS_ALIAS_LD1ROB = AARCH64_INS_ALIAS_LD1ROB, |
| 4127 | ARM64_INS_ALIAS_LD1Q = AARCH64_INS_ALIAS_LD1Q, |
| 4128 | ARM64_INS_ALIAS_ST1Q = AARCH64_INS_ALIAS_ST1Q, |
| 4129 | ARM64_INS_ALIAS_LD1W = AARCH64_INS_ALIAS_LD1W, |
| 4130 | ARM64_INS_ALIAS_PMOV = AARCH64_INS_ALIAS_PMOV, |
| 4131 | ARM64_INS_ALIAS_SMSTART = AARCH64_INS_ALIAS_SMSTART, |
| 4132 | ARM64_INS_ALIAS_SMSTOP = AARCH64_INS_ALIAS_SMSTOP, |
| 4133 | ARM64_INS_ALIAS_ZERO = AARCH64_INS_ALIAS_ZERO, |
| 4134 | ARM64_INS_ALIAS_MOVT = AARCH64_INS_ALIAS_MOVT, |
| 4135 | ARM64_INS_ALIAS_NOP = AARCH64_INS_ALIAS_NOP, |
| 4136 | ARM64_INS_ALIAS_YIELD = AARCH64_INS_ALIAS_YIELD, |
| 4137 | ARM64_INS_ALIAS_WFE = AARCH64_INS_ALIAS_WFE, |
| 4138 | ARM64_INS_ALIAS_WFI = AARCH64_INS_ALIAS_WFI, |
| 4139 | ARM64_INS_ALIAS_SEV = AARCH64_INS_ALIAS_SEV, |
| 4140 | ARM64_INS_ALIAS_SEVL = AARCH64_INS_ALIAS_SEVL, |
| 4141 | ARM64_INS_ALIAS_DGH = AARCH64_INS_ALIAS_DGH, |
| 4142 | ARM64_INS_ALIAS_ESB = AARCH64_INS_ALIAS_ESB, |
| 4143 | ARM64_INS_ALIAS_CSDB = AARCH64_INS_ALIAS_CSDB, |
| 4144 | ARM64_INS_ALIAS_BTI = AARCH64_INS_ALIAS_BTI, |
| 4145 | ARM64_INS_ALIAS_PSB = AARCH64_INS_ALIAS_PSB, |
| 4146 | ARM64_INS_ALIAS_CHKFEAT = AARCH64_INS_ALIAS_CHKFEAT, |
| 4147 | ARM64_INS_ALIAS_PACIAZ = AARCH64_INS_ALIAS_PACIAZ, |
| 4148 | ARM64_INS_ALIAS_PACIBZ = AARCH64_INS_ALIAS_PACIBZ, |
| 4149 | ARM64_INS_ALIAS_AUTIAZ = AARCH64_INS_ALIAS_AUTIAZ, |
| 4150 | ARM64_INS_ALIAS_AUTIBZ = AARCH64_INS_ALIAS_AUTIBZ, |
| 4151 | ARM64_INS_ALIAS_PACIASP = AARCH64_INS_ALIAS_PACIASP, |
| 4152 | ARM64_INS_ALIAS_PACIBSP = AARCH64_INS_ALIAS_PACIBSP, |
| 4153 | ARM64_INS_ALIAS_AUTIASP = AARCH64_INS_ALIAS_AUTIASP, |
| 4154 | ARM64_INS_ALIAS_AUTIBSP = AARCH64_INS_ALIAS_AUTIBSP, |
| 4155 | ARM64_INS_ALIAS_PACIA1716 = AARCH64_INS_ALIAS_PACIA1716, |
| 4156 | ARM64_INS_ALIAS_PACIB1716 = AARCH64_INS_ALIAS_PACIB1716, |
| 4157 | ARM64_INS_ALIAS_AUTIA1716 = AARCH64_INS_ALIAS_AUTIA1716, |
| 4158 | ARM64_INS_ALIAS_AUTIB1716 = AARCH64_INS_ALIAS_AUTIB1716, |
| 4159 | ARM64_INS_ALIAS_XPACLRI = AARCH64_INS_ALIAS_XPACLRI, |
| 4160 | ARM64_INS_ALIAS_LDRAB = AARCH64_INS_ALIAS_LDRAB, |
| 4161 | ARM64_INS_ALIAS_PACM = AARCH64_INS_ALIAS_PACM, |
| 4162 | ARM64_INS_ALIAS_CLREX = AARCH64_INS_ALIAS_CLREX, |
| 4163 | ARM64_INS_ALIAS_ISB = AARCH64_INS_ALIAS_ISB, |
| 4164 | ARM64_INS_ALIAS_SSBB = AARCH64_INS_ALIAS_SSBB, |
| 4165 | ARM64_INS_ALIAS_PSSBB = AARCH64_INS_ALIAS_PSSBB, |
| 4166 | ARM64_INS_ALIAS_DFB = AARCH64_INS_ALIAS_DFB, |
| 4167 | ARM64_INS_ALIAS_SYS = AARCH64_INS_ALIAS_SYS, |
| 4168 | ARM64_INS_ALIAS_MOVN = AARCH64_INS_ALIAS_MOVN, |
| 4169 | ARM64_INS_ALIAS_MOVZ = AARCH64_INS_ALIAS_MOVZ, |
| 4170 | ARM64_INS_ALIAS_NGC = AARCH64_INS_ALIAS_NGC, |
| 4171 | ARM64_INS_ALIAS_NGCS = AARCH64_INS_ALIAS_NGCS, |
| 4172 | ARM64_INS_ALIAS_SUB = AARCH64_INS_ALIAS_SUB, |
| 4173 | ARM64_INS_ALIAS_CMP = AARCH64_INS_ALIAS_CMP, |
| 4174 | ARM64_INS_ALIAS_SUBS = AARCH64_INS_ALIAS_SUBS, |
| 4175 | ARM64_INS_ALIAS_NEG = AARCH64_INS_ALIAS_NEG, |
| 4176 | ARM64_INS_ALIAS_NEGS = AARCH64_INS_ALIAS_NEGS, |
| 4177 | ARM64_INS_ALIAS_MUL = AARCH64_INS_ALIAS_MUL, |
| 4178 | ARM64_INS_ALIAS_MNEG = AARCH64_INS_ALIAS_MNEG, |
| 4179 | ARM64_INS_ALIAS_SMULL = AARCH64_INS_ALIAS_SMULL, |
| 4180 | ARM64_INS_ALIAS_SMNEGL = AARCH64_INS_ALIAS_SMNEGL, |
| 4181 | ARM64_INS_ALIAS_UMULL = AARCH64_INS_ALIAS_UMULL, |
| 4182 | ARM64_INS_ALIAS_UMNEGL = AARCH64_INS_ALIAS_UMNEGL, |
| 4183 | ARM64_INS_ALIAS_STCLRLB = AARCH64_INS_ALIAS_STCLRLB, |
| 4184 | ARM64_INS_ALIAS_STCLRLH = AARCH64_INS_ALIAS_STCLRLH, |
| 4185 | ARM64_INS_ALIAS_STCLRL = AARCH64_INS_ALIAS_STCLRL, |
| 4186 | ARM64_INS_ALIAS_STCLRB = AARCH64_INS_ALIAS_STCLRB, |
| 4187 | ARM64_INS_ALIAS_STCLRH = AARCH64_INS_ALIAS_STCLRH, |
| 4188 | ARM64_INS_ALIAS_STCLR = AARCH64_INS_ALIAS_STCLR, |
| 4189 | ARM64_INS_ALIAS_STEORLB = AARCH64_INS_ALIAS_STEORLB, |
| 4190 | ARM64_INS_ALIAS_STEORLH = AARCH64_INS_ALIAS_STEORLH, |
| 4191 | ARM64_INS_ALIAS_STEORL = AARCH64_INS_ALIAS_STEORL, |
| 4192 | ARM64_INS_ALIAS_STEORB = AARCH64_INS_ALIAS_STEORB, |
| 4193 | ARM64_INS_ALIAS_STEORH = AARCH64_INS_ALIAS_STEORH, |
| 4194 | ARM64_INS_ALIAS_STEOR = AARCH64_INS_ALIAS_STEOR, |
| 4195 | ARM64_INS_ALIAS_STSETLB = AARCH64_INS_ALIAS_STSETLB, |
| 4196 | ARM64_INS_ALIAS_STSETLH = AARCH64_INS_ALIAS_STSETLH, |
| 4197 | ARM64_INS_ALIAS_STSETL = AARCH64_INS_ALIAS_STSETL, |
| 4198 | ARM64_INS_ALIAS_STSETB = AARCH64_INS_ALIAS_STSETB, |
| 4199 | ARM64_INS_ALIAS_STSETH = AARCH64_INS_ALIAS_STSETH, |
| 4200 | ARM64_INS_ALIAS_STSET = AARCH64_INS_ALIAS_STSET, |
| 4201 | ARM64_INS_ALIAS_STSMAXLB = AARCH64_INS_ALIAS_STSMAXLB, |
| 4202 | ARM64_INS_ALIAS_STSMAXLH = AARCH64_INS_ALIAS_STSMAXLH, |
| 4203 | ARM64_INS_ALIAS_STSMAXL = AARCH64_INS_ALIAS_STSMAXL, |
| 4204 | ARM64_INS_ALIAS_STSMAXB = AARCH64_INS_ALIAS_STSMAXB, |
| 4205 | ARM64_INS_ALIAS_STSMAXH = AARCH64_INS_ALIAS_STSMAXH, |
| 4206 | ARM64_INS_ALIAS_STSMAX = AARCH64_INS_ALIAS_STSMAX, |
| 4207 | ARM64_INS_ALIAS_STSMINLB = AARCH64_INS_ALIAS_STSMINLB, |
| 4208 | ARM64_INS_ALIAS_STSMINLH = AARCH64_INS_ALIAS_STSMINLH, |
| 4209 | ARM64_INS_ALIAS_STSMINL = AARCH64_INS_ALIAS_STSMINL, |
| 4210 | ARM64_INS_ALIAS_STSMINB = AARCH64_INS_ALIAS_STSMINB, |
| 4211 | ARM64_INS_ALIAS_STSMINH = AARCH64_INS_ALIAS_STSMINH, |
| 4212 | ARM64_INS_ALIAS_STSMIN = AARCH64_INS_ALIAS_STSMIN, |
| 4213 | ARM64_INS_ALIAS_STUMAXLB = AARCH64_INS_ALIAS_STUMAXLB, |
| 4214 | ARM64_INS_ALIAS_STUMAXLH = AARCH64_INS_ALIAS_STUMAXLH, |
| 4215 | ARM64_INS_ALIAS_STUMAXL = AARCH64_INS_ALIAS_STUMAXL, |
| 4216 | ARM64_INS_ALIAS_STUMAXB = AARCH64_INS_ALIAS_STUMAXB, |
| 4217 | ARM64_INS_ALIAS_STUMAXH = AARCH64_INS_ALIAS_STUMAXH, |
| 4218 | ARM64_INS_ALIAS_STUMAX = AARCH64_INS_ALIAS_STUMAX, |
| 4219 | ARM64_INS_ALIAS_STUMINLB = AARCH64_INS_ALIAS_STUMINLB, |
| 4220 | ARM64_INS_ALIAS_STUMINLH = AARCH64_INS_ALIAS_STUMINLH, |
| 4221 | ARM64_INS_ALIAS_STUMINL = AARCH64_INS_ALIAS_STUMINL, |
| 4222 | ARM64_INS_ALIAS_STUMINB = AARCH64_INS_ALIAS_STUMINB, |
| 4223 | ARM64_INS_ALIAS_STUMINH = AARCH64_INS_ALIAS_STUMINH, |
| 4224 | ARM64_INS_ALIAS_STUMIN = AARCH64_INS_ALIAS_STUMIN, |
| 4225 | ARM64_INS_ALIAS_IRG = AARCH64_INS_ALIAS_IRG, |
| 4226 | ARM64_INS_ALIAS_LDG = AARCH64_INS_ALIAS_LDG, |
| 4227 | ARM64_INS_ALIAS_STZG = AARCH64_INS_ALIAS_STZG, |
| 4228 | ARM64_INS_ALIAS_ST2G = AARCH64_INS_ALIAS_ST2G, |
| 4229 | ARM64_INS_ALIAS_STZ2G = AARCH64_INS_ALIAS_STZ2G, |
| 4230 | ARM64_INS_ALIAS_BICS = AARCH64_INS_ALIAS_BICS, |
| 4231 | ARM64_INS_ALIAS_BIC = AARCH64_INS_ALIAS_BIC, |
| 4232 | ARM64_INS_ALIAS_EON = AARCH64_INS_ALIAS_EON, |
| 4233 | ARM64_INS_ALIAS_EOR = AARCH64_INS_ALIAS_EOR, |
| 4234 | ARM64_INS_ALIAS_ORN = AARCH64_INS_ALIAS_ORN, |
| 4235 | ARM64_INS_ALIAS_MVN = AARCH64_INS_ALIAS_MVN, |
| 4236 | ARM64_INS_ALIAS_TST = AARCH64_INS_ALIAS_TST, |
| 4237 | ARM64_INS_ALIAS_ROR = AARCH64_INS_ALIAS_ROR, |
| 4238 | ARM64_INS_ALIAS_ASR = AARCH64_INS_ALIAS_ASR, |
| 4239 | ARM64_INS_ALIAS_SXTB = AARCH64_INS_ALIAS_SXTB, |
| 4240 | ARM64_INS_ALIAS_SXTH = AARCH64_INS_ALIAS_SXTH, |
| 4241 | ARM64_INS_ALIAS_SXTW = AARCH64_INS_ALIAS_SXTW, |
| 4242 | ARM64_INS_ALIAS_LSR = AARCH64_INS_ALIAS_LSR, |
| 4243 | ARM64_INS_ALIAS_UXTB = AARCH64_INS_ALIAS_UXTB, |
| 4244 | ARM64_INS_ALIAS_UXTH = AARCH64_INS_ALIAS_UXTH, |
| 4245 | ARM64_INS_ALIAS_UXTW = AARCH64_INS_ALIAS_UXTW, |
| 4246 | ARM64_INS_ALIAS_CSET = AARCH64_INS_ALIAS_CSET, |
| 4247 | ARM64_INS_ALIAS_CSETM = AARCH64_INS_ALIAS_CSETM, |
| 4248 | ARM64_INS_ALIAS_CINC = AARCH64_INS_ALIAS_CINC, |
| 4249 | ARM64_INS_ALIAS_CINV = AARCH64_INS_ALIAS_CINV, |
| 4250 | ARM64_INS_ALIAS_CNEG = AARCH64_INS_ALIAS_CNEG, |
| 4251 | ARM64_INS_ALIAS_RET = AARCH64_INS_ALIAS_RET, |
| 4252 | ARM64_INS_ALIAS_DCPS1 = AARCH64_INS_ALIAS_DCPS1, |
| 4253 | ARM64_INS_ALIAS_DCPS2 = AARCH64_INS_ALIAS_DCPS2, |
| 4254 | ARM64_INS_ALIAS_DCPS3 = AARCH64_INS_ALIAS_DCPS3, |
| 4255 | ARM64_INS_ALIAS_LDPSW = AARCH64_INS_ALIAS_LDPSW, |
| 4256 | ARM64_INS_ALIAS_LDRSH = AARCH64_INS_ALIAS_LDRSH, |
| 4257 | ARM64_INS_ALIAS_LDRSB = AARCH64_INS_ALIAS_LDRSB, |
| 4258 | ARM64_INS_ALIAS_LDRSW = AARCH64_INS_ALIAS_LDRSW, |
| 4259 | ARM64_INS_ALIAS_LDURH = AARCH64_INS_ALIAS_LDURH, |
| 4260 | ARM64_INS_ALIAS_LDURB = AARCH64_INS_ALIAS_LDURB, |
| 4261 | ARM64_INS_ALIAS_LDURSH = AARCH64_INS_ALIAS_LDURSH, |
| 4262 | ARM64_INS_ALIAS_LDURSB = AARCH64_INS_ALIAS_LDURSB, |
| 4263 | ARM64_INS_ALIAS_LDURSW = AARCH64_INS_ALIAS_LDURSW, |
| 4264 | ARM64_INS_ALIAS_LDTRH = AARCH64_INS_ALIAS_LDTRH, |
| 4265 | ARM64_INS_ALIAS_LDTRB = AARCH64_INS_ALIAS_LDTRB, |
| 4266 | ARM64_INS_ALIAS_LDTRSH = AARCH64_INS_ALIAS_LDTRSH, |
| 4267 | ARM64_INS_ALIAS_LDTRSB = AARCH64_INS_ALIAS_LDTRSB, |
| 4268 | ARM64_INS_ALIAS_LDTRSW = AARCH64_INS_ALIAS_LDTRSW, |
| 4269 | ARM64_INS_ALIAS_STP = AARCH64_INS_ALIAS_STP, |
| 4270 | ARM64_INS_ALIAS_STURH = AARCH64_INS_ALIAS_STURH, |
| 4271 | ARM64_INS_ALIAS_STURB = AARCH64_INS_ALIAS_STURB, |
| 4272 | ARM64_INS_ALIAS_STLURH = AARCH64_INS_ALIAS_STLURH, |
| 4273 | ARM64_INS_ALIAS_LDAPURSB = AARCH64_INS_ALIAS_LDAPURSB, |
| 4274 | ARM64_INS_ALIAS_LDAPURH = AARCH64_INS_ALIAS_LDAPURH, |
| 4275 | ARM64_INS_ALIAS_LDAPURSH = AARCH64_INS_ALIAS_LDAPURSH, |
| 4276 | ARM64_INS_ALIAS_LDAPURSW = AARCH64_INS_ALIAS_LDAPURSW, |
| 4277 | ARM64_INS_ALIAS_STTRH = AARCH64_INS_ALIAS_STTRH, |
| 4278 | ARM64_INS_ALIAS_STTRB = AARCH64_INS_ALIAS_STTRB, |
| 4279 | ARM64_INS_ALIAS_BIC_4H = AARCH64_INS_ALIAS_BIC_4H, |
| 4280 | ARM64_INS_ALIAS_BIC_8H = AARCH64_INS_ALIAS_BIC_8H, |
| 4281 | ARM64_INS_ALIAS_BIC_2S = AARCH64_INS_ALIAS_BIC_2S, |
| 4282 | ARM64_INS_ALIAS_BIC_4S = AARCH64_INS_ALIAS_BIC_4S, |
| 4283 | ARM64_INS_ALIAS_ORR_4H = AARCH64_INS_ALIAS_ORR_4H, |
| 4284 | ARM64_INS_ALIAS_ORR_8H = AARCH64_INS_ALIAS_ORR_8H, |
| 4285 | ARM64_INS_ALIAS_ORR_2S = AARCH64_INS_ALIAS_ORR_2S, |
| 4286 | ARM64_INS_ALIAS_ORR_4S = AARCH64_INS_ALIAS_ORR_4S, |
| 4287 | ARM64_INS_ALIAS_SXTL_8H = AARCH64_INS_ALIAS_SXTL_8H, |
| 4288 | ARM64_INS_ALIAS_SXTL = AARCH64_INS_ALIAS_SXTL, |
| 4289 | ARM64_INS_ALIAS_SXTL_4S = AARCH64_INS_ALIAS_SXTL_4S, |
| 4290 | ARM64_INS_ALIAS_SXTL_2D = AARCH64_INS_ALIAS_SXTL_2D, |
| 4291 | ARM64_INS_ALIAS_SXTL2_8H = AARCH64_INS_ALIAS_SXTL2_8H, |
| 4292 | ARM64_INS_ALIAS_SXTL2 = AARCH64_INS_ALIAS_SXTL2, |
| 4293 | ARM64_INS_ALIAS_SXTL2_4S = AARCH64_INS_ALIAS_SXTL2_4S, |
| 4294 | ARM64_INS_ALIAS_SXTL2_2D = AARCH64_INS_ALIAS_SXTL2_2D, |
| 4295 | ARM64_INS_ALIAS_UXTL_8H = AARCH64_INS_ALIAS_UXTL_8H, |
| 4296 | ARM64_INS_ALIAS_UXTL = AARCH64_INS_ALIAS_UXTL, |
| 4297 | ARM64_INS_ALIAS_UXTL_4S = AARCH64_INS_ALIAS_UXTL_4S, |
| 4298 | ARM64_INS_ALIAS_UXTL_2D = AARCH64_INS_ALIAS_UXTL_2D, |
| 4299 | ARM64_INS_ALIAS_UXTL2_8H = AARCH64_INS_ALIAS_UXTL2_8H, |
| 4300 | ARM64_INS_ALIAS_UXTL2 = AARCH64_INS_ALIAS_UXTL2, |
| 4301 | ARM64_INS_ALIAS_UXTL2_4S = AARCH64_INS_ALIAS_UXTL2_4S, |
| 4302 | ARM64_INS_ALIAS_UXTL2_2D = AARCH64_INS_ALIAS_UXTL2_2D, |
| 4303 | ARM64_INS_ALIAS_LD2 = AARCH64_INS_ALIAS_LD2, |
| 4304 | ARM64_INS_ALIAS_LD3 = AARCH64_INS_ALIAS_LD3, |
| 4305 | ARM64_INS_ALIAS_LD4 = AARCH64_INS_ALIAS_LD4, |
| 4306 | ARM64_INS_ALIAS_ST1 = AARCH64_INS_ALIAS_ST1, |
| 4307 | ARM64_INS_ALIAS_ST2 = AARCH64_INS_ALIAS_ST2, |
| 4308 | ARM64_INS_ALIAS_ST3 = AARCH64_INS_ALIAS_ST3, |
| 4309 | ARM64_INS_ALIAS_ST4 = AARCH64_INS_ALIAS_ST4, |
| 4310 | ARM64_INS_ALIAS_LD2R = AARCH64_INS_ALIAS_LD2R, |
| 4311 | ARM64_INS_ALIAS_LD3R = AARCH64_INS_ALIAS_LD3R, |
| 4312 | ARM64_INS_ALIAS_LD4R = AARCH64_INS_ALIAS_LD4R, |
| 4313 | ARM64_INS_ALIAS_CLRBHB = AARCH64_INS_ALIAS_CLRBHB, |
| 4314 | ARM64_INS_ALIAS_STILP = AARCH64_INS_ALIAS_STILP, |
| 4315 | ARM64_INS_ALIAS_STL1 = AARCH64_INS_ALIAS_STL1, |
| 4316 | ARM64_INS_ALIAS_SYSP = AARCH64_INS_ALIAS_SYSP, |
| 4317 | ARM64_INS_ALIAS_LD1SW = AARCH64_INS_ALIAS_LD1SW, |
| 4318 | ARM64_INS_ALIAS_LD1H = AARCH64_INS_ALIAS_LD1H, |
| 4319 | ARM64_INS_ALIAS_LD1SH = AARCH64_INS_ALIAS_LD1SH, |
| 4320 | ARM64_INS_ALIAS_LD1D = AARCH64_INS_ALIAS_LD1D, |
| 4321 | ARM64_INS_ALIAS_LD1RSW = AARCH64_INS_ALIAS_LD1RSW, |
| 4322 | ARM64_INS_ALIAS_LD1RH = AARCH64_INS_ALIAS_LD1RH, |
| 4323 | ARM64_INS_ALIAS_LD1RSH = AARCH64_INS_ALIAS_LD1RSH, |
| 4324 | ARM64_INS_ALIAS_LD1RW = AARCH64_INS_ALIAS_LD1RW, |
| 4325 | ARM64_INS_ALIAS_LD1RSB = AARCH64_INS_ALIAS_LD1RSB, |
| 4326 | ARM64_INS_ALIAS_LD1RD = AARCH64_INS_ALIAS_LD1RD, |
| 4327 | ARM64_INS_ALIAS_LD1RQH = AARCH64_INS_ALIAS_LD1RQH, |
| 4328 | ARM64_INS_ALIAS_LD1RQW = AARCH64_INS_ALIAS_LD1RQW, |
| 4329 | ARM64_INS_ALIAS_LD1RQD = AARCH64_INS_ALIAS_LD1RQD, |
| 4330 | ARM64_INS_ALIAS_LDNF1SW = AARCH64_INS_ALIAS_LDNF1SW, |
| 4331 | ARM64_INS_ALIAS_LDNF1H = AARCH64_INS_ALIAS_LDNF1H, |
| 4332 | ARM64_INS_ALIAS_LDNF1SH = AARCH64_INS_ALIAS_LDNF1SH, |
| 4333 | ARM64_INS_ALIAS_LDNF1W = AARCH64_INS_ALIAS_LDNF1W, |
| 4334 | ARM64_INS_ALIAS_LDNF1SB = AARCH64_INS_ALIAS_LDNF1SB, |
| 4335 | ARM64_INS_ALIAS_LDNF1D = AARCH64_INS_ALIAS_LDNF1D, |
| 4336 | ARM64_INS_ALIAS_LDFF1SW = AARCH64_INS_ALIAS_LDFF1SW, |
| 4337 | ARM64_INS_ALIAS_LDFF1H = AARCH64_INS_ALIAS_LDFF1H, |
| 4338 | ARM64_INS_ALIAS_LDFF1SH = AARCH64_INS_ALIAS_LDFF1SH, |
| 4339 | ARM64_INS_ALIAS_LDFF1W = AARCH64_INS_ALIAS_LDFF1W, |
| 4340 | ARM64_INS_ALIAS_LDFF1SB = AARCH64_INS_ALIAS_LDFF1SB, |
| 4341 | ARM64_INS_ALIAS_LDFF1D = AARCH64_INS_ALIAS_LDFF1D, |
| 4342 | ARM64_INS_ALIAS_LD3B = AARCH64_INS_ALIAS_LD3B, |
| 4343 | ARM64_INS_ALIAS_LD4B = AARCH64_INS_ALIAS_LD4B, |
| 4344 | ARM64_INS_ALIAS_LD2H = AARCH64_INS_ALIAS_LD2H, |
| 4345 | ARM64_INS_ALIAS_LD3H = AARCH64_INS_ALIAS_LD3H, |
| 4346 | ARM64_INS_ALIAS_LD4H = AARCH64_INS_ALIAS_LD4H, |
| 4347 | ARM64_INS_ALIAS_LD2W = AARCH64_INS_ALIAS_LD2W, |
| 4348 | ARM64_INS_ALIAS_LD3W = AARCH64_INS_ALIAS_LD3W, |
| 4349 | ARM64_INS_ALIAS_LD4W = AARCH64_INS_ALIAS_LD4W, |
| 4350 | ARM64_INS_ALIAS_LD2D = AARCH64_INS_ALIAS_LD2D, |
| 4351 | ARM64_INS_ALIAS_LD3D = AARCH64_INS_ALIAS_LD3D, |
| 4352 | ARM64_INS_ALIAS_LD4D = AARCH64_INS_ALIAS_LD4D, |
| 4353 | ARM64_INS_ALIAS_LD2Q = AARCH64_INS_ALIAS_LD2Q, |
| 4354 | ARM64_INS_ALIAS_LD3Q = AARCH64_INS_ALIAS_LD3Q, |
| 4355 | ARM64_INS_ALIAS_LD4Q = AARCH64_INS_ALIAS_LD4Q, |
| 4356 | ARM64_INS_ALIAS_LDNT1H = AARCH64_INS_ALIAS_LDNT1H, |
| 4357 | ARM64_INS_ALIAS_LDNT1W = AARCH64_INS_ALIAS_LDNT1W, |
| 4358 | ARM64_INS_ALIAS_LDNT1D = AARCH64_INS_ALIAS_LDNT1D, |
| 4359 | ARM64_INS_ALIAS_ST1H = AARCH64_INS_ALIAS_ST1H, |
| 4360 | ARM64_INS_ALIAS_ST1W = AARCH64_INS_ALIAS_ST1W, |
| 4361 | ARM64_INS_ALIAS_ST1D = AARCH64_INS_ALIAS_ST1D, |
| 4362 | ARM64_INS_ALIAS_ST3B = AARCH64_INS_ALIAS_ST3B, |
| 4363 | ARM64_INS_ALIAS_ST4B = AARCH64_INS_ALIAS_ST4B, |
| 4364 | ARM64_INS_ALIAS_ST2H = AARCH64_INS_ALIAS_ST2H, |
| 4365 | ARM64_INS_ALIAS_ST3H = AARCH64_INS_ALIAS_ST3H, |
| 4366 | ARM64_INS_ALIAS_ST4H = AARCH64_INS_ALIAS_ST4H, |
| 4367 | ARM64_INS_ALIAS_ST2W = AARCH64_INS_ALIAS_ST2W, |
| 4368 | ARM64_INS_ALIAS_ST3W = AARCH64_INS_ALIAS_ST3W, |
| 4369 | ARM64_INS_ALIAS_ST4W = AARCH64_INS_ALIAS_ST4W, |
| 4370 | ARM64_INS_ALIAS_ST2D = AARCH64_INS_ALIAS_ST2D, |
| 4371 | ARM64_INS_ALIAS_ST3D = AARCH64_INS_ALIAS_ST3D, |
| 4372 | ARM64_INS_ALIAS_ST4D = AARCH64_INS_ALIAS_ST4D, |
| 4373 | ARM64_INS_ALIAS_ST3Q = AARCH64_INS_ALIAS_ST3Q, |
| 4374 | ARM64_INS_ALIAS_ST4Q = AARCH64_INS_ALIAS_ST4Q, |
| 4375 | ARM64_INS_ALIAS_STNT1H = AARCH64_INS_ALIAS_STNT1H, |
| 4376 | ARM64_INS_ALIAS_STNT1W = AARCH64_INS_ALIAS_STNT1W, |
| 4377 | ARM64_INS_ALIAS_STNT1D = AARCH64_INS_ALIAS_STNT1D, |
| 4378 | ARM64_INS_ALIAS_PRFH = AARCH64_INS_ALIAS_PRFH, |
| 4379 | ARM64_INS_ALIAS_PRFW = AARCH64_INS_ALIAS_PRFW, |
| 4380 | ARM64_INS_ALIAS_PRFD = AARCH64_INS_ALIAS_PRFD, |
| 4381 | ARM64_INS_ALIAS_CNTH = AARCH64_INS_ALIAS_CNTH, |
| 4382 | ARM64_INS_ALIAS_CNTW = AARCH64_INS_ALIAS_CNTW, |
| 4383 | ARM64_INS_ALIAS_CNTD = AARCH64_INS_ALIAS_CNTD, |
| 4384 | ARM64_INS_ALIAS_DECB = AARCH64_INS_ALIAS_DECB, |
| 4385 | ARM64_INS_ALIAS_INCH = AARCH64_INS_ALIAS_INCH, |
| 4386 | ARM64_INS_ALIAS_DECH = AARCH64_INS_ALIAS_DECH, |
| 4387 | ARM64_INS_ALIAS_INCW = AARCH64_INS_ALIAS_INCW, |
| 4388 | ARM64_INS_ALIAS_DECW = AARCH64_INS_ALIAS_DECW, |
| 4389 | ARM64_INS_ALIAS_INCD = AARCH64_INS_ALIAS_INCD, |
| 4390 | ARM64_INS_ALIAS_DECD = AARCH64_INS_ALIAS_DECD, |
| 4391 | ARM64_INS_ALIAS_SQDECB = AARCH64_INS_ALIAS_SQDECB, |
| 4392 | ARM64_INS_ALIAS_UQDECB = AARCH64_INS_ALIAS_UQDECB, |
| 4393 | ARM64_INS_ALIAS_UQINCH = AARCH64_INS_ALIAS_UQINCH, |
| 4394 | ARM64_INS_ALIAS_SQDECH = AARCH64_INS_ALIAS_SQDECH, |
| 4395 | ARM64_INS_ALIAS_UQDECH = AARCH64_INS_ALIAS_UQDECH, |
| 4396 | ARM64_INS_ALIAS_SQINCW = AARCH64_INS_ALIAS_SQINCW, |
| 4397 | ARM64_INS_ALIAS_UQINCW = AARCH64_INS_ALIAS_UQINCW, |
| 4398 | ARM64_INS_ALIAS_SQDECW = AARCH64_INS_ALIAS_SQDECW, |
| 4399 | ARM64_INS_ALIAS_UQDECW = AARCH64_INS_ALIAS_UQDECW, |
| 4400 | ARM64_INS_ALIAS_SQINCD = AARCH64_INS_ALIAS_SQINCD, |
| 4401 | ARM64_INS_ALIAS_UQINCD = AARCH64_INS_ALIAS_UQINCD, |
| 4402 | ARM64_INS_ALIAS_SQDECD = AARCH64_INS_ALIAS_SQDECD, |
| 4403 | ARM64_INS_ALIAS_UQDECD = AARCH64_INS_ALIAS_UQDECD, |
| 4404 | ARM64_INS_ALIAS_MOVS = AARCH64_INS_ALIAS_MOVS, |
| 4405 | ARM64_INS_ALIAS_NOT = AARCH64_INS_ALIAS_NOT, |
| 4406 | ARM64_INS_ALIAS_NOTS = AARCH64_INS_ALIAS_NOTS, |
| 4407 | ARM64_INS_ALIAS_LD1ROH = AARCH64_INS_ALIAS_LD1ROH, |
| 4408 | ARM64_INS_ALIAS_LD1ROW = AARCH64_INS_ALIAS_LD1ROW, |
| 4409 | ARM64_INS_ALIAS_LD1ROD = AARCH64_INS_ALIAS_LD1ROD, |
| 4410 | ARM64_INS_ALIAS_BCAX = AARCH64_INS_ALIAS_BCAX, |
| 4411 | ARM64_INS_ALIAS_BSL = AARCH64_INS_ALIAS_BSL, |
| 4412 | ARM64_INS_ALIAS_BSL1N = AARCH64_INS_ALIAS_BSL1N, |
| 4413 | ARM64_INS_ALIAS_BSL2N = AARCH64_INS_ALIAS_BSL2N, |
| 4414 | ARM64_INS_ALIAS_NBSL = AARCH64_INS_ALIAS_NBSL, |
| 4415 | ARM64_INS_ALIAS_LDNT1SH = AARCH64_INS_ALIAS_LDNT1SH, |
| 4416 | ARM64_INS_ALIAS_LDNT1SW = AARCH64_INS_ALIAS_LDNT1SW, |
| 4417 | |
| 4418 | |
| 4419 | ARM64_INS_ALIAS_CFP = AARCH64_INS_ALIAS_CFP, |
| 4420 | ARM64_INS_ALIAS_DVP = AARCH64_INS_ALIAS_DVP, |
| 4421 | ARM64_INS_ALIAS_COSP = AARCH64_INS_ALIAS_COSP, |
| 4422 | ARM64_INS_ALIAS_CPP = AARCH64_INS_ALIAS_CPP, |
| 4423 | ARM64_INS_ALIAS_IC = AARCH64_INS_ALIAS_IC, |
| 4424 | ARM64_INS_ALIAS_DC = AARCH64_INS_ALIAS_DC, |
| 4425 | ARM64_INS_ALIAS_AT = AARCH64_INS_ALIAS_AT, |
| 4426 | ARM64_INS_ALIAS_TLBI = AARCH64_INS_ALIAS_TLBI, |
| 4427 | ARM64_INS_ALIAS_TLBIP = AARCH64_INS_ALIAS_TLBIP, |
| 4428 | ARM64_INS_ALIAS_RPRFM = AARCH64_INS_ALIAS_RPRFM, |
| 4429 | ARM64_INS_ALIAS_LSL = AARCH64_INS_ALIAS_LSL, |
| 4430 | ARM64_INS_ALIAS_SBFX = AARCH64_INS_ALIAS_SBFX, |
| 4431 | ARM64_INS_ALIAS_UBFX = AARCH64_INS_ALIAS_UBFX, |
| 4432 | ARM64_INS_ALIAS_SBFIZ = AARCH64_INS_ALIAS_SBFIZ, |
| 4433 | ARM64_INS_ALIAS_UBFIZ = AARCH64_INS_ALIAS_UBFIZ, |
| 4434 | ARM64_INS_ALIAS_BFC = AARCH64_INS_ALIAS_BFC, |
| 4435 | ARM64_INS_ALIAS_BFI = AARCH64_INS_ALIAS_BFI, |
| 4436 | ARM64_INS_ALIAS_BFXIL = AARCH64_INS_ALIAS_BFXIL, |
| 4437 | |
| 4438 | ARM64_INS_ALIAS_END = AARCH64_INS_ALIAS_END, |
| 4439 | } arm64_insn; |
| 4440 | |
| 4441 | typedef enum { |
| 4442 | ARM64_GRP_INVALID = AARCH64_GRP_INVALID, |
| 4443 | |
| 4444 | ARM64_GRP_JUMP = AARCH64_GRP_JUMP, |
| 4445 | ARM64_GRP_CALL = AARCH64_GRP_CALL, |
| 4446 | ARM64_GRP_RET = AARCH64_GRP_RET, |
| 4447 | ARM64_GRP_INT = AARCH64_GRP_INT, |
| 4448 | ARM64_GRP_PRIVILEGE = AARCH64_GRP_PRIVILEGE, |
| 4449 | ARM64_GRP_BRANCH_RELATIVE = AARCH64_GRP_BRANCH_RELATIVE, |
| 4450 | |
| 4451 | ARM64_FEATURE_HASV8_0A = AARCH64_FEATURE_HASV8_0A, |
| 4452 | ARM64_FEATURE_HASV8_1A = AARCH64_FEATURE_HASV8_1A, |
| 4453 | ARM64_FEATURE_HASV8_2A = AARCH64_FEATURE_HASV8_2A, |
| 4454 | ARM64_FEATURE_HASV8_3A = AARCH64_FEATURE_HASV8_3A, |
| 4455 | ARM64_FEATURE_HASV8_4A = AARCH64_FEATURE_HASV8_4A, |
| 4456 | ARM64_FEATURE_HASV8_5A = AARCH64_FEATURE_HASV8_5A, |
| 4457 | ARM64_FEATURE_HASV8_6A = AARCH64_FEATURE_HASV8_6A, |
| 4458 | ARM64_FEATURE_HASV8_7A = AARCH64_FEATURE_HASV8_7A, |
| 4459 | ARM64_FEATURE_HASV8_8A = AARCH64_FEATURE_HASV8_8A, |
| 4460 | ARM64_FEATURE_HASV8_9A = AARCH64_FEATURE_HASV8_9A, |
| 4461 | ARM64_FEATURE_HASV9_0A = AARCH64_FEATURE_HASV9_0A, |
| 4462 | ARM64_FEATURE_HASV9_1A = AARCH64_FEATURE_HASV9_1A, |
| 4463 | ARM64_FEATURE_HASV9_2A = AARCH64_FEATURE_HASV9_2A, |
| 4464 | ARM64_FEATURE_HASV9_3A = AARCH64_FEATURE_HASV9_3A, |
| 4465 | ARM64_FEATURE_HASV9_4A = AARCH64_FEATURE_HASV9_4A, |
| 4466 | ARM64_FEATURE_HASV8_0R = AARCH64_FEATURE_HASV8_0R, |
| 4467 | ARM64_FEATURE_HASEL2VMSA = AARCH64_FEATURE_HASEL2VMSA, |
| 4468 | ARM64_FEATURE_HASEL3 = AARCH64_FEATURE_HASEL3, |
| 4469 | ARM64_FEATURE_HASVH = AARCH64_FEATURE_HASVH, |
| 4470 | ARM64_FEATURE_HASLOR = AARCH64_FEATURE_HASLOR, |
| 4471 | ARM64_FEATURE_HASPAUTH = AARCH64_FEATURE_HASPAUTH, |
| 4472 | ARM64_FEATURE_HASPAUTHLR = AARCH64_FEATURE_HASPAUTHLR, |
| 4473 | ARM64_FEATURE_HASJS = AARCH64_FEATURE_HASJS, |
| 4474 | ARM64_FEATURE_HASCCIDX = AARCH64_FEATURE_HASCCIDX, |
| 4475 | ARM64_FEATURE_HASCOMPLXNUM = AARCH64_FEATURE_HASCOMPLXNUM, |
| 4476 | ARM64_FEATURE_HASNV = AARCH64_FEATURE_HASNV, |
| 4477 | ARM64_FEATURE_HASMPAM = AARCH64_FEATURE_HASMPAM, |
| 4478 | ARM64_FEATURE_HASDIT = AARCH64_FEATURE_HASDIT, |
| 4479 | ARM64_FEATURE_HASTRACEV8_4 = AARCH64_FEATURE_HASTRACEV8_4, |
| 4480 | ARM64_FEATURE_HASAM = AARCH64_FEATURE_HASAM, |
| 4481 | ARM64_FEATURE_HASSEL2 = AARCH64_FEATURE_HASSEL2, |
| 4482 | ARM64_FEATURE_HASTLB_RMI = AARCH64_FEATURE_HASTLB_RMI, |
| 4483 | ARM64_FEATURE_HASFLAGM = AARCH64_FEATURE_HASFLAGM, |
| 4484 | ARM64_FEATURE_HASRCPC_IMMO = AARCH64_FEATURE_HASRCPC_IMMO, |
| 4485 | ARM64_FEATURE_HASFPARMV8 = AARCH64_FEATURE_HASFPARMV8, |
| 4486 | ARM64_FEATURE_HASNEON = AARCH64_FEATURE_HASNEON, |
| 4487 | ARM64_FEATURE_HASSM4 = AARCH64_FEATURE_HASSM4, |
| 4488 | ARM64_FEATURE_HASSHA3 = AARCH64_FEATURE_HASSHA3, |
| 4489 | ARM64_FEATURE_HASSHA2 = AARCH64_FEATURE_HASSHA2, |
| 4490 | ARM64_FEATURE_HASAES = AARCH64_FEATURE_HASAES, |
| 4491 | ARM64_FEATURE_HASDOTPROD = AARCH64_FEATURE_HASDOTPROD, |
| 4492 | ARM64_FEATURE_HASCRC = AARCH64_FEATURE_HASCRC, |
| 4493 | ARM64_FEATURE_HASCSSC = AARCH64_FEATURE_HASCSSC, |
| 4494 | ARM64_FEATURE_HASLSE = AARCH64_FEATURE_HASLSE, |
| 4495 | ARM64_FEATURE_HASRAS = AARCH64_FEATURE_HASRAS, |
| 4496 | ARM64_FEATURE_HASRDM = AARCH64_FEATURE_HASRDM, |
| 4497 | ARM64_FEATURE_HASFULLFP16 = AARCH64_FEATURE_HASFULLFP16, |
| 4498 | ARM64_FEATURE_HASFP16FML = AARCH64_FEATURE_HASFP16FML, |
| 4499 | ARM64_FEATURE_HASSPE = AARCH64_FEATURE_HASSPE, |
| 4500 | ARM64_FEATURE_HASFUSEAES = AARCH64_FEATURE_HASFUSEAES, |
| 4501 | ARM64_FEATURE_HASSVE = AARCH64_FEATURE_HASSVE, |
| 4502 | ARM64_FEATURE_HASSVE2 = AARCH64_FEATURE_HASSVE2, |
| 4503 | ARM64_FEATURE_HASSVE2P1 = AARCH64_FEATURE_HASSVE2P1, |
| 4504 | ARM64_FEATURE_HASSVE2AES = AARCH64_FEATURE_HASSVE2AES, |
| 4505 | ARM64_FEATURE_HASSVE2SM4 = AARCH64_FEATURE_HASSVE2SM4, |
| 4506 | ARM64_FEATURE_HASSVE2SHA3 = AARCH64_FEATURE_HASSVE2SHA3, |
| 4507 | ARM64_FEATURE_HASSVE2BITPERM = AARCH64_FEATURE_HASSVE2BITPERM, |
| 4508 | ARM64_FEATURE_HASB16B16 = AARCH64_FEATURE_HASB16B16, |
| 4509 | ARM64_FEATURE_HASSME = AARCH64_FEATURE_HASSME, |
| 4510 | ARM64_FEATURE_HASSMEF64F64 = AARCH64_FEATURE_HASSMEF64F64, |
| 4511 | ARM64_FEATURE_HASSMEF16F16 = AARCH64_FEATURE_HASSMEF16F16, |
| 4512 | ARM64_FEATURE_HASSMEFA64 = AARCH64_FEATURE_HASSMEFA64, |
| 4513 | ARM64_FEATURE_HASSMEI16I64 = AARCH64_FEATURE_HASSMEI16I64, |
| 4514 | ARM64_FEATURE_HASSME2 = AARCH64_FEATURE_HASSME2, |
| 4515 | ARM64_FEATURE_HASSME2P1 = AARCH64_FEATURE_HASSME2P1, |
| 4516 | ARM64_FEATURE_HASFPMR = AARCH64_FEATURE_HASFPMR, |
| 4517 | ARM64_FEATURE_HASFP8 = AARCH64_FEATURE_HASFP8, |
| 4518 | ARM64_FEATURE_HASFAMINMAX = AARCH64_FEATURE_HASFAMINMAX, |
| 4519 | ARM64_FEATURE_HASFP8FMA = AARCH64_FEATURE_HASFP8FMA, |
| 4520 | ARM64_FEATURE_HASSSVE_FP8FMA = AARCH64_FEATURE_HASSSVE_FP8FMA, |
| 4521 | ARM64_FEATURE_HASFP8DOT2 = AARCH64_FEATURE_HASFP8DOT2, |
| 4522 | ARM64_FEATURE_HASSSVE_FP8DOT2 = AARCH64_FEATURE_HASSSVE_FP8DOT2, |
| 4523 | ARM64_FEATURE_HASFP8DOT4 = AARCH64_FEATURE_HASFP8DOT4, |
| 4524 | ARM64_FEATURE_HASSSVE_FP8DOT4 = AARCH64_FEATURE_HASSSVE_FP8DOT4, |
| 4525 | ARM64_FEATURE_HASLUT = AARCH64_FEATURE_HASLUT, |
| 4526 | ARM64_FEATURE_HASSME_LUTV2 = AARCH64_FEATURE_HASSME_LUTV2, |
| 4527 | ARM64_FEATURE_HASSMEF8F16 = AARCH64_FEATURE_HASSMEF8F16, |
| 4528 | ARM64_FEATURE_HASSMEF8F32 = AARCH64_FEATURE_HASSMEF8F32, |
| 4529 | ARM64_FEATURE_HASSVEORSME = AARCH64_FEATURE_HASSVEORSME, |
| 4530 | ARM64_FEATURE_HASSVE2ORSME = AARCH64_FEATURE_HASSVE2ORSME, |
| 4531 | ARM64_FEATURE_HASSVE2ORSME2 = AARCH64_FEATURE_HASSVE2ORSME2, |
| 4532 | ARM64_FEATURE_HASSVE2P1_OR_HASSME = AARCH64_FEATURE_HASSVE2P1_OR_HASSME, |
| 4533 | ARM64_FEATURE_HASSVE2P1_OR_HASSME2 = AARCH64_FEATURE_HASSVE2P1_OR_HASSME2, |
| 4534 | ARM64_FEATURE_HASSVE2P1_OR_HASSME2P1 = AARCH64_FEATURE_HASSVE2P1_OR_HASSME2P1, |
| 4535 | ARM64_FEATURE_HASNEONORSME = AARCH64_FEATURE_HASNEONORSME, |
| 4536 | ARM64_FEATURE_HASRCPC = AARCH64_FEATURE_HASRCPC, |
| 4537 | ARM64_FEATURE_HASALTNZCV = AARCH64_FEATURE_HASALTNZCV, |
| 4538 | ARM64_FEATURE_HASFRINT3264 = AARCH64_FEATURE_HASFRINT3264, |
| 4539 | ARM64_FEATURE_HASSB = AARCH64_FEATURE_HASSB, |
| 4540 | ARM64_FEATURE_HASPREDRES = AARCH64_FEATURE_HASPREDRES, |
| 4541 | ARM64_FEATURE_HASCCDP = AARCH64_FEATURE_HASCCDP, |
| 4542 | ARM64_FEATURE_HASBTI = AARCH64_FEATURE_HASBTI, |
| 4543 | ARM64_FEATURE_HASMTE = AARCH64_FEATURE_HASMTE, |
| 4544 | ARM64_FEATURE_HASTME = AARCH64_FEATURE_HASTME, |
| 4545 | ARM64_FEATURE_HASETE = AARCH64_FEATURE_HASETE, |
| 4546 | ARM64_FEATURE_HASTRBE = AARCH64_FEATURE_HASTRBE, |
| 4547 | ARM64_FEATURE_HASBF16 = AARCH64_FEATURE_HASBF16, |
| 4548 | ARM64_FEATURE_HASMATMULINT8 = AARCH64_FEATURE_HASMATMULINT8, |
| 4549 | ARM64_FEATURE_HASMATMULFP32 = AARCH64_FEATURE_HASMATMULFP32, |
| 4550 | ARM64_FEATURE_HASMATMULFP64 = AARCH64_FEATURE_HASMATMULFP64, |
| 4551 | ARM64_FEATURE_HASXS = AARCH64_FEATURE_HASXS, |
| 4552 | ARM64_FEATURE_HASWFXT = AARCH64_FEATURE_HASWFXT, |
| 4553 | ARM64_FEATURE_HASLS64 = AARCH64_FEATURE_HASLS64, |
| 4554 | ARM64_FEATURE_HASBRBE = AARCH64_FEATURE_HASBRBE, |
| 4555 | ARM64_FEATURE_HASSPE_EEF = AARCH64_FEATURE_HASSPE_EEF, |
| 4556 | ARM64_FEATURE_HASHBC = AARCH64_FEATURE_HASHBC, |
| 4557 | ARM64_FEATURE_HASMOPS = AARCH64_FEATURE_HASMOPS, |
| 4558 | ARM64_FEATURE_HASCLRBHB = AARCH64_FEATURE_HASCLRBHB, |
| 4559 | ARM64_FEATURE_HASSPECRES2 = AARCH64_FEATURE_HASSPECRES2, |
| 4560 | ARM64_FEATURE_HASITE = AARCH64_FEATURE_HASITE, |
| 4561 | ARM64_FEATURE_HASTHE = AARCH64_FEATURE_HASTHE, |
| 4562 | ARM64_FEATURE_HASRCPC3 = AARCH64_FEATURE_HASRCPC3, |
| 4563 | ARM64_FEATURE_HASLSE128 = AARCH64_FEATURE_HASLSE128, |
| 4564 | ARM64_FEATURE_HASD128 = AARCH64_FEATURE_HASD128, |
| 4565 | ARM64_FEATURE_HASCHK = AARCH64_FEATURE_HASCHK, |
| 4566 | ARM64_FEATURE_HASGCS = AARCH64_FEATURE_HASGCS, |
| 4567 | ARM64_FEATURE_HASCPA = AARCH64_FEATURE_HASCPA, |
| 4568 | ARM64_FEATURE_USENEGATIVEIMMEDIATES = AARCH64_FEATURE_USENEGATIVEIMMEDIATES, |
| 4569 | ARM64_FEATURE_HASCCPP = AARCH64_FEATURE_HASCCPP, |
| 4570 | ARM64_FEATURE_HASPAN = AARCH64_FEATURE_HASPAN, |
| 4571 | ARM64_FEATURE_HASPSUAO = AARCH64_FEATURE_HASPSUAO, |
| 4572 | ARM64_FEATURE_HASPAN_RWV = AARCH64_FEATURE_HASPAN_RWV, |
| 4573 | ARM64_FEATURE_HASCONTEXTIDREL2 = AARCH64_FEATURE_HASCONTEXTIDREL2, |
| 4574 | |
| 4575 | |
| 4576 | ARM64_GRP_ENDING = AARCH64_GRP_ENDING, |
| 4577 | } arm64_insn_group; |
| 4578 | |
| 4579 | #ifdef __cplusplus |
| 4580 | } |
| 4581 | #endif |
| 4582 | |
| 4583 | #endif |
| 4584 | |
| 4585 | #define arm64_cc AArch64CC_CondCode |
| 4586 | #define ARM64_CC_EQ AArch64CC_EQ |
| 4587 | #define ARM64_CC_NE AArch64CC_NE |
| 4588 | #define ARM64_CC_HS AArch64CC_HS |
| 4589 | #define ARM64_CC_LO AArch64CC_LO |
| 4590 | #define ARM64_CC_MI AArch64CC_MI |
| 4591 | #define ARM64_CC_PL AArch64CC_PL |
| 4592 | #define ARM64_CC_VS AArch64CC_VS |
| 4593 | #define ARM64_CC_VC AArch64CC_VC |
| 4594 | #define ARM64_CC_HI AArch64CC_HI |
| 4595 | #define ARM64_CC_LS AArch64CC_LS |
| 4596 | #define ARM64_CC_GE AArch64CC_GE |
| 4597 | #define ARM64_CC_LT AArch64CC_LT |
| 4598 | #define ARM64_CC_GT AArch64CC_GT |
| 4599 | #define ARM64_CC_LE AArch64CC_LE |
| 4600 | #define ARM64_CC_AL AArch64CC_AL |
| 4601 | #define ARM64_CC_NV AArch64CC_NV |
| 4602 | #define ARM64_CC_INVALID AArch64CC_Invalid |
| 4603 | #define ARM64_VAS_INVALID AARCH64LAYOUT_INVALID |
| 4604 | #define ARM64_VAS_16B AARCH64LAYOUT_VL_16B |
| 4605 | #define ARM64_VAS_8B AARCH64LAYOUT_VL_8B |
| 4606 | #define ARM64_VAS_4B AARCH64LAYOUT_VL_4B |
| 4607 | #define ARM64_VAS_1B AARCH64LAYOUT_VL_1B |
| 4608 | #define ARM64_VAS_8H AARCH64LAYOUT_VL_8H |
| 4609 | #define ARM64_VAS_4H AARCH64LAYOUT_VL_4H |
| 4610 | #define ARM64_VAS_2H AARCH64LAYOUT_VL_2H |
| 4611 | #define ARM64_VAS_1H AARCH64LAYOUT_VL_1H |
| 4612 | #define ARM64_VAS_4S AARCH64LAYOUT_VL_4S |
| 4613 | #define ARM64_VAS_2S AARCH64LAYOUT_VL_2S |
| 4614 | #define ARM64_VAS_1S AARCH64LAYOUT_VL_1S |
| 4615 | #define ARM64_VAS_2D AARCH64LAYOUT_VL_2D |
| 4616 | #define ARM64_VAS_1D AARCH64LAYOUT_VL_1D |
| 4617 | #define ARM64_VAS_1Q AARCH64LAYOUT_VL_1Q |
| 4618 | #define arm64_vas AArch64Layout_VectorLayout |
| 4619 |