Seregon/Hermes

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DyMain/include/capstone/arm.h
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Hermes / DyMain / include / capstone / arm.h
1#ifndef CAPSTONE_ARM_H
2#define CAPSTONE_ARM_H
3 
4/* Capstone Disassembly Engine */
5/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
6/* Rot127 <unisono@quyllur.org>, 2022-2023 */
7 
8#ifdef __cplusplus
9extern "C" {
10#endif
11 
12#include <assert.h>
13#include <string.h>
14 
15#include "cs_operand.h"
16#include "platform.h"
17 
18#ifdef _MSC_VER
19#pragma warning(disable:4201)
20#endif
21 
22// Enums corresponding to ARM condition codes
23// The CondCodes constants map directly to the 4-bit encoding of the
24// condition field for predicated instructions.
25typedef enum CondCodes {
26 // Meaning (integer) Meaning (floating-point)
27 ARMCC_EQ, // Equal Equal
28 ARMCC_NE, // Not equal Not equal, or unordered
29 ARMCC_HS, // Carry set >, ==, or unordered
30 ARMCC_LO, // Carry clear Less than
31 ARMCC_MI, // Minus, negative Less than
32 ARMCC_PL, // Plus, positive or zero >, ==, or unordered
33 ARMCC_VS, // Overflow Unordered
34 ARMCC_VC, // No overflow Not unordered
35 ARMCC_HI, // Unsigned higher Greater than, or unordered
36 ARMCC_LS, // Unsigned lower or same Less than or equal
37 ARMCC_GE, // Greater than or equal Greater than or equal
38 ARMCC_LT, // Less than Less than, or unordered
39 ARMCC_GT, // Greater than Greater than
40 ARMCC_LE, // Less than or equal <, ==, or unordered
41 ARMCC_AL, // Always (unconditional) Always (unconditional)
42 ARMCC_UNDEF = 15, // Undefined
43 ARMCC_Invalid = 16, // Invalid
44} ARMCC_CondCodes;
45 
46inline static ARMCC_CondCodes ARMCC_getOppositeCondition(ARMCC_CondCodes CC)
47{
48 switch (CC) {
49 default:
50 // llvm_unreachable("Unknown condition code");
51 assert(0);
52 case ARMCC_EQ:
53 return ARMCC_NE;
54 case ARMCC_NE:
55 return ARMCC_EQ;
56 case ARMCC_HS:
57 return ARMCC_LO;
58 case ARMCC_LO:
59 return ARMCC_HS;
60 case ARMCC_MI:
61 return ARMCC_PL;
62 case ARMCC_PL:
63 return ARMCC_MI;
64 case ARMCC_VS:
65 return ARMCC_VC;
66 case ARMCC_VC:
67 return ARMCC_VS;
68 case ARMCC_HI:
69 return ARMCC_LS;
70 case ARMCC_LS:
71 return ARMCC_HI;
72 case ARMCC_GE:
73 return ARMCC_LT;
74 case ARMCC_LT:
75 return ARMCC_GE;
76 case ARMCC_GT:
77 return ARMCC_LE;
78 case ARMCC_LE:
79 return ARMCC_GT;
80 }
81}
82 
83/// getSwappedCondition - assume the flags are set by MI(a,b), return
84/// the condition code if we modify the instructions such that flags are
85/// set by MI(b,a).
86inline static ARMCC_CondCodes ARMCC_getSwappedCondition(ARMCC_CondCodes CC)
87{
88 switch (CC) {
89 default:
90 return ARMCC_AL;
91 case ARMCC_EQ:
92 return ARMCC_EQ;
93 case ARMCC_NE:
94 return ARMCC_NE;
95 case ARMCC_HS:
96 return ARMCC_LS;
97 case ARMCC_LO:
98 return ARMCC_HI;
99 case ARMCC_HI:
100 return ARMCC_LO;
101 case ARMCC_LS:
102 return ARMCC_HS;
103 case ARMCC_GE:
104 return ARMCC_LE;
105 case ARMCC_LT:
106 return ARMCC_GT;
107 case ARMCC_GT:
108 return ARMCC_LT;
109 case ARMCC_LE:
110 return ARMCC_GE;
111 }
112}
113 
114typedef enum VPTCodes {
115 ARMVCC_None = 0,
116 ARMVCC_Then,
117 ARMVCC_Else
118} ARMVCC_VPTCodes;
119 
120/// Mask values for IT and VPT Blocks, to be used by MCOperands.
121/// Note that this is different from the "real" encoding used by the
122/// instructions. In this encoding, the lowest set bit indicates the end of
123/// the encoding, and above that, "1" indicates an else, while "0" indicates
124/// a then.
125/// Tx = x100
126/// Txy = xy10
127/// Txyz = xyz1
128typedef enum PredBlockMask {
129 ARM_PredBlockMaskInvalid = 0,
130 ARM_T = 0x8, // 0b1000
131 ARM_TT = 0x4, // 0b0100
132 ARM_TE = 0xc, // 0b1100
133 ARM_TTT = 0x2, // 0b0010
134 ARM_TTE = 0x6, // 0b0110
135 ARM_TEE = 0xe, // 0b1110
136 ARM_TET = 0xa, // 0b1010
137 ARM_TTTT = 0x1, // 0b0001
138 ARM_TTTE = 0x3, // 0b0011
139 ARM_TTEE = 0x7, // 0b0111
140 ARM_TTET = 0x5, // 0b0101
141 ARM_TEEE = 0xf, // 0b1111
142 ARM_TEET = 0xd, // 0b1101
143 ARM_TETT = 0x9, // 0b1001
144 ARM_TETE = 0xb, // 0b1011
145} ARM_PredBlockMask;
146 
147// Expands a PredBlockMask by adding an E or a T at the end, depending on Kind.
148// e.g ExpandPredBlockMask(T, Then) = TT, ExpandPredBlockMask(TT, Else) = TTE,
149// and so on.
150inline static const char *ARMVPTPredToString(ARMVCC_VPTCodes CC)
151{
152 switch (CC) {
153 case ARMVCC_None:
154 return "none";
155 case ARMVCC_Then:
156 return "t";
157 case ARMVCC_Else:
158 return "e";
159 }
160 assert(0 && "Unknown VPT code");
161 return "";
162}
163 
164inline static unsigned ARMVectorCondCodeFromString(const char CC)
165{
166 switch (CC) {
167 default:
168 return ~0U;
169 case 't':
170 return ARMVCC_Then;
171 case 'e':
172 return ARMVCC_Else;
173 }
174}
175 
176inline static const char *ARMCondCodeToString(ARMCC_CondCodes CC)
177{
178 switch (CC) {
179 default:
180 assert(0 && "Unknown condition code");
181 case ARMCC_EQ:
182 return "eq";
183 case ARMCC_NE:
184 return "ne";
185 case ARMCC_HS:
186 return "hs";
187 case ARMCC_LO:
188 return "lo";
189 case ARMCC_MI:
190 return "mi";
191 case ARMCC_PL:
192 return "pl";
193 case ARMCC_VS:
194 return "vs";
195 case ARMCC_VC:
196 return "vc";
197 case ARMCC_HI:
198 return "hi";
199 case ARMCC_LS:
200 return "ls";
201 case ARMCC_GE:
202 return "ge";
203 case ARMCC_LT:
204 return "lt";
205 case ARMCC_GT:
206 return "gt";
207 case ARMCC_LE:
208 return "le";
209 case ARMCC_AL:
210 return "al";
211 }
212}
213 
214inline static unsigned ARMCondCodeFromString(const char *CC)
215{
216 if (strcmp("eq", CC) == 0)
217 return ARMCC_EQ;
218 else if (strcmp("ne", CC) == 0)
219 return ARMCC_NE;
220 else if (strcmp("hs", CC) == 0)
221 return ARMCC_HS;
222 else if (strcmp("cs", CC) == 0)
223 return ARMCC_HS;
224 else if (strcmp("lo", CC) == 0)
225 return ARMCC_LO;
226 else if (strcmp("cc", CC) == 0)
227 return ARMCC_LO;
228 else if (strcmp("mi", CC) == 0)
229 return ARMCC_MI;
230 else if (strcmp("pl", CC) == 0)
231 return ARMCC_PL;
232 else if (strcmp("vs", CC) == 0)
233 return ARMCC_VS;
234 else if (strcmp("vc", CC) == 0)
235 return ARMCC_VC;
236 else if (strcmp("hi", CC) == 0)
237 return ARMCC_HI;
238 else if (strcmp("ls", CC) == 0)
239 return ARMCC_LS;
240 else if (strcmp("ge", CC) == 0)
241 return ARMCC_GE;
242 else if (strcmp("lt", CC) == 0)
243 return ARMCC_LT;
244 else if (strcmp("gt", CC) == 0)
245 return ARMCC_GT;
246 else if (strcmp("le", CC) == 0)
247 return ARMCC_LE;
248 else if (strcmp("al", CC) == 0)
249 return ARMCC_AL;
250 return (~0U);
251}
252 
253/// ARM shift type
254typedef enum arm_shifter {
255 ARM_SFT_INVALID = 0,
256 ARM_SFT_ASR,
257 ARM_SFT_LSL,
258 ARM_SFT_LSR,
259 ARM_SFT_ROR,
260 ARM_SFT_RRX,
261 ARM_SFT_UXTW,
262 
263 // Added by Capstone to signal that the shift amount is stored in a register.
264 // shift.val should be interpreted as register id.
265 ARM_SFT_REG,
266 ARM_SFT_ASR_REG,
267 ARM_SFT_LSL_REG,
268 ARM_SFT_LSR_REG,
269 ARM_SFT_ROR_REG,
270 // Others are not defined in the ISA.
271} arm_shifter;
272 
273/// The memory barrier constants map directly to the 4-bit encoding of
274/// the option field for Memory Barrier operations.
275typedef enum MemBOpt {
276 ARM_MB_RESERVED_0,
277 ARM_MB_OSHLD,
278 ARM_MB_OSHST,
279 ARM_MB_OSH,
280 ARM_MB_RESERVED_4,
281 ARM_MB_NSHLD,
282 ARM_MB_NSHST,
283 ARM_MB_NSH,
284 ARM_MB_RESERVED_8,
285 ARM_MB_ISHLD,
286 ARM_MB_ISHST,
287 ARM_MB_ISH,
288 ARM_MB_RESERVED_12,
289 ARM_MB_LD,
290 ARM_MB_ST,
291 ARM_MB_SY,
292} arm_mem_bo_opt;
293 
294typedef enum {
295 // SPSR* field flags can be OR combined
296 ARM_FIELD_SPSR_C = 1,
297 ARM_FIELD_SPSR_X = 2,
298 ARM_FIELD_SPSR_S = 4,
299 ARM_FIELD_SPSR_F = 8,
300 
301 // CPSR* field flags can be OR combined
302 ARM_FIELD_CPSR_C = 16,
303 ARM_FIELD_CPSR_X = 32,
304 ARM_FIELD_CPSR_S = 64,
305 ARM_FIELD_CPSR_F = 128,
306} arm_spsr_cspr_bits;
307 
308// From LLVM docs:
309// The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM field
310// and bit 5 is R.
311typedef enum {
312 // generated content <ARMGenCSSystemOperandsEnum.inc:GET_ENUM_VALUES_BankedReg> begin
313 // clang-format off
314 
315 ARM_BANKEDREG_ELR_HYP = 0x1e,
316 ARM_BANKEDREG_LR_ABT = 0x14,
317 ARM_BANKEDREG_LR_FIQ = 0xe,
318 ARM_BANKEDREG_LR_IRQ = 0x10,
319 ARM_BANKEDREG_LR_MON = 0x1c,
320 ARM_BANKEDREG_LR_SVC = 0x12,
321 ARM_BANKEDREG_LR_UND = 0x16,
322 ARM_BANKEDREG_LR_USR = 0x6,
323 ARM_BANKEDREG_R10_FIQ = 0xa,
324 ARM_BANKEDREG_R10_USR = 0x2,
325 ARM_BANKEDREG_R11_FIQ = 0xb,
326 ARM_BANKEDREG_R11_USR = 0x3,
327 ARM_BANKEDREG_R12_FIQ = 0xc,
328 ARM_BANKEDREG_R12_USR = 0x4,
329 ARM_BANKEDREG_R8_FIQ = 0x8,
330 ARM_BANKEDREG_R8_USR = 0x0,
331 ARM_BANKEDREG_R9_FIQ = 0x9,
332 ARM_BANKEDREG_R9_USR = 0x1,
333 ARM_BANKEDREG_SPSR_ABT = 0x34,
334 ARM_BANKEDREG_SPSR_FIQ = 0x2e,
335 ARM_BANKEDREG_SPSR_HYP = 0x3e,
336 ARM_BANKEDREG_SPSR_IRQ = 0x30,
337 ARM_BANKEDREG_SPSR_MON = 0x3c,
338 ARM_BANKEDREG_SPSR_SVC = 0x32,
339 ARM_BANKEDREG_SPSR_UND = 0x36,
340 ARM_BANKEDREG_SP_ABT = 0x15,
341 ARM_BANKEDREG_SP_FIQ = 0xd,
342 ARM_BANKEDREG_SP_HYP = 0x1f,
343 ARM_BANKEDREG_SP_IRQ = 0x11,
344 ARM_BANKEDREG_SP_MON = 0x1d,
345 ARM_BANKEDREG_SP_SVC = 0x13,
346 ARM_BANKEDREG_SP_UND = 0x17,
347 ARM_BANKEDREG_SP_USR = 0x5,
348 
349 // clang-format on
350 // generated content <ARMGenCSSystemOperandsEnum.inc:GET_ENUM_VALUES_BankedReg> end
351} arm_bankedreg;
352 
353typedef enum {
354 // generated content <ARMGenCSSystemOperandsEnum.inc:GET_ENUM_VALUES_MClassSysReg> begin
355 // clang-format off
356 
357 ARM_MCLASSSYSREG_APSR = 0x800,
358 ARM_MCLASSSYSREG_APSR_G = 0x400,
359 ARM_MCLASSSYSREG_APSR_NZCVQ = 0x800,
360 ARM_MCLASSSYSREG_APSR_NZCVQG = 0xc00,
361 ARM_MCLASSSYSREG_BASEPRI = 0x811,
362 ARM_MCLASSSYSREG_BASEPRI_MAX = 0x812,
363 ARM_MCLASSSYSREG_BASEPRI_NS = 0x891,
364 ARM_MCLASSSYSREG_CONTROL = 0x814,
365 ARM_MCLASSSYSREG_CONTROL_NS = 0x894,
366 ARM_MCLASSSYSREG_EAPSR = 0x802,
367 ARM_MCLASSSYSREG_EAPSR_G = 0x402,
368 ARM_MCLASSSYSREG_EAPSR_NZCVQ = 0x802,
369 ARM_MCLASSSYSREG_EAPSR_NZCVQG = 0xc02,
370 ARM_MCLASSSYSREG_EPSR = 0x806,
371 ARM_MCLASSSYSREG_FAULTMASK = 0x813,
372 ARM_MCLASSSYSREG_FAULTMASK_NS = 0x893,
373 ARM_MCLASSSYSREG_IAPSR = 0x801,
374 ARM_MCLASSSYSREG_IAPSR_G = 0x401,
375 ARM_MCLASSSYSREG_IAPSR_NZCVQ = 0x801,
376 ARM_MCLASSSYSREG_IAPSR_NZCVQG = 0xc01,
377 ARM_MCLASSSYSREG_IEPSR = 0x807,
378 ARM_MCLASSSYSREG_IPSR = 0x805,
379 ARM_MCLASSSYSREG_MSP = 0x808,
380 ARM_MCLASSSYSREG_MSPLIM = 0x80a,
381 ARM_MCLASSSYSREG_MSPLIM_NS = 0x88a,
382 ARM_MCLASSSYSREG_MSP_NS = 0x888,
383 ARM_MCLASSSYSREG_PAC_KEY_P_0 = 0x820,
384 ARM_MCLASSSYSREG_PAC_KEY_P_0_NS = 0x8a0,
385 ARM_MCLASSSYSREG_PAC_KEY_P_1 = 0x821,
386 ARM_MCLASSSYSREG_PAC_KEY_P_1_NS = 0x8a1,
387 ARM_MCLASSSYSREG_PAC_KEY_P_2 = 0x822,
388 ARM_MCLASSSYSREG_PAC_KEY_P_2_NS = 0x8a2,
389 ARM_MCLASSSYSREG_PAC_KEY_P_3 = 0x823,
390 ARM_MCLASSSYSREG_PAC_KEY_P_3_NS = 0x8a3,
391 ARM_MCLASSSYSREG_PAC_KEY_U_0 = 0x824,
392 ARM_MCLASSSYSREG_PAC_KEY_U_0_NS = 0x8a4,
393 ARM_MCLASSSYSREG_PAC_KEY_U_1 = 0x825,
394 ARM_MCLASSSYSREG_PAC_KEY_U_1_NS = 0x8a5,
395 ARM_MCLASSSYSREG_PAC_KEY_U_2 = 0x826,
396 ARM_MCLASSSYSREG_PAC_KEY_U_2_NS = 0x8a6,
397 ARM_MCLASSSYSREG_PAC_KEY_U_3 = 0x827,
398 ARM_MCLASSSYSREG_PAC_KEY_U_3_NS = 0x8a7,
399 ARM_MCLASSSYSREG_PRIMASK = 0x810,
400 ARM_MCLASSSYSREG_PRIMASK_NS = 0x890,
401 ARM_MCLASSSYSREG_PSP = 0x809,
402 ARM_MCLASSSYSREG_PSPLIM = 0x80b,
403 ARM_MCLASSSYSREG_PSPLIM_NS = 0x88b,
404 ARM_MCLASSSYSREG_PSP_NS = 0x889,
405 ARM_MCLASSSYSREG_SP_NS = 0x898,
406 ARM_MCLASSSYSREG_XPSR = 0x803,
407 ARM_MCLASSSYSREG_XPSR_G = 0x403,
408 ARM_MCLASSSYSREG_XPSR_NZCVQ = 0x803,
409 ARM_MCLASSSYSREG_XPSR_NZCVQG = 0xc03,
410 
411 // clang-format on
412 // generated content <ARMGenCSSystemOperandsEnum.inc:GET_ENUM_VALUES_MClassSysReg> end
413} arm_sysreg;
414 
415typedef union {
416 arm_sysreg mclasssysreg;
417 arm_bankedreg bankedreg;
418 int raw_val; ///< Raw value for assignment in generated files.
419} arm_sysop_reg;
420 
421/// Operand type for instruction's operands
422typedef enum arm_op_type {
423 ARM_OP_INVALID = CS_OP_INVALID, ///< Invalid
424 ARM_OP_REG = CS_OP_REG, ///< Register operand
425 ARM_OP_IMM = CS_OP_IMM, ///< Immediate operand
426 ARM_OP_FP = CS_OP_FP, ///< Floating-Point operand
427 ARM_OP_PRED = CS_OP_PRED, ///< Predicate
428 ARM_OP_CIMM = CS_OP_SPECIAL + 0, ///< C-Immediate (coprocessor registers)
429 ARM_OP_PIMM = CS_OP_SPECIAL + 1, ///< P-Immediate (coprocessor registers)
430 ARM_OP_SETEND = CS_OP_SPECIAL + 2, ///< operand for SETEND instruction
431 ARM_OP_SYSREG = CS_OP_SPECIAL + 3, ///< MSR/MRS special register operand
432 ARM_OP_BANKEDREG = CS_OP_SPECIAL + 4, ///< Banked register operand
433 ARM_OP_SPSR = CS_OP_SPECIAL + 5, ///< Collection of SPSR bits
434 ARM_OP_CPSR = CS_OP_SPECIAL + 6, ///< Collection of CPSR bits
435 ARM_OP_SYSM = CS_OP_SPECIAL + 7, ///< Raw SYSm field
436 ARM_OP_VPRED_R = CS_OP_SPECIAL + 8, ///< Vector predicate. Leaves inactive lanes of output vector register unchanged.
437 ARM_OP_VPRED_N = CS_OP_SPECIAL + 9, ///< Vector predicate. Don't preserved inactive lanes of output register.
438 ARM_OP_MEM = CS_OP_MEM, ///< Memory operand
439} arm_op_type;
440 
441/// Operand type for SETEND instruction
442typedef enum arm_setend_type {
443 ARM_SETEND_INVALID = 0, ///< Uninitialized.
444 ARM_SETEND_BE, ///< BE operand.
445 ARM_SETEND_LE, ///< LE operand
446} arm_setend_type;
447 
448typedef enum arm_cpsmode_type {
449 ARM_CPSMODE_INVALID = 0,
450 ARM_CPSMODE_IE = 2,
451 ARM_CPSMODE_ID = 3
452} arm_cpsmode_type;
453 
454/// Operand type for SETEND instruction
455typedef enum arm_cpsflag_type {
456 ARM_CPSFLAG_INVALID = 0,
457 ARM_CPSFLAG_F = 1,
458 ARM_CPSFLAG_I = 2,
459 ARM_CPSFLAG_A = 4,
460 ARM_CPSFLAG_NONE = 16, ///< no flag
461} arm_cpsflag_type;
462 
463/// Data type for elements of vector instructions.
464typedef enum arm_vectordata_type {
465 ARM_VECTORDATA_INVALID = 0,
466 
467 // Integer type
468 ARM_VECTORDATA_I8,
469 ARM_VECTORDATA_I16,
470 ARM_VECTORDATA_I32,
471 ARM_VECTORDATA_I64,
472 
473 // Signed integer type
474 ARM_VECTORDATA_S8,
475 ARM_VECTORDATA_S16,
476 ARM_VECTORDATA_S32,
477 ARM_VECTORDATA_S64,
478 
479 // Unsigned integer type
480 ARM_VECTORDATA_U8,
481 ARM_VECTORDATA_U16,
482 ARM_VECTORDATA_U32,
483 ARM_VECTORDATA_U64,
484 
485 // Data type for VMUL/VMULL
486 ARM_VECTORDATA_P8,
487 ARM_VECTORDATA_P16,
488 
489 // Floating type
490 ARM_VECTORDATA_F16,
491 ARM_VECTORDATA_F32,
492 ARM_VECTORDATA_F64,
493 
494 // Convert float <-> float
495 ARM_VECTORDATA_F16F64, // f16.f64
496 ARM_VECTORDATA_F64F16, // f64.f16
497 ARM_VECTORDATA_F32F16, // f32.f16
498 ARM_VECTORDATA_F16F32, // f32.f16
499 ARM_VECTORDATA_F64F32, // f64.f32
500 ARM_VECTORDATA_F32F64, // f32.f64
501 
502 // Convert integer <-> float
503 ARM_VECTORDATA_S32F32, // s32.f32
504 ARM_VECTORDATA_U32F32, // u32.f32
505 ARM_VECTORDATA_F32S32, // f32.s32
506 ARM_VECTORDATA_F32U32, // f32.u32
507 ARM_VECTORDATA_F64S16, // f64.s16
508 ARM_VECTORDATA_F32S16, // f32.s16
509 ARM_VECTORDATA_F64S32, // f64.s32
510 ARM_VECTORDATA_S16F64, // s16.f64
511 ARM_VECTORDATA_S16F32, // s16.f64
512 ARM_VECTORDATA_S32F64, // s32.f64
513 ARM_VECTORDATA_U16F64, // u16.f64
514 ARM_VECTORDATA_U16F32, // u16.f32
515 ARM_VECTORDATA_U32F64, // u32.f64
516 ARM_VECTORDATA_F64U16, // f64.u16
517 ARM_VECTORDATA_F32U16, // f32.u16
518 ARM_VECTORDATA_F64U32, // f64.u32
519 ARM_VECTORDATA_F16U16, // f16.u16
520 ARM_VECTORDATA_U16F16, // u16.f16
521 ARM_VECTORDATA_F16U32, // f16.u32
522 ARM_VECTORDATA_U32F16, // u32.f16
523 ARM_VECTORDATA_F16S16,
524 ARM_VECTORDATA_S16F16,
525 ARM_VECTORDATA_F16S32,
526 ARM_VECTORDATA_S32F16,
527} arm_vectordata_type;
528 
529/// ARM registers
530typedef enum arm_reg {
531 // generated content <ARMGenCSRegEnum.inc> begin
532 // clang-format off
533 
534 ARM_REG_INVALID = 0,
535 ARM_REG_APSR = 1,
536 ARM_REG_APSR_NZCV = 2,
537 ARM_REG_CPSR = 3,
538 ARM_REG_FPCXTNS = 4,
539 ARM_REG_FPCXTS = 5,
540 ARM_REG_FPEXC = 6,
541 ARM_REG_FPINST = 7,
542 ARM_REG_FPSCR = 8,
543 ARM_REG_FPSCR_NZCV = 9,
544 ARM_REG_FPSCR_NZCVQC = 10,
545 ARM_REG_FPSID = 11,
546 ARM_REG_ITSTATE = 12,
547 ARM_REG_LR = 13,
548 ARM_REG_PC = 14,
549 ARM_REG_RA_AUTH_CODE = 15,
550 ARM_REG_SP = 16,
551 ARM_REG_SPSR = 17,
552 ARM_REG_VPR = 18,
553 ARM_REG_ZR = 19,
554 ARM_REG_D0 = 20,
555 ARM_REG_D1 = 21,
556 ARM_REG_D2 = 22,
557 ARM_REG_D3 = 23,
558 ARM_REG_D4 = 24,
559 ARM_REG_D5 = 25,
560 ARM_REG_D6 = 26,
561 ARM_REG_D7 = 27,
562 ARM_REG_D8 = 28,
563 ARM_REG_D9 = 29,
564 ARM_REG_D10 = 30,
565 ARM_REG_D11 = 31,
566 ARM_REG_D12 = 32,
567 ARM_REG_D13 = 33,
568 ARM_REG_D14 = 34,
569 ARM_REG_D15 = 35,
570 ARM_REG_D16 = 36,
571 ARM_REG_D17 = 37,
572 ARM_REG_D18 = 38,
573 ARM_REG_D19 = 39,
574 ARM_REG_D20 = 40,
575 ARM_REG_D21 = 41,
576 ARM_REG_D22 = 42,
577 ARM_REG_D23 = 43,
578 ARM_REG_D24 = 44,
579 ARM_REG_D25 = 45,
580 ARM_REG_D26 = 46,
581 ARM_REG_D27 = 47,
582 ARM_REG_D28 = 48,
583 ARM_REG_D29 = 49,
584 ARM_REG_D30 = 50,
585 ARM_REG_D31 = 51,
586 ARM_REG_FPINST2 = 52,
587 ARM_REG_MVFR0 = 53,
588 ARM_REG_MVFR1 = 54,
589 ARM_REG_MVFR2 = 55,
590 ARM_REG_P0 = 56,
591 ARM_REG_Q0 = 57,
592 ARM_REG_Q1 = 58,
593 ARM_REG_Q2 = 59,
594 ARM_REG_Q3 = 60,
595 ARM_REG_Q4 = 61,
596 ARM_REG_Q5 = 62,
597 ARM_REG_Q6 = 63,
598 ARM_REG_Q7 = 64,
599 ARM_REG_Q8 = 65,
600 ARM_REG_Q9 = 66,
601 ARM_REG_Q10 = 67,
602 ARM_REG_Q11 = 68,
603 ARM_REG_Q12 = 69,
604 ARM_REG_Q13 = 70,
605 ARM_REG_Q14 = 71,
606 ARM_REG_Q15 = 72,
607 ARM_REG_R0 = 73,
608 ARM_REG_R1 = 74,
609 ARM_REG_R2 = 75,
610 ARM_REG_R3 = 76,
611 ARM_REG_R4 = 77,
612 ARM_REG_R5 = 78,
613 ARM_REG_R6 = 79,
614 ARM_REG_R7 = 80,
615 ARM_REG_R8 = 81,
616 ARM_REG_R9 = 82,
617 ARM_REG_R10 = 83,
618 ARM_REG_R11 = 84,
619 ARM_REG_R12 = 85,
620 ARM_REG_S0 = 86,
621 ARM_REG_S1 = 87,
622 ARM_REG_S2 = 88,
623 ARM_REG_S3 = 89,
624 ARM_REG_S4 = 90,
625 ARM_REG_S5 = 91,
626 ARM_REG_S6 = 92,
627 ARM_REG_S7 = 93,
628 ARM_REG_S8 = 94,
629 ARM_REG_S9 = 95,
630 ARM_REG_S10 = 96,
631 ARM_REG_S11 = 97,
632 ARM_REG_S12 = 98,
633 ARM_REG_S13 = 99,
634 ARM_REG_S14 = 100,
635 ARM_REG_S15 = 101,
636 ARM_REG_S16 = 102,
637 ARM_REG_S17 = 103,
638 ARM_REG_S18 = 104,
639 ARM_REG_S19 = 105,
640 ARM_REG_S20 = 106,
641 ARM_REG_S21 = 107,
642 ARM_REG_S22 = 108,
643 ARM_REG_S23 = 109,
644 ARM_REG_S24 = 110,
645 ARM_REG_S25 = 111,
646 ARM_REG_S26 = 112,
647 ARM_REG_S27 = 113,
648 ARM_REG_S28 = 114,
649 ARM_REG_S29 = 115,
650 ARM_REG_S30 = 116,
651 ARM_REG_S31 = 117,
652 ARM_REG_D0_D2 = 118,
653 ARM_REG_D1_D3 = 119,
654 ARM_REG_D2_D4 = 120,
655 ARM_REG_D3_D5 = 121,
656 ARM_REG_D4_D6 = 122,
657 ARM_REG_D5_D7 = 123,
658 ARM_REG_D6_D8 = 124,
659 ARM_REG_D7_D9 = 125,
660 ARM_REG_D8_D10 = 126,
661 ARM_REG_D9_D11 = 127,
662 ARM_REG_D10_D12 = 128,
663 ARM_REG_D11_D13 = 129,
664 ARM_REG_D12_D14 = 130,
665 ARM_REG_D13_D15 = 131,
666 ARM_REG_D14_D16 = 132,
667 ARM_REG_D15_D17 = 133,
668 ARM_REG_D16_D18 = 134,
669 ARM_REG_D17_D19 = 135,
670 ARM_REG_D18_D20 = 136,
671 ARM_REG_D19_D21 = 137,
672 ARM_REG_D20_D22 = 138,
673 ARM_REG_D21_D23 = 139,
674 ARM_REG_D22_D24 = 140,
675 ARM_REG_D23_D25 = 141,
676 ARM_REG_D24_D26 = 142,
677 ARM_REG_D25_D27 = 143,
678 ARM_REG_D26_D28 = 144,
679 ARM_REG_D27_D29 = 145,
680 ARM_REG_D28_D30 = 146,
681 ARM_REG_D29_D31 = 147,
682 ARM_REG_Q0_Q1 = 148,
683 ARM_REG_Q1_Q2 = 149,
684 ARM_REG_Q2_Q3 = 150,
685 ARM_REG_Q3_Q4 = 151,
686 ARM_REG_Q4_Q5 = 152,
687 ARM_REG_Q5_Q6 = 153,
688 ARM_REG_Q6_Q7 = 154,
689 ARM_REG_Q7_Q8 = 155,
690 ARM_REG_Q8_Q9 = 156,
691 ARM_REG_Q9_Q10 = 157,
692 ARM_REG_Q10_Q11 = 158,
693 ARM_REG_Q11_Q12 = 159,
694 ARM_REG_Q12_Q13 = 160,
695 ARM_REG_Q13_Q14 = 161,
696 ARM_REG_Q14_Q15 = 162,
697 ARM_REG_Q0_Q1_Q2_Q3 = 163,
698 ARM_REG_Q1_Q2_Q3_Q4 = 164,
699 ARM_REG_Q2_Q3_Q4_Q5 = 165,
700 ARM_REG_Q3_Q4_Q5_Q6 = 166,
701 ARM_REG_Q4_Q5_Q6_Q7 = 167,
702 ARM_REG_Q5_Q6_Q7_Q8 = 168,
703 ARM_REG_Q6_Q7_Q8_Q9 = 169,
704 ARM_REG_Q7_Q8_Q9_Q10 = 170,
705 ARM_REG_Q8_Q9_Q10_Q11 = 171,
706 ARM_REG_Q9_Q10_Q11_Q12 = 172,
707 ARM_REG_Q10_Q11_Q12_Q13 = 173,
708 ARM_REG_Q11_Q12_Q13_Q14 = 174,
709 ARM_REG_Q12_Q13_Q14_Q15 = 175,
710 ARM_REG_R0_R1 = 176,
711 ARM_REG_R2_R3 = 177,
712 ARM_REG_R4_R5 = 178,
713 ARM_REG_R6_R7 = 179,
714 ARM_REG_R8_R9 = 180,
715 ARM_REG_R10_R11 = 181,
716 ARM_REG_R12_SP = 182,
717 ARM_REG_D0_D1_D2 = 183,
718 ARM_REG_D1_D2_D3 = 184,
719 ARM_REG_D2_D3_D4 = 185,
720 ARM_REG_D3_D4_D5 = 186,
721 ARM_REG_D4_D5_D6 = 187,
722 ARM_REG_D5_D6_D7 = 188,
723 ARM_REG_D6_D7_D8 = 189,
724 ARM_REG_D7_D8_D9 = 190,
725 ARM_REG_D8_D9_D10 = 191,
726 ARM_REG_D9_D10_D11 = 192,
727 ARM_REG_D10_D11_D12 = 193,
728 ARM_REG_D11_D12_D13 = 194,
729 ARM_REG_D12_D13_D14 = 195,
730 ARM_REG_D13_D14_D15 = 196,
731 ARM_REG_D14_D15_D16 = 197,
732 ARM_REG_D15_D16_D17 = 198,
733 ARM_REG_D16_D17_D18 = 199,
734 ARM_REG_D17_D18_D19 = 200,
735 ARM_REG_D18_D19_D20 = 201,
736 ARM_REG_D19_D20_D21 = 202,
737 ARM_REG_D20_D21_D22 = 203,
738 ARM_REG_D21_D22_D23 = 204,
739 ARM_REG_D22_D23_D24 = 205,
740 ARM_REG_D23_D24_D25 = 206,
741 ARM_REG_D24_D25_D26 = 207,
742 ARM_REG_D25_D26_D27 = 208,
743 ARM_REG_D26_D27_D28 = 209,
744 ARM_REG_D27_D28_D29 = 210,
745 ARM_REG_D28_D29_D30 = 211,
746 ARM_REG_D29_D30_D31 = 212,
747 ARM_REG_D0_D2_D4 = 213,
748 ARM_REG_D1_D3_D5 = 214,
749 ARM_REG_D2_D4_D6 = 215,
750 ARM_REG_D3_D5_D7 = 216,
751 ARM_REG_D4_D6_D8 = 217,
752 ARM_REG_D5_D7_D9 = 218,
753 ARM_REG_D6_D8_D10 = 219,
754 ARM_REG_D7_D9_D11 = 220,
755 ARM_REG_D8_D10_D12 = 221,
756 ARM_REG_D9_D11_D13 = 222,
757 ARM_REG_D10_D12_D14 = 223,
758 ARM_REG_D11_D13_D15 = 224,
759 ARM_REG_D12_D14_D16 = 225,
760 ARM_REG_D13_D15_D17 = 226,
761 ARM_REG_D14_D16_D18 = 227,
762 ARM_REG_D15_D17_D19 = 228,
763 ARM_REG_D16_D18_D20 = 229,
764 ARM_REG_D17_D19_D21 = 230,
765 ARM_REG_D18_D20_D22 = 231,
766 ARM_REG_D19_D21_D23 = 232,
767 ARM_REG_D20_D22_D24 = 233,
768 ARM_REG_D21_D23_D25 = 234,
769 ARM_REG_D22_D24_D26 = 235,
770 ARM_REG_D23_D25_D27 = 236,
771 ARM_REG_D24_D26_D28 = 237,
772 ARM_REG_D25_D27_D29 = 238,
773 ARM_REG_D26_D28_D30 = 239,
774 ARM_REG_D27_D29_D31 = 240,
775 ARM_REG_D0_D2_D4_D6 = 241,
776 ARM_REG_D1_D3_D5_D7 = 242,
777 ARM_REG_D2_D4_D6_D8 = 243,
778 ARM_REG_D3_D5_D7_D9 = 244,
779 ARM_REG_D4_D6_D8_D10 = 245,
780 ARM_REG_D5_D7_D9_D11 = 246,
781 ARM_REG_D6_D8_D10_D12 = 247,
782 ARM_REG_D7_D9_D11_D13 = 248,
783 ARM_REG_D8_D10_D12_D14 = 249,
784 ARM_REG_D9_D11_D13_D15 = 250,
785 ARM_REG_D10_D12_D14_D16 = 251,
786 ARM_REG_D11_D13_D15_D17 = 252,
787 ARM_REG_D12_D14_D16_D18 = 253,
788 ARM_REG_D13_D15_D17_D19 = 254,
789 ARM_REG_D14_D16_D18_D20 = 255,
790 ARM_REG_D15_D17_D19_D21 = 256,
791 ARM_REG_D16_D18_D20_D22 = 257,
792 ARM_REG_D17_D19_D21_D23 = 258,
793 ARM_REG_D18_D20_D22_D24 = 259,
794 ARM_REG_D19_D21_D23_D25 = 260,
795 ARM_REG_D20_D22_D24_D26 = 261,
796 ARM_REG_D21_D23_D25_D27 = 262,
797 ARM_REG_D22_D24_D26_D28 = 263,
798 ARM_REG_D23_D25_D27_D29 = 264,
799 ARM_REG_D24_D26_D28_D30 = 265,
800 ARM_REG_D25_D27_D29_D31 = 266,
801 ARM_REG_D1_D2 = 267,
802 ARM_REG_D3_D4 = 268,
803 ARM_REG_D5_D6 = 269,
804 ARM_REG_D7_D8 = 270,
805 ARM_REG_D9_D10 = 271,
806 ARM_REG_D11_D12 = 272,
807 ARM_REG_D13_D14 = 273,
808 ARM_REG_D15_D16 = 274,
809 ARM_REG_D17_D18 = 275,
810 ARM_REG_D19_D20 = 276,
811 ARM_REG_D21_D22 = 277,
812 ARM_REG_D23_D24 = 278,
813 ARM_REG_D25_D26 = 279,
814 ARM_REG_D27_D28 = 280,
815 ARM_REG_D29_D30 = 281,
816 ARM_REG_D1_D2_D3_D4 = 282,
817 ARM_REG_D3_D4_D5_D6 = 283,
818 ARM_REG_D5_D6_D7_D8 = 284,
819 ARM_REG_D7_D8_D9_D10 = 285,
820 ARM_REG_D9_D10_D11_D12 = 286,
821 ARM_REG_D11_D12_D13_D14 = 287,
822 ARM_REG_D13_D14_D15_D16 = 288,
823 ARM_REG_D15_D16_D17_D18 = 289,
824 ARM_REG_D17_D18_D19_D20 = 290,
825 ARM_REG_D19_D20_D21_D22 = 291,
826 ARM_REG_D21_D22_D23_D24 = 292,
827 ARM_REG_D23_D24_D25_D26 = 293,
828 ARM_REG_D25_D26_D27_D28 = 294,
829 ARM_REG_D27_D28_D29_D30 = 295,
830 ARM_REG_ENDING, // 296
831 
832 // clang-format on
833 // generated content <ARMGenCSRegEnum.inc> end
834 
835 // alias registers
836 ARM_REG_R13 = ARM_REG_SP,
837 ARM_REG_R14 = ARM_REG_LR,
838 ARM_REG_R15 = ARM_REG_PC,
839 
840 ARM_REG_SB = ARM_REG_R9,
841 ARM_REG_SL = ARM_REG_R10,
842 ARM_REG_FP = ARM_REG_R11,
843 ARM_REG_IP = ARM_REG_R12,
844} arm_reg;
845 
846/// Instruction's operand referring to memory
847/// This is associated with ARM_OP_MEM operand type above
848typedef struct arm_op_mem {
849 arm_reg base; ///< base register
850 arm_reg index; ///< index register
851 int scale; ///< scale for index register. Can be 1 if index reg is added, -1 if it is subtracted or 0 if unset.
852 int disp; ///< displacement/offset value
853 unsigned align; ///< Alignment of base register. 0 If not set.
854} arm_op_mem;
855 
856typedef struct {
857 arm_sysop_reg reg; ///< The system or banked register.
858 arm_spsr_cspr_bits psr_bits; ///< SPSR/CPSR bits.
859 uint16_t sysm; ///< Raw SYSm field. UINT16_MAX if unset.
860 uint8_t msr_mask; ///< Mask of MSR instructions. UINT8_MAX if invalid.
861} arm_sysop;
862 
863/// Instruction operand
864typedef struct cs_arm_op {
865 int vector_index; ///< Vector Index for some vector operands (or -1 if irrelevant)
866 
867 struct {
868 arm_shifter type; ///< The shift type
869 unsigned int value; ///< The amount to shift. If shift.type > ARM_SFT_REG, the value must be interpreted as register id.
870 } shift;
871 
872 arm_op_type type; ///< operand type
873 
874 union {
875 int reg; ///< register value for REG
876 arm_sysop sysop; ///< System operand.
877 int64_t imm; ///< immediate value for C-IMM, P-IMM or IMM operand
878 int pred; ///< Predicate operand value.
879 double fp; ///< floating point value for FP operand
880 arm_op_mem mem; ///< base/index/scale/disp value for MEM operand
881 arm_setend_type setend; ///< SETEND instruction's operand type
882 };
883 
884 /// in some instructions, an operand can be subtracted or added to
885 /// the base register,
886 /// if TRUE, this operand is subtracted. otherwise, it is added.
887 bool subtracted;
888 
889 /// How is this operand accessed? (READ, WRITE or READ|WRITE)
890 /// This field is combined of cs_ac_type.
891 /// NOTE: this field is irrelevant if engine is compiled in DIET mode.
892 uint8_t access;
893 
894 /// Neon lane index for NEON instructions (or -1 if irrelevant)
895 int8_t neon_lane;
896} cs_arm_op;
897 
898typedef struct {
899 cs_ac_type mem_acc; ///< CGI memory access according to mayLoad and mayStore
900} arm_suppl_info;
901 
902#define NUM_ARM_OPS 36
903 
904/// Instruction structure
905typedef struct cs_arm {
906 bool usermode; ///< User-mode registers to be loaded (for LDM/STM instructions)
907 int vector_size; ///< Scalar size for vector instructions
908 arm_vectordata_type vector_data; ///< Data type for elements of vector instructions
909 arm_cpsmode_type cps_mode; ///< CPS mode for CPS instruction
910 arm_cpsflag_type cps_flag; ///< CPS mode for CPS instruction
911 ARMCC_CondCodes cc; ///< conditional code for this insn
912 ARMVCC_VPTCodes vcc; ///< Vector conditional code for this instruction.
913 bool update_flags; ///< does this insn update flags?
914 bool post_index; ///< only set if writeback is 'True', if 'False' pre-index, otherwise post.
915 arm_mem_bo_opt mem_barrier; ///< Option for some memory barrier instructions
916 // Check ARM_PredBlockMask for encoding details.
917 uint8_t /* ARM_PredBlockMask */ pred_mask; ///< Used by IT/VPT block instructions.
918 /// Number of operands of this instruction,
919 /// or 0 when instruction has no operand.
920 uint8_t op_count;
921 
922 cs_arm_op operands[NUM_ARM_OPS]; ///< operands for this instruction.
923} cs_arm;
924 
925/// ARM instruction
926typedef enum arm_insn {
927 // generated content <ARMGenCSInsnEnum.inc> begin
928 // clang-format off
929 
930 ARM_INS_INVALID,
931 ARM_INS_ASR,
932 ARM_INS_IT,
933 ARM_INS_LDRBT,
934 ARM_INS_LDR,
935 ARM_INS_LDRHT,
936 ARM_INS_LDRSBT,
937 ARM_INS_LDRSHT,
938 ARM_INS_LDRT,
939 ARM_INS_LSL,
940 ARM_INS_LSR,
941 ARM_INS_ROR,
942 ARM_INS_RRX,
943 ARM_INS_STRBT,
944 ARM_INS_STRT,
945 ARM_INS_VLD1,
946 ARM_INS_VLD2,
947 ARM_INS_VLD3,
948 ARM_INS_VLD4,
949 ARM_INS_VST1,
950 ARM_INS_VST2,
951 ARM_INS_VST3,
952 ARM_INS_VST4,
953 ARM_INS_LDRB,
954 ARM_INS_LDRH,
955 ARM_INS_LDRSB,
956 ARM_INS_LDRSH,
957 ARM_INS_MOVS,
958 ARM_INS_MOV,
959 ARM_INS_STRB,
960 ARM_INS_STRH,
961 ARM_INS_STR,
962 ARM_INS_ADC,
963 ARM_INS_ADD,
964 ARM_INS_ADR,
965 ARM_INS_AESD,
966 ARM_INS_AESE,
967 ARM_INS_AESIMC,
968 ARM_INS_AESMC,
969 ARM_INS_AND,
970 ARM_INS_VDOT,
971 ARM_INS_VCVT,
972 ARM_INS_VCVTB,
973 ARM_INS_VCVTT,
974 ARM_INS_BFC,
975 ARM_INS_BFI,
976 ARM_INS_BIC,
977 ARM_INS_BKPT,
978 ARM_INS_BL,
979 ARM_INS_BLX,
980 ARM_INS_BX,
981 ARM_INS_BXJ,
982 ARM_INS_B,
983 ARM_INS_CX1,
984 ARM_INS_CX1A,
985 ARM_INS_CX1D,
986 ARM_INS_CX1DA,
987 ARM_INS_CX2,
988 ARM_INS_CX2A,
989 ARM_INS_CX2D,
990 ARM_INS_CX2DA,
991 ARM_INS_CX3,
992 ARM_INS_CX3A,
993 ARM_INS_CX3D,
994 ARM_INS_CX3DA,
995 ARM_INS_VCX1A,
996 ARM_INS_VCX1,
997 ARM_INS_VCX2A,
998 ARM_INS_VCX2,
999 ARM_INS_VCX3A,
1000 ARM_INS_VCX3,
1001 ARM_INS_CDP,
1002 ARM_INS_CDP2,
1003 ARM_INS_CLREX,
1004 ARM_INS_CLZ,
1005 ARM_INS_CMN,
1006 ARM_INS_CMP,
1007 ARM_INS_CPS,
1008 ARM_INS_CRC32B,
1009 ARM_INS_CRC32CB,
1010 ARM_INS_CRC32CH,
1011 ARM_INS_CRC32CW,
1012 ARM_INS_CRC32H,
1013 ARM_INS_CRC32W,
1014 ARM_INS_DBG,
1015 ARM_INS_DMB,
1016 ARM_INS_DSB,
1017 ARM_INS_EOR,
1018 ARM_INS_ERET,
1019 ARM_INS_VMOV,
1020 ARM_INS_FLDMDBX,
1021 ARM_INS_FLDMIAX,
1022 ARM_INS_VMRS,
1023 ARM_INS_FSTMDBX,
1024 ARM_INS_FSTMIAX,
1025 ARM_INS_HINT,
1026 ARM_INS_HLT,
1027 ARM_INS_HVC,
1028 ARM_INS_ISB,
1029 ARM_INS_LDA,
1030 ARM_INS_LDAB,
1031 ARM_INS_LDAEX,
1032 ARM_INS_LDAEXB,
1033 ARM_INS_LDAEXD,
1034 ARM_INS_LDAEXH,
1035 ARM_INS_LDAH,
1036 ARM_INS_LDC2L,
1037 ARM_INS_LDC2,
1038 ARM_INS_LDCL,
1039 ARM_INS_LDC,
1040 ARM_INS_LDMDA,
1041 ARM_INS_LDMDB,
1042 ARM_INS_LDM,
1043 ARM_INS_LDMIB,
1044 ARM_INS_LDRD,
1045 ARM_INS_LDREX,
1046 ARM_INS_LDREXB,
1047 ARM_INS_LDREXD,
1048 ARM_INS_LDREXH,
1049 ARM_INS_MCR,
1050 ARM_INS_MCR2,
1051 ARM_INS_MCRR,
1052 ARM_INS_MCRR2,
1053 ARM_INS_MLA,
1054 ARM_INS_MLS,
1055 ARM_INS_MOVT,
1056 ARM_INS_MOVW,
1057 ARM_INS_MRC,
1058 ARM_INS_MRC2,
1059 ARM_INS_MRRC,
1060 ARM_INS_MRRC2,
1061 ARM_INS_MRS,
1062 ARM_INS_MSR,
1063 ARM_INS_MUL,
1064 ARM_INS_ASRL,
1065 ARM_INS_DLSTP,
1066 ARM_INS_LCTP,
1067 ARM_INS_LETP,
1068 ARM_INS_LSLL,
1069 ARM_INS_LSRL,
1070 ARM_INS_SQRSHR,
1071 ARM_INS_SQRSHRL,
1072 ARM_INS_SQSHL,
1073 ARM_INS_SQSHLL,
1074 ARM_INS_SRSHR,
1075 ARM_INS_SRSHRL,
1076 ARM_INS_UQRSHL,
1077 ARM_INS_UQRSHLL,
1078 ARM_INS_UQSHL,
1079 ARM_INS_UQSHLL,
1080 ARM_INS_URSHR,
1081 ARM_INS_URSHRL,
1082 ARM_INS_VABAV,
1083 ARM_INS_VABD,
1084 ARM_INS_VABS,
1085 ARM_INS_VADC,
1086 ARM_INS_VADCI,
1087 ARM_INS_VADDLVA,
1088 ARM_INS_VADDLV,
1089 ARM_INS_VADDVA,
1090 ARM_INS_VADDV,
1091 ARM_INS_VADD,
1092 ARM_INS_VAND,
1093 ARM_INS_VBIC,
1094 ARM_INS_VBRSR,
1095 ARM_INS_VCADD,
1096 ARM_INS_VCLS,
1097 ARM_INS_VCLZ,
1098 ARM_INS_VCMLA,
1099 ARM_INS_VCMP,
1100 ARM_INS_VCMUL,
1101 ARM_INS_VCTP,
1102 ARM_INS_VCVTA,
1103 ARM_INS_VCVTM,
1104 ARM_INS_VCVTN,
1105 ARM_INS_VCVTP,
1106 ARM_INS_VDDUP,
1107 ARM_INS_VDUP,
1108 ARM_INS_VDWDUP,
1109 ARM_INS_VEOR,
1110 ARM_INS_VFMAS,
1111 ARM_INS_VFMA,
1112 ARM_INS_VFMS,
1113 ARM_INS_VHADD,
1114 ARM_INS_VHCADD,
1115 ARM_INS_VHSUB,
1116 ARM_INS_VIDUP,
1117 ARM_INS_VIWDUP,
1118 ARM_INS_VLD20,
1119 ARM_INS_VLD21,
1120 ARM_INS_VLD40,
1121 ARM_INS_VLD41,
1122 ARM_INS_VLD42,
1123 ARM_INS_VLD43,
1124 ARM_INS_VLDRB,
1125 ARM_INS_VLDRD,
1126 ARM_INS_VLDRH,
1127 ARM_INS_VLDRW,
1128 ARM_INS_VMAXAV,
1129 ARM_INS_VMAXA,
1130 ARM_INS_VMAXNMAV,
1131 ARM_INS_VMAXNMA,
1132 ARM_INS_VMAXNMV,
1133 ARM_INS_VMAXNM,
1134 ARM_INS_VMAXV,
1135 ARM_INS_VMAX,
1136 ARM_INS_VMINAV,
1137 ARM_INS_VMINA,
1138 ARM_INS_VMINNMAV,
1139 ARM_INS_VMINNMA,
1140 ARM_INS_VMINNMV,
1141 ARM_INS_VMINNM,
1142 ARM_INS_VMINV,
1143 ARM_INS_VMIN,
1144 ARM_INS_VMLADAVA,
1145 ARM_INS_VMLADAVAX,
1146 ARM_INS_VMLADAV,
1147 ARM_INS_VMLADAVX,
1148 ARM_INS_VMLALDAVA,
1149 ARM_INS_VMLALDAVAX,
1150 ARM_INS_VMLALDAV,
1151 ARM_INS_VMLALDAVX,
1152 ARM_INS_VMLAS,
1153 ARM_INS_VMLA,
1154 ARM_INS_VMLSDAVA,
1155 ARM_INS_VMLSDAVAX,
1156 ARM_INS_VMLSDAV,
1157 ARM_INS_VMLSDAVX,
1158 ARM_INS_VMLSLDAVA,
1159 ARM_INS_VMLSLDAVAX,
1160 ARM_INS_VMLSLDAV,
1161 ARM_INS_VMLSLDAVX,
1162 ARM_INS_VMOVLB,
1163 ARM_INS_VMOVLT,
1164 ARM_INS_VMOVNB,
1165 ARM_INS_VMOVNT,
1166 ARM_INS_VMULH,
1167 ARM_INS_VMULLB,
1168 ARM_INS_VMULLT,
1169 ARM_INS_VMUL,
1170 ARM_INS_VMVN,
1171 ARM_INS_VNEG,
1172 ARM_INS_VORN,
1173 ARM_INS_VORR,
1174 ARM_INS_VPNOT,
1175 ARM_INS_VPSEL,
1176 ARM_INS_VPST,
1177 ARM_INS_VPT,
1178 ARM_INS_VQABS,
1179 ARM_INS_VQADD,
1180 ARM_INS_VQDMLADHX,
1181 ARM_INS_VQDMLADH,
1182 ARM_INS_VQDMLAH,
1183 ARM_INS_VQDMLASH,
1184 ARM_INS_VQDMLSDHX,
1185 ARM_INS_VQDMLSDH,
1186 ARM_INS_VQDMULH,
1187 ARM_INS_VQDMULLB,
1188 ARM_INS_VQDMULLT,
1189 ARM_INS_VQMOVNB,
1190 ARM_INS_VQMOVNT,
1191 ARM_INS_VQMOVUNB,
1192 ARM_INS_VQMOVUNT,
1193 ARM_INS_VQNEG,
1194 ARM_INS_VQRDMLADHX,
1195 ARM_INS_VQRDMLADH,
1196 ARM_INS_VQRDMLAH,
1197 ARM_INS_VQRDMLASH,
1198 ARM_INS_VQRDMLSDHX,
1199 ARM_INS_VQRDMLSDH,
1200 ARM_INS_VQRDMULH,
1201 ARM_INS_VQRSHL,
1202 ARM_INS_VQRSHRNB,
1203 ARM_INS_VQRSHRNT,
1204 ARM_INS_VQRSHRUNB,
1205 ARM_INS_VQRSHRUNT,
1206 ARM_INS_VQSHLU,
1207 ARM_INS_VQSHL,
1208 ARM_INS_VQSHRNB,
1209 ARM_INS_VQSHRNT,
1210 ARM_INS_VQSHRUNB,
1211 ARM_INS_VQSHRUNT,
1212 ARM_INS_VQSUB,
1213 ARM_INS_VREV16,
1214 ARM_INS_VREV32,
1215 ARM_INS_VREV64,
1216 ARM_INS_VRHADD,
1217 ARM_INS_VRINTA,
1218 ARM_INS_VRINTM,
1219 ARM_INS_VRINTN,
1220 ARM_INS_VRINTP,
1221 ARM_INS_VRINTX,
1222 ARM_INS_VRINTZ,
1223 ARM_INS_VRMLALDAVHA,
1224 ARM_INS_VRMLALDAVHAX,
1225 ARM_INS_VRMLALDAVH,
1226 ARM_INS_VRMLALDAVHX,
1227 ARM_INS_VRMLSLDAVHA,
1228 ARM_INS_VRMLSLDAVHAX,
1229 ARM_INS_VRMLSLDAVH,
1230 ARM_INS_VRMLSLDAVHX,
1231 ARM_INS_VRMULH,
1232 ARM_INS_VRSHL,
1233 ARM_INS_VRSHRNB,
1234 ARM_INS_VRSHRNT,
1235 ARM_INS_VRSHR,
1236 ARM_INS_VSBC,
1237 ARM_INS_VSBCI,
1238 ARM_INS_VSHLC,
1239 ARM_INS_VSHLLB,
1240 ARM_INS_VSHLLT,
1241 ARM_INS_VSHL,
1242 ARM_INS_VSHRNB,
1243 ARM_INS_VSHRNT,
1244 ARM_INS_VSHR,
1245 ARM_INS_VSLI,
1246 ARM_INS_VSRI,
1247 ARM_INS_VST20,
1248 ARM_INS_VST21,
1249 ARM_INS_VST40,
1250 ARM_INS_VST41,
1251 ARM_INS_VST42,
1252 ARM_INS_VST43,
1253 ARM_INS_VSTRB,
1254 ARM_INS_VSTRD,
1255 ARM_INS_VSTRH,
1256 ARM_INS_VSTRW,
1257 ARM_INS_VSUB,
1258 ARM_INS_WLSTP,
1259 ARM_INS_MVN,
1260 ARM_INS_ORR,
1261 ARM_INS_PKHBT,
1262 ARM_INS_PKHTB,
1263 ARM_INS_PLDW,
1264 ARM_INS_PLD,
1265 ARM_INS_PLI,
1266 ARM_INS_QADD,
1267 ARM_INS_QADD16,
1268 ARM_INS_QADD8,
1269 ARM_INS_QASX,
1270 ARM_INS_QDADD,
1271 ARM_INS_QDSUB,
1272 ARM_INS_QSAX,
1273 ARM_INS_QSUB,
1274 ARM_INS_QSUB16,
1275 ARM_INS_QSUB8,
1276 ARM_INS_RBIT,
1277 ARM_INS_REV,
1278 ARM_INS_REV16,
1279 ARM_INS_REVSH,
1280 ARM_INS_RFEDA,
1281 ARM_INS_RFEDB,
1282 ARM_INS_RFEIA,
1283 ARM_INS_RFEIB,
1284 ARM_INS_RSB,
1285 ARM_INS_RSC,
1286 ARM_INS_SADD16,
1287 ARM_INS_SADD8,
1288 ARM_INS_SASX,
1289 ARM_INS_SB,
1290 ARM_INS_SBC,
1291 ARM_INS_SBFX,
1292 ARM_INS_SDIV,
1293 ARM_INS_SEL,
1294 ARM_INS_SETEND,
1295 ARM_INS_SETPAN,
1296 ARM_INS_SHA1C,
1297 ARM_INS_SHA1H,
1298 ARM_INS_SHA1M,
1299 ARM_INS_SHA1P,
1300 ARM_INS_SHA1SU0,
1301 ARM_INS_SHA1SU1,
1302 ARM_INS_SHA256H,
1303 ARM_INS_SHA256H2,
1304 ARM_INS_SHA256SU0,
1305 ARM_INS_SHA256SU1,
1306 ARM_INS_SHADD16,
1307 ARM_INS_SHADD8,
1308 ARM_INS_SHASX,
1309 ARM_INS_SHSAX,
1310 ARM_INS_SHSUB16,
1311 ARM_INS_SHSUB8,
1312 ARM_INS_SMC,
1313 ARM_INS_SMLABB,
1314 ARM_INS_SMLABT,
1315 ARM_INS_SMLAD,
1316 ARM_INS_SMLADX,
1317 ARM_INS_SMLAL,
1318 ARM_INS_SMLALBB,
1319 ARM_INS_SMLALBT,
1320 ARM_INS_SMLALD,
1321 ARM_INS_SMLALDX,
1322 ARM_INS_SMLALTB,
1323 ARM_INS_SMLALTT,
1324 ARM_INS_SMLATB,
1325 ARM_INS_SMLATT,
1326 ARM_INS_SMLAWB,
1327 ARM_INS_SMLAWT,
1328 ARM_INS_SMLSD,
1329 ARM_INS_SMLSDX,
1330 ARM_INS_SMLSLD,
1331 ARM_INS_SMLSLDX,
1332 ARM_INS_SMMLA,
1333 ARM_INS_SMMLAR,
1334 ARM_INS_SMMLS,
1335 ARM_INS_SMMLSR,
1336 ARM_INS_SMMUL,
1337 ARM_INS_SMMULR,
1338 ARM_INS_SMUAD,
1339 ARM_INS_SMUADX,
1340 ARM_INS_SMULBB,
1341 ARM_INS_SMULBT,
1342 ARM_INS_SMULL,
1343 ARM_INS_SMULTB,
1344 ARM_INS_SMULTT,
1345 ARM_INS_SMULWB,
1346 ARM_INS_SMULWT,
1347 ARM_INS_SMUSD,
1348 ARM_INS_SMUSDX,
1349 ARM_INS_SRSDA,
1350 ARM_INS_SRSDB,
1351 ARM_INS_SRSIA,
1352 ARM_INS_SRSIB,
1353 ARM_INS_SSAT,
1354 ARM_INS_SSAT16,
1355 ARM_INS_SSAX,
1356 ARM_INS_SSUB16,
1357 ARM_INS_SSUB8,
1358 ARM_INS_STC2L,
1359 ARM_INS_STC2,
1360 ARM_INS_STCL,
1361 ARM_INS_STC,
1362 ARM_INS_STL,
1363 ARM_INS_STLB,
1364 ARM_INS_STLEX,
1365 ARM_INS_STLEXB,
1366 ARM_INS_STLEXD,
1367 ARM_INS_STLEXH,
1368 ARM_INS_STLH,
1369 ARM_INS_STMDA,
1370 ARM_INS_STMDB,
1371 ARM_INS_STM,
1372 ARM_INS_STMIB,
1373 ARM_INS_STRD,
1374 ARM_INS_STREX,
1375 ARM_INS_STREXB,
1376 ARM_INS_STREXD,
1377 ARM_INS_STREXH,
1378 ARM_INS_STRHT,
1379 ARM_INS_SUB,
1380 ARM_INS_SVC,
1381 ARM_INS_SWP,
1382 ARM_INS_SWPB,
1383 ARM_INS_SXTAB,
1384 ARM_INS_SXTAB16,
1385 ARM_INS_SXTAH,
1386 ARM_INS_SXTB,
1387 ARM_INS_SXTB16,
1388 ARM_INS_SXTH,
1389 ARM_INS_TEQ,
1390 ARM_INS_TRAP,
1391 ARM_INS_TSB,
1392 ARM_INS_TST,
1393 ARM_INS_UADD16,
1394 ARM_INS_UADD8,
1395 ARM_INS_UASX,
1396 ARM_INS_UBFX,
1397 ARM_INS_UDF,
1398 ARM_INS_UDIV,
1399 ARM_INS_UHADD16,
1400 ARM_INS_UHADD8,
1401 ARM_INS_UHASX,
1402 ARM_INS_UHSAX,
1403 ARM_INS_UHSUB16,
1404 ARM_INS_UHSUB8,
1405 ARM_INS_UMAAL,
1406 ARM_INS_UMLAL,
1407 ARM_INS_UMULL,
1408 ARM_INS_UQADD16,
1409 ARM_INS_UQADD8,
1410 ARM_INS_UQASX,
1411 ARM_INS_UQSAX,
1412 ARM_INS_UQSUB16,
1413 ARM_INS_UQSUB8,
1414 ARM_INS_USAD8,
1415 ARM_INS_USADA8,
1416 ARM_INS_USAT,
1417 ARM_INS_USAT16,
1418 ARM_INS_USAX,
1419 ARM_INS_USUB16,
1420 ARM_INS_USUB8,
1421 ARM_INS_UXTAB,
1422 ARM_INS_UXTAB16,
1423 ARM_INS_UXTAH,
1424 ARM_INS_UXTB,
1425 ARM_INS_UXTB16,
1426 ARM_INS_UXTH,
1427 ARM_INS_VABAL,
1428 ARM_INS_VABA,
1429 ARM_INS_VABDL,
1430 ARM_INS_VACGE,
1431 ARM_INS_VACGT,
1432 ARM_INS_VADDHN,
1433 ARM_INS_VADDL,
1434 ARM_INS_VADDW,
1435 ARM_INS_VFMAB,
1436 ARM_INS_VFMAT,
1437 ARM_INS_VBIF,
1438 ARM_INS_VBIT,
1439 ARM_INS_VBSL,
1440 ARM_INS_VCEQ,
1441 ARM_INS_VCGE,
1442 ARM_INS_VCGT,
1443 ARM_INS_VCLE,
1444 ARM_INS_VCLT,
1445 ARM_INS_VCMPE,
1446 ARM_INS_VCNT,
1447 ARM_INS_VDIV,
1448 ARM_INS_VEXT,
1449 ARM_INS_VFMAL,
1450 ARM_INS_VFMSL,
1451 ARM_INS_VFNMA,
1452 ARM_INS_VFNMS,
1453 ARM_INS_VINS,
1454 ARM_INS_VJCVT,
1455 ARM_INS_VLDMDB,
1456 ARM_INS_VLDMIA,
1457 ARM_INS_VLDR,
1458 ARM_INS_VLLDM,
1459 ARM_INS_VLSTM,
1460 ARM_INS_VMLAL,
1461 ARM_INS_VMLS,
1462 ARM_INS_VMLSL,
1463 ARM_INS_VMMLA,
1464 ARM_INS_VMOVX,
1465 ARM_INS_VMOVL,
1466 ARM_INS_VMOVN,
1467 ARM_INS_VMSR,
1468 ARM_INS_VMULL,
1469 ARM_INS_VNMLA,
1470 ARM_INS_VNMLS,
1471 ARM_INS_VNMUL,
1472 ARM_INS_VPADAL,
1473 ARM_INS_VPADDL,
1474 ARM_INS_VPADD,
1475 ARM_INS_VPMAX,
1476 ARM_INS_VPMIN,
1477 ARM_INS_VQDMLAL,
1478 ARM_INS_VQDMLSL,
1479 ARM_INS_VQDMULL,
1480 ARM_INS_VQMOVUN,
1481 ARM_INS_VQMOVN,
1482 ARM_INS_VQRDMLSH,
1483 ARM_INS_VQRSHRN,
1484 ARM_INS_VQRSHRUN,
1485 ARM_INS_VQSHRN,
1486 ARM_INS_VQSHRUN,
1487 ARM_INS_VRADDHN,
1488 ARM_INS_VRECPE,
1489 ARM_INS_VRECPS,
1490 ARM_INS_VRINTR,
1491 ARM_INS_VRSHRN,
1492 ARM_INS_VRSQRTE,
1493 ARM_INS_VRSQRTS,
1494 ARM_INS_VRSRA,
1495 ARM_INS_VRSUBHN,
1496 ARM_INS_VSCCLRM,
1497 ARM_INS_VSDOT,
1498 ARM_INS_VSELEQ,
1499 ARM_INS_VSELGE,
1500 ARM_INS_VSELGT,
1501 ARM_INS_VSELVS,
1502 ARM_INS_VSHLL,
1503 ARM_INS_VSHRN,
1504 ARM_INS_VSMMLA,
1505 ARM_INS_VSQRT,
1506 ARM_INS_VSRA,
1507 ARM_INS_VSTMDB,
1508 ARM_INS_VSTMIA,
1509 ARM_INS_VSTR,
1510 ARM_INS_VSUBHN,
1511 ARM_INS_VSUBL,
1512 ARM_INS_VSUBW,
1513 ARM_INS_VSUDOT,
1514 ARM_INS_VSWP,
1515 ARM_INS_VTBL,
1516 ARM_INS_VTBX,
1517 ARM_INS_VCVTR,
1518 ARM_INS_VTRN,
1519 ARM_INS_VTST,
1520 ARM_INS_VUDOT,
1521 ARM_INS_VUMMLA,
1522 ARM_INS_VUSDOT,
1523 ARM_INS_VUSMMLA,
1524 ARM_INS_VUZP,
1525 ARM_INS_VZIP,
1526 ARM_INS_ADDW,
1527 ARM_INS_AUT,
1528 ARM_INS_AUTG,
1529 ARM_INS_BFL,
1530 ARM_INS_BFLX,
1531 ARM_INS_BF,
1532 ARM_INS_BFCSEL,
1533 ARM_INS_BFX,
1534 ARM_INS_BTI,
1535 ARM_INS_BXAUT,
1536 ARM_INS_CLRM,
1537 ARM_INS_CSEL,
1538 ARM_INS_CSINC,
1539 ARM_INS_CSINV,
1540 ARM_INS_CSNEG,
1541 ARM_INS_DCPS1,
1542 ARM_INS_DCPS2,
1543 ARM_INS_DCPS3,
1544 ARM_INS_DLS,
1545 ARM_INS_LE,
1546 ARM_INS_ORN,
1547 ARM_INS_PAC,
1548 ARM_INS_PACBTI,
1549 ARM_INS_PACG,
1550 ARM_INS_SG,
1551 ARM_INS_SUBS,
1552 ARM_INS_SUBW,
1553 ARM_INS_TBB,
1554 ARM_INS_TBH,
1555 ARM_INS_TT,
1556 ARM_INS_TTA,
1557 ARM_INS_TTAT,
1558 ARM_INS_TTT,
1559 ARM_INS_WLS,
1560 ARM_INS_BLXNS,
1561 ARM_INS_BXNS,
1562 ARM_INS_CBNZ,
1563 ARM_INS_CBZ,
1564 ARM_INS_POP,
1565 ARM_INS_PUSH,
1566 ARM_INS___BRKDIV0,
1567 
1568 // clang-format on
1569 // generated content <ARMGenCSInsnEnum.inc> end
1570 
1571 ARM_INS_ENDING, // <-- mark the end of the list of instructions
1572 
1573 ARM_INS_ALIAS_BEGIN,
1574 // generated content <ARMGenCSAliasEnum.inc> begin
1575 // clang-format off
1576 
1577 ARM_INS_ALIAS_VMOV, // Real instr.: ARM_MVE_VORR
1578 ARM_INS_ALIAS_NOP, // Real instr.: ARM_HINT
1579 ARM_INS_ALIAS_YIELD, // Real instr.: ARM_HINT
1580 ARM_INS_ALIAS_WFE, // Real instr.: ARM_HINT
1581 ARM_INS_ALIAS_WFI, // Real instr.: ARM_HINT
1582 ARM_INS_ALIAS_SEV, // Real instr.: ARM_HINT
1583 ARM_INS_ALIAS_SEVL, // Real instr.: ARM_HINT
1584 ARM_INS_ALIAS_ESB, // Real instr.: ARM_HINT
1585 ARM_INS_ALIAS_CSDB, // Real instr.: ARM_HINT
1586 ARM_INS_ALIAS_CLRBHB, // Real instr.: ARM_HINT
1587 ARM_INS_ALIAS_PACBTI, // Real instr.: ARM_t2HINT
1588 ARM_INS_ALIAS_BTI, // Real instr.: ARM_t2HINT
1589 ARM_INS_ALIAS_PAC, // Real instr.: ARM_t2HINT
1590 ARM_INS_ALIAS_AUT, // Real instr.: ARM_t2HINT
1591 ARM_INS_ALIAS_SSBB, // Real instr.: ARM_t2DSB
1592 ARM_INS_ALIAS_PSSBB, // Real instr.: ARM_t2DSB
1593 ARM_INS_ALIAS_DFB, // Real instr.: ARM_t2DSB
1594 ARM_INS_ALIAS_CSETM, // Real instr.: ARM_t2CSINV
1595 ARM_INS_ALIAS_CSET, // Real instr.: ARM_t2CSINC
1596 ARM_INS_ALIAS_CINC, // Real instr.: ARM_t2CSINC
1597 ARM_INS_ALIAS_CINV, // Real instr.: ARM_t2CSINV
1598 ARM_INS_ALIAS_CNEG, // Real instr.: ARM_t2CSNEG
1599 ARM_INS_ALIAS_VMLAV, // Real instr.: ARM_MVE_VMLADAVs8
1600 ARM_INS_ALIAS_VMLAVA, // Real instr.: ARM_MVE_VMLADAVas8
1601 ARM_INS_ALIAS_VRMLALVH, // Real instr.: ARM_MVE_VRMLALDAVHs32
1602 ARM_INS_ALIAS_VRMLALVHA, // Real instr.: ARM_MVE_VRMLALDAVHas32
1603 ARM_INS_ALIAS_VMLALV, // Real instr.: ARM_MVE_VMLALDAVs16
1604 ARM_INS_ALIAS_VMLALVA, // Real instr.: ARM_MVE_VMLALDAVas16
1605 ARM_INS_ALIAS_VBIC, // Real instr.: ARM_MVE_VBIC
1606 ARM_INS_ALIAS_VEOR, // Real instr.: ARM_MVE_VEOR
1607 ARM_INS_ALIAS_VORN, // Real instr.: ARM_MVE_VORN
1608 ARM_INS_ALIAS_VORR, // Real instr.: ARM_MVE_VORR
1609 ARM_INS_ALIAS_VAND, // Real instr.: ARM_MVE_VAND
1610 ARM_INS_ALIAS_VPSEL, // Real instr.: ARM_MVE_VPSEL
1611 ARM_INS_ALIAS_ERET, // Real instr.: ARM_t2SUBS_PC_LR
1612 
1613 // clang-format on
1614 // generated content <ARMGenCSAliasEnum.inc> end
1615 
1616 // Hardcoded in LLVM printer
1617 ARM_INS_ALIAS_ASR,
1618 ARM_INS_ALIAS_LSL,
1619 ARM_INS_ALIAS_LSR,
1620 ARM_INS_ALIAS_ROR,
1621 ARM_INS_ALIAS_RRX,
1622 ARM_INS_ALIAS_UXTW,
1623 ARM_INS_ALIAS_LDM,
1624 ARM_INS_ALIAS_POP,
1625 ARM_INS_ALIAS_PUSH,
1626 ARM_INS_ALIAS_POPW,
1627 ARM_INS_ALIAS_PUSHW,
1628 ARM_INS_ALIAS_VPOP,
1629 ARM_INS_ALIAS_VPUSH,
1630 
1631 ARM_INS_ALIAS_END,
1632} arm_insn;
1633 
1634/// Group of ARM instructions
1635typedef enum arm_insn_group {
1636 ARM_GRP_INVALID = 0, ///< = CS_GRP_INVALID
1637 
1638 // Generic groups
1639 // all jump instructions (conditional+direct+indirect jumps)
1640 ARM_GRP_JUMP, ///< = CS_GRP_JUMP
1641 ARM_GRP_CALL, ///< = CS_GRP_CALL
1642 ARM_GRP_RET, ///< = CS_GRP_RET
1643 ARM_GRP_INT = 4, ///< = CS_GRP_INT
1644 ARM_GRP_PRIVILEGE = 6, ///< = CS_GRP_PRIVILEGE
1645 ARM_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE
1646 
1647 // Architecture-specific groups
1648 // generated content <ARMGenCSFeatureEnum.inc> begin
1649 // clang-format off
1650 
1651 ARM_FEATURE_HASV4T = 128,
1652 ARM_FEATURE_HASV5T,
1653 ARM_FEATURE_HASV5TE,
1654 ARM_FEATURE_HASV6,
1655 ARM_FEATURE_HASV6M,
1656 ARM_FEATURE_HASV8MBASELINE,
1657 ARM_FEATURE_HASV8MMAINLINE,
1658 ARM_FEATURE_HASV8_1MMAINLINE,
1659 ARM_FEATURE_HASMVEINT,
1660 ARM_FEATURE_HASMVEFLOAT,
1661 ARM_FEATURE_HASCDE,
1662 ARM_FEATURE_HASFPREGS,
1663 ARM_FEATURE_HASFPREGS16,
1664 ARM_FEATURE_HASNOFPREGS16,
1665 ARM_FEATURE_HASFPREGS64,
1666 ARM_FEATURE_HASFPREGSV8_1M,
1667 ARM_FEATURE_HASV6T2,
1668 ARM_FEATURE_HASV6K,
1669 ARM_FEATURE_HASV7,
1670 ARM_FEATURE_HASV8,
1671 ARM_FEATURE_PREV8,
1672 ARM_FEATURE_HASV8_1A,
1673 ARM_FEATURE_HASV8_2A,
1674 ARM_FEATURE_HASV8_3A,
1675 ARM_FEATURE_HASV8_4A,
1676 ARM_FEATURE_HASV8_5A,
1677 ARM_FEATURE_HASV8_6A,
1678 ARM_FEATURE_HASV8_7A,
1679 ARM_FEATURE_HASVFP2,
1680 ARM_FEATURE_HASVFP3,
1681 ARM_FEATURE_HASVFP4,
1682 ARM_FEATURE_HASDPVFP,
1683 ARM_FEATURE_HASFPARMV8,
1684 ARM_FEATURE_HASNEON,
1685 ARM_FEATURE_HASSHA2,
1686 ARM_FEATURE_HASAES,
1687 ARM_FEATURE_HASCRYPTO,
1688 ARM_FEATURE_HASDOTPROD,
1689 ARM_FEATURE_HASCRC,
1690 ARM_FEATURE_HASRAS,
1691 ARM_FEATURE_HASLOB,
1692 ARM_FEATURE_HASPACBTI,
1693 ARM_FEATURE_HASFP16,
1694 ARM_FEATURE_HASFULLFP16,
1695 ARM_FEATURE_HASFP16FML,
1696 ARM_FEATURE_HASBF16,
1697 ARM_FEATURE_HASMATMULINT8,
1698 ARM_FEATURE_HASDIVIDEINTHUMB,
1699 ARM_FEATURE_HASDIVIDEINARM,
1700 ARM_FEATURE_HASDSP,
1701 ARM_FEATURE_HASDB,
1702 ARM_FEATURE_HASDFB,
1703 ARM_FEATURE_HASV7CLREX,
1704 ARM_FEATURE_HASACQUIRERELEASE,
1705 ARM_FEATURE_HASMP,
1706 ARM_FEATURE_HASVIRTUALIZATION,
1707 ARM_FEATURE_HASTRUSTZONE,
1708 ARM_FEATURE_HAS8MSECEXT,
1709 ARM_FEATURE_ISTHUMB,
1710 ARM_FEATURE_ISTHUMB2,
1711 ARM_FEATURE_ISMCLASS,
1712 ARM_FEATURE_ISNOTMCLASS,
1713 ARM_FEATURE_ISARM,
1714 ARM_FEATURE_USENACLTRAP,
1715 ARM_FEATURE_USENEGATIVEIMMEDIATES,
1716 ARM_FEATURE_HASSB,
1717 ARM_FEATURE_HASCLRBHB,
1718 
1719 // clang-format on
1720 // generated content <ARMGenCSFeatureEnum.inc> end
1721 
1722 ARM_GRP_ENDING,
1723} arm_insn_group;
1724 
1725#ifdef CAPSTONE_ARM_COMPAT_HEADER
1726#define arm_cc ARMCC_CondCodes
1727#define ARM_CC_EQ ARMCC_EQ
1728#define ARM_CC_NE ARMCC_NE
1729#define ARM_CC_HS ARMCC_HS
1730#define ARM_CC_LO ARMCC_LO
1731#define ARM_CC_MI ARMCC_MI
1732#define ARM_CC_PL ARMCC_PL
1733#define ARM_CC_VS ARMCC_VS
1734#define ARM_CC_VC ARMCC_VC
1735#define ARM_CC_HI ARMCC_HI
1736#define ARM_CC_LS ARMCC_LS
1737#define ARM_CC_GE ARMCC_GE
1738#define ARM_CC_LT ARMCC_LT
1739#define ARM_CC_GT ARMCC_GT
1740#define ARM_CC_LE ARMCC_LE
1741#define ARM_CC_AL ARMCC_AL
1742#define ARM_CC_INVALID ARMCC_Invalid
1743#endif
1744 
1745#ifdef __cplusplus
1746}
1747#endif
1748 
1749#endif
1750