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DyMain/include/capstone/alpha.h

Hermes / DyMain / include / capstone / alpha.h

1	#ifndef CAPSTONE_ALPHA_H
2	#define CAPSTONE_ALPHA_H
3
4	/* Capstone Disassembly Engine */
5	/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014 */
6
7	#ifdef __cplusplus
8	extern "C" {
9	#endif
10
11	#if !defined(_MSC_VER) \|\| !defined(_KERNEL_MODE)
12	#include <stdint.h>
13	#endif
14
15	#include "cs_operand.h"
16	#include "platform.h"
17
18	#ifdef _MSC_VER
19	#pragma warning(disable : 4201)
20	#endif
21
22	#define NUM_ALPHA_OPS 3
23
24	//> Operand type for instruction's operands
25	typedef enum alpha_op_type {
26	ALPHA_OP_INVALID = CS_OP_INVALID, ///< CS_OP_INVALID (Uninitialized).
27	ALPHA_OP_REG = CS_OP_REG, ///< CS_OP_REG (Register operand).
28	ALPHA_OP_IMM = CS_OP_IMM, ///< CS_OP_IMM (Immediate operand).
29	} alpha_op_type;
30
31	// Instruction operand
32	typedef struct cs_alpha_op {
33	alpha_op_type type; // operand type
34	union {
35	unsigned int reg; // register value for REG operand
36	int32_t imm; // immediate value for IMM operand
37	};
38	enum cs_ac_type access;
39	} cs_alpha_op;
40
41	// Instruction structure
42	typedef struct cs_alpha {
43	// Number of operands of this instruction,
44	// or 0 when instruction has no operand.
45	uint8_t op_count;
46	cs_alpha_op operands[NUM_ALPHA_OPS]; // operands for this instruction.
47	} cs_alpha;
48
49
50	//> Alpha registers
51	typedef enum alpha_reg {
52	// generated content <AlphaGenCSRegEnum.inc> begin
53	// clang-format off
54
55	Alpha_REG_INVALID = 0,
56	Alpha_REG_F0 = 1,
57	Alpha_REG_F1 = 2,
58	Alpha_REG_F2 = 3,
59	Alpha_REG_F3 = 4,
60	Alpha_REG_F4 = 5,
61	Alpha_REG_F5 = 6,
62	Alpha_REG_F6 = 7,
63	Alpha_REG_F7 = 8,
64	Alpha_REG_F8 = 9,
65	Alpha_REG_F9 = 10,
66	Alpha_REG_F10 = 11,
67	Alpha_REG_F11 = 12,
68	Alpha_REG_F12 = 13,
69	Alpha_REG_F13 = 14,
70	Alpha_REG_F14 = 15,
71	Alpha_REG_F15 = 16,
72	Alpha_REG_F16 = 17,
73	Alpha_REG_F17 = 18,
74	Alpha_REG_F18 = 19,
75	Alpha_REG_F19 = 20,
76	Alpha_REG_F20 = 21,
77	Alpha_REG_F21 = 22,
78	Alpha_REG_F22 = 23,
79	Alpha_REG_F23 = 24,
80	Alpha_REG_F24 = 25,
81	Alpha_REG_F25 = 26,
82	Alpha_REG_F26 = 27,
83	Alpha_REG_F27 = 28,
84	Alpha_REG_F28 = 29,
85	Alpha_REG_F29 = 30,
86	Alpha_REG_F30 = 31,
87	Alpha_REG_F31 = 32,
88	Alpha_REG_R0 = 33,
89	Alpha_REG_R1 = 34,
90	Alpha_REG_R2 = 35,
91	Alpha_REG_R3 = 36,
92	Alpha_REG_R4 = 37,
93	Alpha_REG_R5 = 38,
94	Alpha_REG_R6 = 39,
95	Alpha_REG_R7 = 40,
96	Alpha_REG_R8 = 41,
97	Alpha_REG_R9 = 42,
98	Alpha_REG_R10 = 43,
99	Alpha_REG_R11 = 44,
100	Alpha_REG_R12 = 45,
101	Alpha_REG_R13 = 46,
102	Alpha_REG_R14 = 47,
103	Alpha_REG_R15 = 48,
104	Alpha_REG_R16 = 49,
105	Alpha_REG_R17 = 50,
106	Alpha_REG_R18 = 51,
107	Alpha_REG_R19 = 52,
108	Alpha_REG_R20 = 53,
109	Alpha_REG_R21 = 54,
110	Alpha_REG_R22 = 55,
111	Alpha_REG_R23 = 56,
112	Alpha_REG_R24 = 57,
113	Alpha_REG_R25 = 58,
114	Alpha_REG_R26 = 59,
115	Alpha_REG_R27 = 60,
116	Alpha_REG_R28 = 61,
117	Alpha_REG_R29 = 62,
118	Alpha_REG_R30 = 63,
119	Alpha_REG_R31 = 64,
120	Alpha_REG_ENDING, // 65
121
122	// clang-format on
123	// generated content <AlphaGenCSRegEnum.inc> end
124	} alpha_reg;
125
126	//> Alpha instruction
127	typedef enum alpha_insn {
128	// generated content <AlphaGenCSInsnEnum.inc:GET_INSTR_ENUM> begin
129	// clang-format off
130
131	Alpha_INS_INVALID,
132	Alpha_INS_ADDL,
133	Alpha_INS_ADDQ,
134	Alpha_INS_ADDSsSU,
135	Alpha_INS_ADDTsSU,
136	Alpha_INS_AND,
137	Alpha_INS_BEQ,
138	Alpha_INS_BGE,
139	Alpha_INS_BGT,
140	Alpha_INS_BIC,
141	Alpha_INS_BIS,
142	Alpha_INS_BLBC,
143	Alpha_INS_BLBS,
144	Alpha_INS_BLE,
145	Alpha_INS_BLT,
146	Alpha_INS_BNE,
147	Alpha_INS_BR,
148	Alpha_INS_BSR,
149	Alpha_INS_CMOVEQ,
150	Alpha_INS_CMOVGE,
151	Alpha_INS_CMOVGT,
152	Alpha_INS_CMOVLBC,
153	Alpha_INS_CMOVLBS,
154	Alpha_INS_CMOVLE,
155	Alpha_INS_CMOVLT,
156	Alpha_INS_CMOVNE,
157	Alpha_INS_CMPBGE,
158	Alpha_INS_CMPEQ,
159	Alpha_INS_CMPLE,
160	Alpha_INS_CMPLT,
161	Alpha_INS_CMPTEQsSU,
162	Alpha_INS_CMPTLEsSU,
163	Alpha_INS_CMPTLTsSU,
164	Alpha_INS_CMPTUNsSU,
165	Alpha_INS_CMPULE,
166	Alpha_INS_CMPULT,
167	Alpha_INS_COND_BRANCH,
168	Alpha_INS_CPYSE,
169	Alpha_INS_CPYSN,
170	Alpha_INS_CPYS,
171	Alpha_INS_CTLZ,
172	Alpha_INS_CTPOP,
173	Alpha_INS_CTTZ,
174	Alpha_INS_CVTQSsSUI,
175	Alpha_INS_CVTQTsSUI,
176	Alpha_INS_CVTSTsS,
177	Alpha_INS_CVTTQsSVC,
178	Alpha_INS_CVTTSsSUI,
179	Alpha_INS_DIVSsSU,
180	Alpha_INS_DIVTsSU,
181	Alpha_INS_ECB,
182	Alpha_INS_EQV,
183	Alpha_INS_EXCB,
184	Alpha_INS_EXTBL,
185	Alpha_INS_EXTLH,
186	Alpha_INS_EXTLL,
187	Alpha_INS_EXTQH,
188	Alpha_INS_EXTQL,
189	Alpha_INS_EXTWH,
190	Alpha_INS_EXTWL,
191	Alpha_INS_FBEQ,
192	Alpha_INS_FBGE,
193	Alpha_INS_FBGT,
194	Alpha_INS_FBLE,
195	Alpha_INS_FBLT,
196	Alpha_INS_FBNE,
197	Alpha_INS_FCMOVEQ,
198	Alpha_INS_FCMOVGE,
199	Alpha_INS_FCMOVGT,
200	Alpha_INS_FCMOVLE,
201	Alpha_INS_FCMOVLT,
202	Alpha_INS_FCMOVNE,
203	Alpha_INS_FETCH,
204	Alpha_INS_FETCH_M,
205	Alpha_INS_FTOIS,
206	Alpha_INS_FTOIT,
207	Alpha_INS_INSBL,
208	Alpha_INS_INSLH,
209	Alpha_INS_INSLL,
210	Alpha_INS_INSQH,
211	Alpha_INS_INSQL,
212	Alpha_INS_INSWH,
213	Alpha_INS_INSWL,
214	Alpha_INS_ITOFS,
215	Alpha_INS_ITOFT,
216	Alpha_INS_JMP,
217	Alpha_INS_JSR,
218	Alpha_INS_JSR_COROUTINE,
219	Alpha_INS_LDA,
220	Alpha_INS_LDAH,
221	Alpha_INS_LDBU,
222	Alpha_INS_LDL,
223	Alpha_INS_LDL_L,
224	Alpha_INS_LDQ,
225	Alpha_INS_LDQ_L,
226	Alpha_INS_LDQ_U,
227	Alpha_INS_LDS,
228	Alpha_INS_LDT,
229	Alpha_INS_LDWU,
230	Alpha_INS_MB,
231	Alpha_INS_MSKBL,
232	Alpha_INS_MSKLH,
233	Alpha_INS_MSKLL,
234	Alpha_INS_MSKQH,
235	Alpha_INS_MSKQL,
236	Alpha_INS_MSKWH,
237	Alpha_INS_MSKWL,
238	Alpha_INS_MULL,
239	Alpha_INS_MULQ,
240	Alpha_INS_MULSsSU,
241	Alpha_INS_MULTsSU,
242	Alpha_INS_ORNOT,
243	Alpha_INS_RC,
244	Alpha_INS_RET,
245	Alpha_INS_RPCC,
246	Alpha_INS_RS,
247	Alpha_INS_S4ADDL,
248	Alpha_INS_S4ADDQ,
249	Alpha_INS_S4SUBL,
250	Alpha_INS_S4SUBQ,
251	Alpha_INS_S8ADDL,
252	Alpha_INS_S8ADDQ,
253	Alpha_INS_S8SUBL,
254	Alpha_INS_S8SUBQ,
255	Alpha_INS_SEXTB,
256	Alpha_INS_SEXTW,
257	Alpha_INS_SLL,
258	Alpha_INS_SQRTSsSU,
259	Alpha_INS_SQRTTsSU,
260	Alpha_INS_SRA,
261	Alpha_INS_SRL,
262	Alpha_INS_STB,
263	Alpha_INS_STL,
264	Alpha_INS_STL_C,
265	Alpha_INS_STQ,
266	Alpha_INS_STQ_C,
267	Alpha_INS_STQ_U,
268	Alpha_INS_STS,
269	Alpha_INS_STT,
270	Alpha_INS_STW,
271	Alpha_INS_SUBL,
272	Alpha_INS_SUBQ,
273	Alpha_INS_SUBSsSU,
274	Alpha_INS_SUBTsSU,
275	Alpha_INS_TRAPB,
276	Alpha_INS_UMULH,
277	Alpha_INS_WH64,
278	Alpha_INS_WH64EN,
279	Alpha_INS_WMB,
280	Alpha_INS_XOR,
281	Alpha_INS_ZAPNOT,
282
283	// clang-format on
284	// generated content <AlphaGenCSInsnEnum.inc:GET_INSTR_ENUM> end
285	ALPHA_INS_ENDING, // <-- mark the end of the list of instructions
286	} alpha_insn;
287
288	//> Group of Alpha instructions
289	typedef enum alpha_insn_group {
290	Alpha_GRP_INVALID, ///< = CS_GRP_INVALID
291	//> Generic groups
292	Alpha_GRP_CALL, ///< = CS_GRP_CALL
293	Alpha_GRP_JUMP, ///< = CS_GRP_JUMP
294	Alpha_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE
295	Alpha_GRP_ENDING, ///< = mark the end of the list of groups
296	} alpha_insn_group;
297
298	#ifdef __cplusplus
299	}
300	#endif
301
302	#endif
303

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